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SN74LVC2G02
SCES194N – APRIL 1999 – REVISED MAY 2019
SN74LVC2G02 Dual 2-Input Positive-NOR Gate
1 Features
3 Description
•
This dual 2-input positive-NOR gate is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ package
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
Max tpd of 4.9 ns at 3.3 V
Low power consumption, 10-μA Max ICC
±24-mA Output drive at 3.3 V
Typical VOLP (output ground bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 100 mA er JESD
78, class II
ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 1000-V Charged-device model (C101)
The SN74LVC2G02 device performs the Boolean
function Y = A + B or Y = A × B in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC2G02DCT
•
•
•
•
•
AV receiver
Audio dock: portable
Blu-ray player and home theater
Embedded PC
MP3 Player/recorder (portable audio)
Personal digital assistant (PDA)
Power: Telecom/server AC/DC supply: single
controller: analog and digital
Solid state drive (SSD): client and enterprise
TV: LCD/digital and high-definition (HDTV)
Tablet: enterprise
Video analytics: server
Wireless headset, keyboard, and mouse
BODY SIZE (NOM)
2.95 mm × 2.8 mm
SN74LVC2G02DCU VSSOP (8)
2.3 mm × 2.0 mm
SN74LVC2G02YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
PACKAGE
SSOP (8)
Simplified Schematic
1
7
1A
1B
2
1Y
5
3
2A
2B
6
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G02
SCES194N – APRIL 1999 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions ......................
Thermal Information .................................................
Electrical Characteristics ..........................................
Switching Characteristics .........................................
Switching Characteristics .........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (November 2013) to Revision N
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Added Device Information table. ........................................................................................................................................... 1
•
Added TJ(Max) spec to Abs Max Ratings table...................................................................................................................... 4
•
Moved Tstg spec to Abs Max Ratings table. ........................................................................................................................... 4
Changes from Revision L (April 1999) to Revision M
Page
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 5
2
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SCES194N – APRIL 1999 – REVISED MAY 2019
5 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
YZP Package
8-Pin DSBGA
Bottom View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A
1
Input
Channel 1 input A
1B
2
Input
Channel 1 input B
2Y
3
Output
GND
4
–
2A
5
Input
Channel 2 input A
2B
6
Input
Channel 2 input B
1Y
7
Output
VCC
8
–
Channel 2 output Y
Ground
Channel 1 output Y
Positive supply
Logic Diagram (Positive Logic)
1
7
1A
1B
2
1Y
5
3
2A
2B
6
2Y
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2500
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
Data retention only
5.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC2G02
THERMAL METRIC (1)
DCT (SSOP)
DCU (VSSOP) YZP (DSBGA)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
182.8
201.8
99.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
87.8
93.3
1.0
°C/W
RθJB
Junction-to-board thermal resistance
97.9
124.0
27.8
°C/W
ψJT
Junction-to-top characterization parameter
20.7
32.3
0.4
°C/W
ψJB
Junction-to-board characterization parameter
96.6
123.6
27.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V to 5.5 V
MIN
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
MAX
UNIT
V
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.75
0.55
0.75
0 to 5.5 V
±5
±5
μA
IOL = 16 mA
3.8
TYP (1)
IOH = –32 mA
3.8
3V
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
MAX
VCC – 0.1
IOL = 24 mA
II
–40°C to 125°C
TYP (1)
1.65 V
IOH = –24 mA
A or B
inputs
MIN
IOH = –4 mA
IOH = –16 mA
VOL
–40°C to 85°C
VCC
IO = 0
V
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
5
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
8.9
1
5.4
1
4.9
1
4.4
ns
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
10.9
1
6.4
1
5.9
1
5.4
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
18
18
19
22
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UNIT
pF
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5
2
4.5
1.8
4
3.5
3
2.5
2
1.5
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
1
0.5
0
VOL, Low-level output voltage (V)
VOH, High-level output voltage (V)
6.9 Typical Characteristics
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
-5
- 10 - 15 - 20 - 25 - 30 - 35 - 40 - 45 - 50
0
5
IOH, High-level output current (mA)
Figure 1. Simulated typical high-level output voltage (VOH)
across high-level output current (IOH) at common supply
values
10
15
20
25
30
35
40
IOL, Low-level output current (mA)
45
50
Figure 2. Simulated typical low-level output voltage (VOL)
across low-level output current (IOL) at common supply
values
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LVC2G02 device contains two 2-input positive-NOR gates and each gate performs the Boolean
function Y = A + B or Y = A • B. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
8.2 Functional Block Diagram
1
7
1A
1B
2
1Y
5
3
2A
2B
2Y
6
8.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
8.4 Device Functional Modes
Table 1. Function Table
(Each Gate)
INPUTS
A
B
OUTPUT
Y
H
X
L
X
H
L
L
L
H
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9 Application and Implementation
9.1 Application Information
The SN74LVC2G02 is a high-drive CMOS device that can be used for implement NOR logic with a high output
drive, such as an LED application. It can produce 24-mA of drive current at 3.3 V making it Ideal for driving
multiple outputs and good for high speed applications up to 100 Mhz. The inputs are 5.5-V tolerant allowing
translation down to VCC.
9.2 Typical Application
NOR Logic Function
Basic LED Driver
uC or Logic
uC or Logic
uC or Logic
uC or Logic
LVC2G02
uC or Logic
LVC2G02
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
9.2.3 Application Curves
10
8
Icc
Icc
Icc
Icc
1.8V
2.5V
3.3V
5V
Icc - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 4. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. A 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC2G02DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C02
(R, Z)
SN74LVC2G02DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C02
(R, Z)
SN74LVC2G02DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C02J, C02Q, C02R)
SN74LVC2G02DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C02J, C02Q, C02R)
SN74LVC2G02YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
CBN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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