SN74LVC2G06DBVR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 SN74LVC2G06 Dual Inverter Buffer and Driver With Open-Drain Outputs 1 Features 3 Description • This dual inverter buffer and driver is designed for 1.65-V to 5.5-V VCC operation. 1 • • • • • • • • • • • Available in the Texas Instruments Package Supports 5-V VCC Operation Max tpd of 3.4 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V Ioff Supports Live Insertion, Partial-Power-Down Mode and Back-Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Supports Down-Translation (5 V to 3.3 V and 3.3 V to 1.8 V) ESD Protection Exceeds JESD 22 – 2000-V Human Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) The output of the SN74LVC2G06 device is an opendrain which can be connected to other open-drain outputs to implement active-low, wired-OR, or activehigh wired-AND functions. The maximum sink current is 32 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. Device Information(1) ORDER NUMBER AV Receivers Blu-ray Players and Home Theaters DVD Recorders and Players Desktop or Notebook PCs Digital Radio or Internet Radio Players Digital Video Cameras (DVC) Embedded PC GPS: Personal Navigation Devices Mobile Internet Devices Network Projector Front-End Portable Media Players Pro Audio Mixers Smoke Detectors Solid-State Drive (SSD): Enterprise High-Definition (HDTV) BODY SIZE (NOM) SN74LVC2G06DBV SOT-23 (6) 2.90 mm × 1.60 mm SN74LVC2G06DCK SC70 (6) 2.00 mm × 1.25 mm SN74LVC2G06DRY SON (6) 1.45 mm × 1.00 mm SN74LVC2G06DSF SON (6) 1.00 mm × 1.00 mm SN74LVC2G06YZP DSBGA (6) 1.41 mm × 0.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram 2 Applications • • • • • • • • • • • • • • • PACKAGE 1A 2A 1 6 3 4 1Y 2Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 5 5 6 6 6 6 7 Absolute Maximum Ratings ..................................... ESD Ratings ............................................................ Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics for –40°C to 85°C ............ Switching Characteristics for –40°C to 125°C .......... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 9 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 9 9 9 9 Application and Implementation ........................ 10 9.1 Application Information............................................ 10 9.2 Typical Application ................................................. 10 10 Power Supply Recommendations ..................... 11 11 Layout................................................................... 11 11.1 Layout Guidelines ................................................. 11 11.2 Layout Example .................................................... 11 12 Device and Documentation Support ................. 12 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 12 12 12 12 13 Mechanical, Packaging, and Orderable Information ........................................................... 12 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (December 2013) to Revision J • Page Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Typical Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision H (August 2012) to Revision I Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Removed Ordering Information table. .................................................................................................................................... 1 • Added ESD warning .............................................................................................................................................................. 1 • Updated operating temperature range. .................................................................................................................................. 5 Changes from Revision G (January 2007) to Revision H • 2 Page Updated package views and ordering information. Added DRY & DSF packages................................................................ 1 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 SN74LVC2G06 www.ti.com SCES307J – AUGUST 2001 – REVISED JULY 2015 5 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View DCK Package 6-Pin SC70 Top View 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y DRY Package 6-Pin SON Top View YZP Package 6-Pin DSBGA Bottom View 2A 3 4 2Y GND 2 5 VCC 1 6 1A 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 1Y DSF Package 6-Pin SON Top View 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y Pin Functions PIN NAME NO I/O DESCRIPTION GND 2 — Ground 1A 1 I Input 1 2A 3 I Input 2 1Y 6 I Open-drain output 1 2Y 4 O Open-drain output 2 VCC 5 — Power pin Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 3 SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 6.5 V (2) VI Input voltage –0.5 6.5 V VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage applied to any output in the high or low state (2) (3) –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage Temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) +1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 SN74LVC2G06 www.ti.com SCES307J – AUGUST 2001 – REVISED JULY 2015 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN VCC Operating Supply voltage 5.5 1.5 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage MAX UNIT 1.65 Data retention only VCC = 1.65 V to 1.95 V VIH NOM 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V IOL Low-level output current VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V Δt/Δv Input transition rise or fall rate VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 ns/V VCC = 5 V ± 0.5 V TA (1) mA 24 5 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information SN74LVC2G06 THERMAL METRIC RθJA (1) (1) Junction-to-ambient thermal resistance DBV (SOT23) DCK (SC70) DRY (SON) YPZ (DSBGA) DSF (SON) 6 PINS 6 PINS 6 PINS 6 PINS 6 PINS 165 259 234 123 300 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 5 SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 μA VOL MIN TYP (1) MAX MAX 0.1 0.1 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.55 0.55 0.55 3V IOL = 32 mA 4.5 V VI = 5.5 V or GND Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND (1) –40°C to 125°C 1.65 V to 5.5 V IOL = 24 mA A inputs MIN TYP (1) IOL = 4 mA IOL = 16 mA II –40°C to 85°C VCC IO = 0 UNIT V 0 to 5.5 V ±5 ±5 μA 0 ±10 ±10 μA 1.65 V to 5.5 V 10 10 μA 3 V to 5.5 V 500 500 μA 3.3 V 3.5 3.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. 6.6 Switching Characteristics for –40°C to 85°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 1.8 7.2 1 3.9 1 3.4 1 2.9 UNIT ns 6.7 Switching Characteristics for –40°C to 125°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 1.8 8.2 1 4.4 1 3.9 1 3.4 UNIT ns 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 2 2 3 4 Submit Documentation Feedback UNIT pF Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 SN74LVC2G06 www.ti.com SCES307J – AUGUST 2001 – REVISED JULY 2015 6.9 Typical Characteristics 2.5 6 TPD TPD 5 2 TPD - ns TPD - ns 4 1.5 1 3 2 0.5 0 -100 1 0 -50 0 50 Temperature - °C 100 150 0 1 D001 Figure 1. TPD Across Temperature at 3.3-V VCC 2 3 Vcc - V 4 5 Product Folder Links: SN74LVC2G06 D002 Figure 2. TPD Across VCC at 25°C Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated 6 7 SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com 7 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) tPHZ/tPZH VLOAD VLOAD VLOAD LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms (Open Drain) 8 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 SN74LVC2G06 www.ti.com SCES307J – AUGUST 2001 – REVISED JULY 2015 8 Detailed Description 8.1 Overview The SN74LVC2G06 dual open-drain inverter device contains one open-drain inverter with a maximum sink current of 32 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram 1 A 3 Y 8.3 Feature Description The wide operating voltage range of 1.65 V to 5.5 V allows the SN74LVC2G06 to be used in systems with many different voltage rails. In addition, the voltage tolerance on the output allows the device to be used for inverting up-translation or down-translation. The IOFF feature safely allows voltage on the inputs and outputs when there's no VCC is present. 8.4 Device Functional Modes Table 1 lists the functional modes of the SN74LVC2G06. Table 1. Function Table INPUT A OUTPUT Y L Hi-Z H L Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 9 SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC2G06 is a dual high-drive CMOS device that implements a high-output drive buffer, such as an LED application. This device can sink 32 mA of current at 4.5 V making it ideal for high-drive applications and high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant and let it to translate up or down to VCC. The following Typical Application shows a simple LED driver application for a single channel of the device. 9.2 Typical Application VPU VCC From MCU Figure 4. Typical Application Diagram 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive currents that exceed maximum limits. The high drive also creates fast edges into light loads. Consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in Absolute Maximum Ratings table. – Do not pull outputs above 5.5 V. 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 SN74LVC2G06 www.ti.com SCES307J – AUGUST 2001 – REVISED JULY 2015 Typical Application (continued) 9.2.3 Application Curve 1600 Icc Icc Icc Icc 1400 1200 1.8V 2.5V 3.3V 5V Icc - µA 1000 800 600 400 200 0 0 20 40 Frequency - MHz 60 80 D001 Figure 5. ICC vs Frequency 10 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin must have a good bypass capacitor in order to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused. Examples include when only two inputs of a triple input and gate are used or when only three of the four buffer gates are used. Avoid leaving input pins unconnected because the undefined voltages at the outside connections result in undefined operational states. Observe the following rules under all circumstances. Connect all unused inputs of digital logic devices to a high or low bias to prevent them from floating. Based on the function of the device, apply the logic level to any unused input. Based on convenience, tie unused inputs to the GND or the VCC. 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure 6. Layout Recommendation Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 11 SN74LVC2G06 SCES307J – AUGUST 2001 – REVISED JULY 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks NanoFree, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G06 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC2G06DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C065, C06R) SN74LVC2G06DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C065, C06R) SN74LVC2G06DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CT5, CTJ, CTR) SN74LVC2G06DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CT5 SN74LVC2G06DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CT5 SN74LVC2G06DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CT SN74LVC2G06DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CT SN74LVC2G06YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CT7, CTN) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of