SN74LVC2G07DBVR

Product Folder Order Now Technical Documents Support & Community Tools & Software SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 SN74LVC2G07 Dual Buffer and Driver With Open-Drain Outputs 1 Features 3 Description • • • • This dual buffer and driver is designed for 1.65-V to 5.5-V VCC operation. The output of the SN74LVC2G07 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA. 1 • • • • • • • • • Dual Open-Drain Buffer Configuration -24-mA Output Drive at 3.3 V Support Translation-Up and Down Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs and Open-Drain Outputs Accept Voltages Up to 5.5 V Max tpd of 3.7 ns at 3.3 V Low Power Consumption, 10-μA Max ICC Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • • • • • • • • • • • • • • Blu-ray Players and Home Theaters DVD Recorders and Players Desktops or Notebook PCs Digital Video Cameras (DVC) Embedded PCs GPS: Personal Navigation Devices Mobile Phones Network Projector Front Ends Portable Media Players Solid State Drive (SSD): Enterprise High-Definition (HDTV) Tablet: Enterprise Audio Dock: Portable DLP Front Projection System NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Device Information(1) PART NUMBER SN74LVC2G07 PACKAGE BODY SIZE (NOM) SOT-23 (6) 2.90 mm × 1.60 mm SC70 (6) 2.00 mm × 1.25 mm DRY SON (6) 1.45 mm × 1.00 mm DSF SON (6) 1.00 mm × 1.00 mm DSBGA (6) 1.41 mm × 0.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram 1A 2A 1 6 3 4 1Y 2Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 5 5 5 5 5 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics from –40°C to 85°C ......... Switching Characteristics from –40°C to 125°C ....... Operating Characteristics.......................................... Typical Characteristics .............................................. 7 Parameter Measurement Information .................. 7 8 Detailed Description .............................................. 8 7.1 (Open-Drain) ............................................................. 7 8.1 8.2 8.3 8.4 9 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 8 8 8 8 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application ................................................... 9 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 10 11.1 Layout Guidelines ................................................. 10 11.2 Layout Examples................................................... 10 12 Device and Documentation Support ................. 11 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 11 13 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (November 2013) to Revision L • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision J (August 2012) to Revision K Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Updated operating temperature range. .................................................................................................................................. 4 2 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 SN74LVC2G07 www.ti.com SCES308L – AUGUST 2001 – REVISED MAY 2015 5 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View 1A GND 2A 1 2 3 YZP Package 6-Pin DSBGA Bottom View 6 1Y 5 VCC 4 2A 3 4 2Y GND 2 5 VCC 1 6 1A 1Y 2Y DRY Package 6-Pin SON Top View DCK Package 6-Pin SC70 Top View 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y DSF Package 6-Pin SON Top View 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y Pin Functions PIN NAME NO I/O DESCRIPTION 1A 1 I Input 1 GND 2 — Ground 2A 3 I Input 2 2Y 4 O Open-drain output 2 VCC 5 — Power pin 1Y 6 O Open-drain output 1 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 3 SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 6.5 V (2) VI Input voltage –0.5 6.5 V VO Voltage applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage applied to any output in the high or low state (2) (3) –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage Temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) +2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) +1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 0.65 × VCC VCC = 4.5 V to 5.5 V VIL UNIT 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current Δt/Δv Input transition rise or fall rate VCC = 3 V 4 mA 24 VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V (1) 8 16 ns/V 5 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 SN74LVC2G07 www.ti.com SCES308L – AUGUST 2001 – REVISED MAY 2015 Recommended Operating Conditions(1) (continued) TA MIN MAX UNIT –40 125 °C Operating free-air temperature 6.4 Thermal Information SN74LVC2G07 THERMAL METRIC (1) RθJA (1) Junction-to-ambient thermal resistance SOT-23 SC70 DRY (SON) DSBGA DSF (SON) 6 PINS 6 PINS 6 PINS 6 PINS 6 PINS 165 259 234 123 300 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 μA VOL TYP (1) –40°C to 125°C MAX MIN TYP (1) MAX 1.65 V to 5.5 V 0.1 0.1 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.55 0.55 0.55 IOL = 16 mA 3V IOL = 32 mA A inputs MIN IOL = 4 mA IOL = 24 mA II –40°C to 85°C VCC 4.5 V VI = 5.5 V or GND Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND CI VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25°C. IO = 0 UNIT V 0 to 5.5 V ±5 ±5 μA 0 ±10 ±10 μA 1.65 V to 5.5 V 10 10 μA 3 V to 5.5 V 500 500 μA 3.3 V 3.5 3.5 pF 6.6 Switching Characteristics from –40°C to 85°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.5 8.6 1 4.4 1 3.7 1 2.9 ns 6.7 Switching Characteristics from –40°C to 125°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) –40°C to 125°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.5 8.6 1 4.9 1 4.2 1 3.4 ns 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 3 3 4 4 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 UNIT pF 5 SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com 6.9 Typical Characteristics 2.5 TPD TPD - ns 2 1.5 1 0.5 0 -100 -50 0 50 Temperature - °C 100 150 D001 Figure 1. TPD Across Temperature at 3.3V Vcc 6 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 SN74LVC2G07 www.ti.com SCES308L – AUGUST 2001 – REVISED MAY 2015 7 Parameter Measurement Information 7.1 (Open-Drain) VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) tPHZ/tPZH VLOAD VLOAD VLOAD LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 7 SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC2G07 device contains two open drain buffer with a maximum sink current of 32 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram 1A 2A 1 6 3 4 1Y 2Y 8.3 Feature Description The open-drain configuration means that the device cannot provide its own output drive current; instead, it relies on pullup resistors to provide the "high" bus state. It can only drive the bus low. In the "Hi-Z" state, the SN74LVC2G07 acts as an open circuit and allows the external pullup to pull the bus high. Therefore, the pullup voltage determines the output level and therefore the SN74LVC2g07 can be used for up or down-translation. The device can sink 24 mA at 3 V while retaining an output voltage (VOL) of 0.55 V or lower. 8.4 Device Functional Modes Table 1 shows the device functional modes of the SN74LVC2G07 device. Table 1. Function Table INPUT A 8 OUTPUT Y L L H H Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 SN74LVC2G07 www.ti.com SCES308L – AUGUST 2001 – REVISED MAY 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LVC2G07 is a high-drive CMOS device that can be used to implement a high output drive buffer, such as an LED application. It can sink 32 mA of current at 4.5 V making it ideal for high-drive and wired-OR/AND functions. The inputs are 5.5 V tolerant allowing it to translate up and down to VCC. 9.2 Typical Application VCC 0.1 F 1A 1Y 2A 2Y From MCU GND Figure 3. Typical Application 9.2.1 Design Requirements 1. Recommended Input Conditions – Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating Conditions table at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table. – Outputs should not be pulled above 5.5 V. 9.2.2 Detailed Design Procedure This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 9 SN74LVC2G07 SCES308L – AUGUST 2001 – REVISED MAY 2015 www.ti.com Typical Application (continued) 9.2.3 Application Curve 6 TPD 5 TPD - ns 4 3 2 1 0 0 1 2 3 Vcc - V 4 5 6 D002 Figure 4. TPD Across VCC at 25°C 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. 11.2 Layout Examples VCC Input Unused Input Output Output Unused Input Input Figure 5. Layout Examples for SN74LVC2G07 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 SN74LVC2G07 www.ti.com SCES308L – AUGUST 2001 – REVISED MAY 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: Implications of Slow or Floating CMOS Inputs, SCBA004. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks NanoFree, E2E are trademarks of Texas Instruments. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G07 11 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2019 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LVC2G07DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (C075, C07F, C07K, C07R) SN74LVC2G07DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C07F, C07R) SN74LVC2G07DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV K, CVR) SN74LVC2G07DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 SN74LVC2G07DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 SN74LVC2G07DCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (CV5, CVF, CVJ, CV K, CVR) SN74LVC2G07DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CV5 SN74LVC2G07DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CV SN74LVC2G07DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CV SN74LVC2G07YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 (CV7, CVN) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of