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SN74LVC2G08
SCES198N – APRIL 1999 – REVISED DECEMBER 2015
SN74LVC2G08 Dual 2-Input Positive-AND Gate
1 Features
3 Description
•
This dual 2-input positive-AND gate is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.7 ns at 3.3 V
Low Power Consumption, 10-μA Maximum ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the VCC
Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
The SN74LVC2G08 device performs the Boolean
function Y = A x B or Y = A + B in positive logic.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC2G08DCT
2.30 mm × 2.00 mm
SN74LVC2G08YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1A
2 Applications
IP Phones: Wired and Wireless
Optical Networking: EPON and Video Over Fiber
Point-to-Point Microwave Backhaul
Power: Telecom DC/DC Module: Analog
Power: Telecom DC/DC Module: Digital
Private Branch Exchange (PBX)
Telecom Shelter: Power Distribution Unit (PDU)
Vector Signal Analyzers and Generators
Wireless Communications Testers
Wireless Repeaters
xDSL Modem/DSLAM
BODY SIZE (NOM)
2.95 mm × 2.80 mm
SN74LVC2G08DCU VSSOP (8)
1B
•
•
•
•
•
•
•
•
•
•
•
PACKAGE
SM8 (8)
2A
2B
1
2
7
1Y
5
6
3
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G08
SCES198N – APRIL 1999 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (April 2014) to Revision N
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings and Thermal Information tables, Feature Description
section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
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SCES198N – APRIL 1999 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
DCU Package
8-Pin VSSOP
Top View
1A
1B
2Y
GND
1
8
VCC
2
7
3
6
4
5
1Y
2B
2A
YZP Package
8-Pin DSBGA
Bottom View
GND
2Y
1B
1A
4 5
3 6
2 7
1 8
2A
2B
1Y
VCC
Pin Functions (1)
PIN
NAME
NO.
I/O
DESCRIPTION
1A
1
I
Channel 1 logic input
1B
2
I
Channel 1 logic input
1Y
7
O
Logic level output
2A
5
I
Channel 2 logic input
2B
6
I
Channel 2 logic input
2Y
3
O
Logic level output
GND
4
—
Ground
VCC
8
—
Power Supply
(1)
See Mechanical, Packaging, and Orderable Information for dimensions.
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SCES198N – APRIL 1999 – REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
Tj
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
Data retention only
5.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
SN74LVC2G08DCU
–40
125
SN74LVC2G08DCT
–40
125
SN74LVC2G08YZP
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC2G08
THERMAL METRIC
(1)
DCT (SM8)
DCU (VSSOP) YZP (DSBGA)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
220
227
128
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
108
84
14
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
VI = 5.5 V or GND
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND, IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND,
TA = –40°C to 85°C
Ci
VI = VCC or GND, TA = –40°C to 85°C
(1)
0.4
f = 10 MHz, TA = –40°C to 85°C
V
0.55
4.5 V
Ioff
Cpd
3.8
3V
IOL = 32 mA
A or B inputs
2.3
4.5 V
IOL = 16 mA
UNIT
V
IOH = –32 mA
IOL = 24 mA
II
MAX
2.4
3V
IOH = –24 mA
TYP (1)
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN
0.55
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
5
1.8 V to 3.3V
17
5V
20
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA
–40°C to 85°C
tpd
A or B
Y
–40°C to 125°C
6
VCC
MIN
VCC = 1.8 V ± 0.15 V
2.6
9
VCC = 2.5 V ± 0.2 V
1
5.1
VCC = 3.3 V ± 0.3 V
1
4.7
VCC = 5 V ± 0.5 V
1
3.8
VCC = 1.8 V ± 0.15 V
2.6
9.8
VCC = 2.5 V ± 0.2 V
1
5.8
VCC = 3.3 V ± 0.3 V
1
5.3
VCC = 5 V ± 0.5 V
1
4.8
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MAX
UNIT
ns
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6.7 Typical Characteristics
8
6
TPD
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. tPD Across Temperature at 3.3-V VCC
2
3
Vcc - V
4
5
Product Folder Links: SN74LVC2G08
D002
Figure 2. tPD Across VCC at 25°C
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6
7
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SCES198N – APRIL 1999 – REVISED DECEMBER 2015
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LVC1G06 device contains two positive-AND gates with a maximum sink current of 24 mA. A very low
tpd of 4.7ns at 3.3V makes the device ideal for high speed applications. Additionally, 5.5V tolerant inputs allow
the device to be used as a down translator if needed.
8.2 Functional Block Diagram
1A
1B
2A
2B
1
7
2
1Y
5
3
6
2Y
8.3 Feature Description
8.3.1 Down Voltage Translation
SN74LVC2G08 allows for logic input and output signals up to 5.5 V. While operating at VCC of 3.3 V, the device
will still recognize 5.5 V as a valid high input, however, the resulting output will be 3.3 V. This is the same for
other voltage levels in the device effectively down translating any input logic level higher than VCC but lower or
equal to 5.5 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2G08.
Table 1. Function Table
INPUTS
OUTPUT
A
B
Y
H
H
H
L
X
L
X
L
L
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www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G08 is a high-drive CMOS device that can be used for implementing AND logic with a high
output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it Ideal for
driving multiple outputs and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
Figure 4. Typical Application
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Tak care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI maximum) in the Recommended
Operating Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents must not exceed (IO maximum) per output and must not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Recommended Operating
Conditions table.
– Outputs must not be pulled above VCC in normal operating conditions.
10
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Typical Application (continued)
9.2.3 Application Curves
10
8
Icc
Icc
Icc
Icc
1.8V
2.5V
3.3V
5V
Icc - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 5. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC
pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass
capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor must be installed as close to the power pin as possible for best results
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on
the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2025
PACKAGING INFORMATION
Orderable part number
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
SN74LVC2G08DCTR
Active
Production
SSOP (DCT) | 8
3000 | LARGE T&R
Yes
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(2WJ5, C08)
(R, Z)
SN74LVC2G08DCTR.B
Active
Production
SSOP (DCT) | 8
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(2WJ5, C08)
(R, Z)
SN74LVC2G08DCTRE4
Active
Production
SSOP (DCT) | 8
3000 | null
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08
(R, Z)
SN74LVC2G08DCTRE4.B
Active
Production
SSOP (DCT) | 8
3000 | null
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08
(R, Z)
SN74LVC2G08DCTRG4
Active
Production
SSOP (DCT) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08
(R, Z)
SN74LVC2G08DCTRG4.B
Active
Production
SSOP (DCT) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08
(R, Z)
SN74LVC2G08DCUR
Active
Production
VSSOP (DCU) | 8
3000 | LARGE T&R
Yes
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(08, C08J, C08Q, C
08R)
(CR, CZ)
SN74LVC2G08DCUR.B
Active
Production
VSSOP (DCU) | 8
3000 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(08, C08J, C08Q, C
08R)
(CR, CZ)
SN74LVC2G08DCURE4
Active
Production
VSSOP (DCU) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08R
SN74LVC2G08DCURG4
Active
Production
VSSOP (DCU) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08R
SN74LVC2G08DCURG4.B
Active
Production
VSSOP (DCU) | 8
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08R
SN74LVC2G08DCUT
Active
Production
VSSOP (DCU) | 8
250 | SMALL T&R
Yes
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C08J, C08Q, C08R)
SN74LVC2G08DCUT.B
Active
Production
VSSOP (DCU) | 8
250 | SMALL T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
(C08J, C08Q, C08R)
SN74LVC2G08DCUTG4
Active
Production
VSSOP (DCU) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08R
SN74LVC2G08DCUTG4.B
Active
Production
VSSOP (DCU) | 8
250 | SMALL T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08R
SN74LVC2G08YZPR
Active
Production
DSBGA (YZP) | 8
3000 | LARGE T&R
Yes
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(CE7, CEN)
SN74LVC2G08YZPR.B
Active
Production
DSBGA (YZP) | 8
3000 | LARGE T&R
Yes
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(CE7, CEN)
CR
CR
(1)
Status: For more details on status, see our product life cycle.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2025
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G08 :
• Automotive : SN74LVC2G08-Q1
• Enhanced Product : SN74LVC2G08-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
SN74LVC2G08DCTR
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DCT
8
3000
180.0
12.4
3.15
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
4.35
1.55
4.0
12.0
Q3
SN74LVC2G08DCTRG4
SSOP
DCT
8
3000
177.8
12.4
3.45
4.4
1.45
4.0
12.0
Q3
SN74LVC2G08DCUR
VSSOP
DCU
8
3000
178.0
9.0
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G08DCURG4
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G08DCUT
VSSOP
DCU
8
250
178.0
9.0
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G08DCUTG4
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G08YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC2G08DCTR
SSOP
DCT
8
3000
190.0
190.0
30.0
SN74LVC2G08DCTRG4
SSOP
DCT
8
3000
183.0
183.0
20.0
SN74LVC2G08DCUR
VSSOP
DCU
8
3000
180.0
180.0
18.0
SN74LVC2G08DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC2G08DCUT
VSSOP
DCU
8
250
180.0
180.0
18.0
SN74LVC2G08DCUTG4
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74LVC2G08YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCT0008A
SSOP - 1.3 mm max height
SCALE 3.500
SMALL OUTLINE PACKAGE
C
4.25
TYP
3.95
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
2X
1.95
3.1
2.9
NOTE 3
4
5
8X
B
3.1
2.9
NOTE 4
SEE DETAIL A
0.30
0.15
0.13
1.3
1.0
C A B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.2
0.0
0.6
0.2
DETAIL A
TYPICAL
4220784/D 10/2025
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
(R0.05)
TYP
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220784/D 10/2025
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4220784/D 10/2025
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
SCALE 6.000
SMALL OUTLINE PACKAGE
3.2
TYP
3.0
A
C
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
NOTE 3
1.5
4
5
8X
B
2.4
2.2
NOTE 3
0.25
0.17
0.08
C A B
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0 -6
(0.13) TYP
0.1
0.0
0.35
0.20
DETAIL A
A 30
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8X (0.3)
8
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
8X (0.3)
1
(R0.05) TYP
8
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
D
C
SYMM
1.5
TYP
0.5
TYP
8X
0.015
D: Max = 1.918 mm, Min =1.858 mm
B
0.25
0.21
C A B
E: Max = 0.918 mm, Min =0.858 mm
A
1
2
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Last updated 10/2025
