SN74LVC2G126
SN74LVC2G126
SCES205N – APRIL 1999 – REVISED
SEPTEMBER 2020
SCES205N – APRIL 1999 – REVISED SEPTEMBER 2020
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SN74LVC2G126 Dual Bus Buffer Gate With 3-State Outputs
1 Features
3 Description
•
These bus transceivers are designed for 1.65-V to
3.6-V V CC operation. The SN74LVC2G126 device is a
dual line driver with 3-state output. The output is
disabled when the output-enable input is low.
•
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments NanoFree™
Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4ns at 3.3V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down to the VCC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
Device Information
PART NUMBER
•
•
BODY SIZE (NOM)
SN74LVC2G126DCT
SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G126DCU
VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G126YZP
DSBGA (8)
1.91 mm × 0.91 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
1OE
1A
1Y
2OE
2A
2 Applications
•
•
•
•
•
•
•
PACKAGE(1)
2Y
Simplified Schematic
Cable Modem Termination Systems
High-Speed Data Acquisition and Generation
Military: Radars and Sonars
Motor Controls: High-Voltage
Power Line Communication Modems
SSDs: Internal or External
Video Broadcasting and Infrastructure: Scalable
Platforms
Video Broadcasting: IP-Based Multi-Format
Transcoders
Video Communication Systems
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, –40°C to +85°C.................6
6.7 Switching Characteristics, –40°C to +125°C...............6
6.8 Operating Characteristics........................................... 7
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (September 2016) to Revision N (September 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Changes from Revision L (December 2014) to Revision M (September 2016)
Page
• Deleted Machine Model from Features ..............................................................................................................1
• Updated Device Information table...................................................................................................................... 1
• Updated pinout images and Pin Functions table................................................................................................ 3
• Added Operating junction temperature, TJ in Absolute Maximum Ratings ........................................................4
Changes from Revision K (November 2013) to Revision L (December 2014)
Page
• Added Applications, Device Information table, ESD Ratings table, Typical Characteristics, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section...................................................................................................1
• Updated Features .............................................................................................................................................. 1
Changes from Revision J (January 2007) to Revision K (November 2013)
Page
• Deleted Ordering Information table. ...................................................................................................................1
• Updated operating temperature range................................................................................................................5
2
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5 Pin Configuration and Functions
1OE
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
Not to scale
See mechanical drawings for dimensions.
Figure 5-1. DCT or DCU Package 8-Pin SM8 or VSSOP Top View
1
2
D
GND
2A
C
2Y
1Y
B
1A
2OE
A
1OE
V
CC
Not to scale
Figure 5-2. YZP Package 8-Pin DSBGA Bottom View
Pin Functions
PIN
NAME
SM8, VSSOP
DSBGA
TYPE
DESCRIPTION
1A
2
B1
I
1OE
1
A1
I
1A Input
1OE Enable/Input
1Y
6
C2
O
1Y Output
2A
5
D2
I
2A Input
2OE
7
B2
I
2OE Enable/Input
2Y
3
C1
O
2Y Output
GND
4
D1
—
Ground Pin
VCC
8
A2
—
Power Pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage
–0.5
6.5
V
voltage(2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2) (3)
UNIT
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
TJ
Operating junction temperature
150
°C
Tstg
Storage temperature
150
°C
Continuous current through VCC or GND
(1)
(2)
(3)
–65
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Section 6.3 table.
6.2 ESD Ratings
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
VALUE
UNIT
2000
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
IOH
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
8
16
Operating free-air temperature
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
(1)
mA
24
VCC = 4.5 V
TA
mA
4
VCC = 3 V
Input transition rise or fall rate
V
–32
VCC = 2.3 V
Δt/Δv
V
–24
VCC = 4.5 V
Low-level output current
V
0.3 × VCC
0
VCC = 1.65 V
IOL
V
V
2
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
ns/V
5
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs,SCBA004.
6.4 Thermal Information
SN74LVC2G126
THERMAL
METRIC(1)
DCT (SM8)
DCU (VSSOP) YZP (DSBGA)
UNIT
8 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
220
227
102
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.65 V to
5.5 V
IOH = –100 µA
VOH
MAX
MIN
–40°C to +125°C
MAX
MIN
VCC – 0.1
VCC – 0.1
VCC – 0.1
1.65 V
1.2
1.2
1.2
2.3 V
1.9
1.9
1.9
2.4
2.4
2.4
2.3
2.3
2.3
3.8
3.8
3.8
3V
MAX
4.5 V
IOL = 100 µA
1.65 V to
5.5 V
0.1
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.3
0.4
0.4
0.4
0.55
0.55
0.55
3V
IOL = 24 mA
UNIT
V
IOH = –32 mA
IOL = 16 mA
II
–40°C to +85°C
TYP(1)
IOH = –4 mA
IOH = –24 mA
A or OE
inputs
TA = 25°C
MIN
IOH = –8 mA
IOH = –16 mA
VOL
VCC
V
IOL = 32 mA
4.5 V
0.55
0.55
0.75
VI = 5.5 V or GND
0 to
5.5 V
±5
±5
±5
µA
Ioff
VI or VO = 5.5 V
0
±10
±10
±10
µA
IOZ
VO = 0 to 5.5 V
3.6 V
10
10
10
µA
1.65 V to
5.5 V
10
10
10
µA
500
500
500
µA
ICC
VI = 5.5 V or GND
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to
5.5 V
VI = VCC or GND
3.3 V
CI
Data
inputs
Control
inputs
Co
(1)
IO = 0
3.5
pF
4
VO = VCC or GND
3.3 V
6.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics, –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
–40°C to +85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.5
9.8
1.7
4.9
1.4
4
1
3.2
ns
ten
OE
Y
3.5
10
1.7
5
1.5
4.1
1
3.1
ns
tdis
OE
Y
1.7
12.6
1
5.7
1
4.4
1
3.3
ns
6.7 Switching Characteristics, –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (seeFigure 7-1 )
–40°C to +125°C
6
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.5
10.8
1.7
5.9
1.4
5
1
3.7
ns
ten
OE
Y
3.5
11
1.7
6
1.5
5.1
1
3.6
ns
tdis
OE
Y
1.7
13.6
1
6.7
1
5.4
1
3.8
ns
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6.8 Operating Characteristics
TA = 25°
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation
capacitance
Outputs enabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
19
19
20
22
2
2
2
3
f = 10 MHz
Outputs disabled
UNIT
pF
6.9 Typical Characteristics
5
2.5
2
4
1.5
3
TPD - ns
TPD - ns
TPD
1
0.5
2
1
TPD
0
-100
-50
0
50
Temperature - °C
100
150
0
0
1
D001
Figure 6-1. TPD Across Tempearture at 3.3 VCC
2
3
VCC - V
4
5
6
D002
Figure 6-2. TPD Across VCC at 25°C
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LVC2G126 device contains a dual buffer gate with output enable control and performs the Boolean
function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
8.2 Functional Block Diagram
1OE
1A
1Y
2OE
2A
2Y
8.3 Feature Description
•
•
•
•
1.65 V to 5.5 V operating voltage range
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8V
Inputs accept voltages to 5.5 V
– 5-V tolerance on input pin
Ioff feature
– Allows voltage on the inputs and outputs when VCC is 0 V
– Able to prevent leakage when VCC is 0 V
8.4 Device Functional Modes
Table 8-1 lists the functional modes of SN74LVC2G126.
Table 8-1. Function Table
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G126 device is a high-drive CMOS device that can be used as an output enabled buffer with a
high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
Buffer Function
Basic LED Driver
VCC
VCC
uC or Logic
uC or Logic
Wired OR
uC or Logic
uC or Logic
uC or Logic
Figure 9-1. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive also creates faster edges into light loads so routing and load conditions should be considered to
prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For rise time and fall time specifications, see Δt/ΔV in the Section 6.3 table.
• For specified high and low levels, see VIH and VIL in the Section 6.3 table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
• Load currents should not exceed 50 mA per output and 100 mA total for the part.
10
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9.2.3 Application Curve
10
VCC
VCC
VCC
VCC
9
8
1.8 V
2.5 V
3.3 V
5V
ICC (mA)
7
6
5
4
3
2
1
0
0
20
40
Frequency (MHz)
60
80
D003
Figure 9-2. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3
table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. Install the bypass capacitor as close to the power terminal as possible for the best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part
when asserted. This does not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagram
12
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: SN74LVC2G126
13
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74LVC2G126DCTRG4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C26
Z
74LVC2G126DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C26R
SN74LVC2G126DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C26
Z
SN74LVC2G126DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C26J, C26Q, C26R)
SN74LVC2G126DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C26J, C26Q, C26R)
SN74LVC2G126YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
(CN7, CNN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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