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SN54LVC373A, SN74LVC373A
SCAS295T – JANUARY 1993 – REVISED JULY 2014
SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation
on All Ports
(5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Live-Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Network Switches
TV Set-top Boxes
Motor Drives
PCs and Notebooks
3 Description
The SN54LVC373A octal transparent D-type latch is
designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC373A octal transparent D-type latch is
designed for 1.65-V to 3.6-V VCC operation.
Device Information(1)
PART NUMBER
SNx4LVC373A
PACKAGE
BODY SIZE (NOM)
SSOP (20)
7.20 mm × 5.30 mm
SOIC (20)
12.80 mm × 7.50 mm
PDIP (20)
24.33 mm 6.35 mm
TSSOP (20)
6.50 mm × 4.40 mm
VQFN (20)
4.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OE
LE
1
11
C1
1D
3
2
1Q
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC373A, SN74LVC373A
SCAS295T – JANUARY 1993 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
7
7
7
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, SN54LVC373A .....................
Timing Requirements, SN74LVC373A .....................
Switching Characteristics, SN54LVC373A ...............
Switching Characteristics, SN74LVC373A ...............
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision S (May 2005) to Revision T
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Changed Ioff Feature. .............................................................................................................................................................. 1
•
Added Military Disclaimer to Features.................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX ambient temperature from 85°C to 125°C. .................................................................................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. .............................................................................................................................................. 7
•
Added Detailed Description section........................................................................................................................................ 9
2
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SCAS295T – JANUARY 1993 – REVISED JULY 2014
6 Pin Configuration and Functions
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
2D
2Q
3Q
3D
4D
8Q
18
1Q
1D
2D
2Q
3Q
3D
4D
4Q
1D
1Q
OE
VCC
3
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54LVC373A . . . FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
19
VCC
20
2
LE
1
OE
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
SN74LVC373A . . . RGY PACKAGE
(TOP VIEW)
GND
SN54LVC373A . . . J OR W PACKAGE
SN74LVC373A . . . DB, DGV, DW, N,
NS, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
OE
I
Enable Pin
2
1Q
O
Output 1
3
1D
I
Input 1
4
2D
I
Input 2
5
2Q
O
Output 2
6
3Q
O
Output 3
7
3D
I
Input 3
8
4D
I
Input 4
9
4Q
O
Output 4
10
GND
–
Ground Pin
11
LE
I
Latch Enable
12
5Q
O
Output 5
13
5D
I
Input 5
14
6D
I
Input 6
15
6Q
O
Output 6
16
7Q
O
Output 7
17
7D
I
Input 7
18
8D
I
Input 8
19
8Q
O
Output 8
20
VCC
–
Power Pin
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
Table 1. Pin Assignments
1
2
3
4
A
1Q
OE
VCC
8Q
4
A
B
2D
7D
1D
8D
B
C
3Q
2Q
6Q
7Q
C
D
4D
5D
3D
6D
D
E
GND
4Q
LE
5Q
E
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCAS295T – JANUARY 1993 – REVISED JULY 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LVC373A
VCC
Operating
Supply voltage
Data retention only
SN74LVC373A
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
High-level input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.7
2
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
V
2
VCC = 1.65 V to 1.95 V
VIL
High-level output current
0.8
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
mA
4
VCC = 2.3 V
Low-level output current
V
0.8
VCC = 1.65 V
IOL
V
1.5
VCC = 1.65 V to 1.95 V
VIH
UNIT
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
–55
125
–40
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).
7.4 Thermal Information
SN74LVC373A
THERMAL METRIC
(1)
PW
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
102.5
RθJC(top)
Junction-to-case (top) thermal resistance
35.9
RθJB
Junction-to-board thermal resistance
53.5
ψJT
Junction-to-top characterization parameter
2.2
ψJB
Junction-to-board characterization parameter
52.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1993–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA
1.65 V
IOH = –8 mA
2.3 V
(1)
(2)
1.7
2.2
3V
2.4
2.4
3V
2.2
2.2
V
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
VI = 0 to 5.5 V
3.6 V
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
UNIT
1.2
2.2
Ioff
ΔICC
MAX
VCC – 0.2
1.65 V to 3.6 V
IOL = 100 µA
ICC
MIN TYP (1)
MAX
2.7 V
IOH = –24 mA
II
SN74LVC373A
VCC – 0.2
2.7 V to 3.6 V
IOH = –12 mA
VOL
MIN TYP
(1)
1.65 V to 3.6 V
IOH = –100 µA
VOH
SN54LVC373A
VCC
±5
±5
µA
±10
µA
±15
±10
µA
10
10
10
10
500
500
3.6 V
2.7 V to 3.6 V
V
µA
µA
Ci
VI = VCC or GND
3.3 V
4
12
4
pF
Co
VO = VCC or GND
3.3 V
5.5
12
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Timing Requirements, SN54LVC373A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC373A
PARAMETER
VCC = 2.7 V
MIN MAX
tw
Pulse duration, LE high
tsu
th
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
3.3
ns
Setup time, data before LE↓
2
2
ns
Hold time, data after LE↓
2
2
ns
7.7 Timing Requirements, SN74LVC373A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC373A
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
Pulse duration, LE high
9
4
3.3
3.3
ns
tsu
Setup time, data before LE↓
6
4
2
2
ns
th
Hold time, data after LE↓
4
2
1.5
1.5
ns
6
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7.8 Switching Characteristics, SN54LVC373A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC373A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
MIN
D
tpd
UNIT
MAX
MIN
MAX
8.5
1
7.5
9.5
1
8.5
Q
LE
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
ns
ten
OE
Q
8.7
1
7.7
ns
tdis
OE
Q
8
0.5
7
ns
7.9 Switching Characteristics, SN74LVC373A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC373A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
D
tpd
VCC = 1.8 V
± 0.15 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MIN
MAX
MIN
MAX
MAX
MIN
MAX
1
19.1
1
9.6
7.8
1.5
6.8
1
22.8
1
10.5
8.2
2
7.6
Q
LE
VCC = 2.5 V
± 0.2 V
UNIT
ns
ten
OE
Q
1
20
1
10.5
8.7
1.5
7.7
ns
tdis
OE
Q
1
19.3
1
7.8
7.6
1.5
7
ns
1
1
1
ns
tsk(o)
1
7.10 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance
per latch
Cpd
Outputs enabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
61
56
46
3
3
3
f = 10 MHz
Outputs disabled
UNIT
pF
7.11 Typical Characteristics
6
8
TPD in ns
7
5
4
5
TPD - ns
TPD - ns
6
4
3
3
2
2
1
1
TPD in ns
0
0
0.5
1
1.5
2
VCC - V
2.5
3
3.5
0
-100
-50
D003
Figure 1. SN74LVC373A LE to Q TDP
VCC vs TPD at 25°C
0
50
Temperature (qC)
100
150
D001
Figure 2. SN74LVC373A LE to Q
Across Temperature at 3.3-V VCC
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
9.2 Functional Block Diagram
OE
LE
1
11
C1
1D
3
2
1Q
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
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9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 2. Function Table (Each Latch)
INPUTS
10
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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SCAS295T – JANUARY 1993 – REVISED JULY 2014
10 Application and Implementation
10.1 Application Information
The SN74LVC373A is a high-drive CMOS device that can be used for a multitude of bus-interface type
applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V.
Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. The
inputs are 5.5 V tolerant allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.3 V
OE
VCC
CLK
1D
1Q
µC
System Logic
µC or
8D
8Q
LEDs
System Logic
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC373A SN74LVC373A
Submit Documentation Feedback
11
SN54LVC373A, SN74LVC373A
SCAS295T – JANUARY 1993 – REVISED JULY 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
3
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
Frequency - MHz
2.5
2
1.5
1
0.5
0
0
10
20
30
ICC - V
40
50
60
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
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Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC373A SN74LVC373A
SN54LVC373A, SN74LVC373A
www.ti.com
SCAS295T – JANUARY 1993 – REVISED JULY 2014
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC373A
Click here
Click here
Click here
Click here
Click here
SN74LVC373A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC373A SN74LVC373A
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
3-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9757301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757301Q2A
SNJ54LVC
373AFK
5962-9757301QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757301QR
A
SNJ54LVC373AJ
5962-9757301QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757301QS
A
SNJ54LVC373AW
SN74LVC373ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC373A
Samples
SN74LVC373ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC373A
Samples
SN74LVC373AN
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC373AN
Samples
SN74LVC373ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC373A
Samples
SN74LVC373APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373APWE4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC373A
Samples
SN74LVC373ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC373A
Samples
SNJ54LVC373AFK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757301Q2A
SNJ54LVC
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
3-Nov-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
373AFK
SNJ54LVC373AJ
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757301QR
A
SNJ54LVC373AJ
SNJ54LVC373AW
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757301QS
A
SNJ54LVC373AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of