SN74LVC3G04DCTR

SN74LVC3G04 www.ti.com SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 Triple Inverter Gate Check for Samples: SN74LVC3G04 FEATURES DESCRIPTION • This triple inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC3G04 device performs the Boolean function Y = A. 1 2 • • • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Live Insertion, Partial-PowerDown Mode, and Back-Drive Protection Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCC Level Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCU PACKAGE (TOP VIEW) 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 1A 3Y 2A GND 1 2 3 8 7 6 4 5 YZP PACKAGE (BOTTOM VIEW) VCC 1Y 3A 2Y GND 2A 3Y 1A 4 5 3 6 2 7 1 8 2Y 3A 1Y VCC See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated SN74LVC3G04 SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table (Each Inverter) INPUT A OUTPUT Y H L L H Logic Diagram (Positive Logic) 1A 2A 3A 1 7 3 5 6 2 1Y 2Y 3Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output when the output is in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output when the output is in the high or low state (2) (3) –0.5 VCC + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) 2 Package thermal impedance (4) DCT package 220 DCU package 227 YZP package 102 Storage temperature range –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC3G04 SN74LVC3G04 www.ti.com SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current Δt/Δv Input transition rise or fall rate –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V ± 0.5 V TA mA –24 VCC = 4.5 V IOL V ns/V 5 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC3G04 3 SN74LVC3G04 SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC – 0.1 IOH = –4 mA 1.65 V 1.2 1.2 IOH = –8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 3V TYP (1) MAX 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 IOL = 32 mA V 0.4 0.4 0.55 0.55 4.5 V 0.55 0.75 0 to 5.5 V ±5 ±5 µA 3V A VI = 5.5 V or GND inputs UNIT V IOH = –32 mA IOL = 24 mA VI or VO = 5.5 V 0 ±10 ±10 µA 10 10 µA 500 500 µA ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V Ci VI = VCC or GND (1) MIN VCC – 0.1 IOL = 16 mA Ioff –40°C to 125°C MAX 1.65 V to 5.5 V IOH = –24 mA II TYP (1) MIN IOH = –100 µA IOH = –16 mA VOL –40°C to 85°C VCC 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC3G04 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3.2 7.9 1.5 4.4 1.4 4.1 1.1 3.2 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC3G04 –40°C to 125°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3.2 8.9 1.5 5.4 1.4 5.1 1.1 3.8 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 16 16 16 18 Submit Documentation Feedback UNIT pF Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC3G04 SN74LVC3G04 www.ti.com SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC3G04 5 SN74LVC3G04 SCES363L – AUGUST 2001 – REVISED NOVEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision K (May 2007) to Revision L Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Removed ordering information. ............................................................................................................................................ 1 • Updated Features. ................................................................................................................................................................ 1 • Added ESD warning. ............................................................................................................................................................ 2 • Updated operating temperature range. ................................................................................................................................. 3 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC3G04 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVC3G04DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04 Z SN74LVC3G04DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04 Z SN74LVC3G04DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C04J, C04Q, C04R) SN74LVC3G04DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04R SN74LVC3G04DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C04J, C04Q, C04R) SN74LVC3G04YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 CCN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of