SN74LVC3G14
www.ti.com
SCES367J – AUGUST 2001 – REVISED NOVEMBER 2013
Triple Schmitt-Trigger Inverter
Check for Samples: SN74LVC3G14
FEATURES
DESCRIPTION
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This triple Schmitt-trigger inverter is designed for
1.65-V to 5.5-V VCC operation.
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Available in the Texas Instruments NanoFree™
Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) 2 V at
VCC = 3.3 V, TA = 25°C
Ioff Feature Supports Live Insertion, PartialPower-Down Mode and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
The SN74LVC3G14 contains three inverters and
performs the Boolean function Y = A. The device
functions as three independent inverters but, because
of Schmitt action, it may have different input threshold
levels for positive-going (VT+) and negative-going
(VT–) signals.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DCU PACKAGE
(TOP VIEW)
VCC
1A
1
8
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
1A
3Y
2A
GND
YZP PACKAGE
(BOTTOM VIEW)
1
8
VCC
2
7
3
6
4
5
1Y
3A
2Y
GND
2A
3Y
1A
4 5
3 6
2 7
1 8
2Y
3A
1Y
VCC
See mechanical drawings for dimensions.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
SN74LVC3G14
SCES367J – AUGUST 2001 – REVISED NOVEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
Logic Diagram (Positive Logic)
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
IIK
Input clamp current
VI
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