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SN74LVC3G34
SCES366L – AUGUST 2001 – REVISED OCTOBER 2015
SN74LVC3G34 Triple Buffer Gate
1 Features
3 Description
•
The SN74LVC3G34 device is a triple buffer gate
designed for 1.65-V to 5.5-V VCC operation. The
SN74LVC3G34 device performs the Boolean function
Y = A in positive logic.
1
•
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the VCC
Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
•
•
•
•
•
AV Receivers
Audio Docks: Portable
Blu-ray Players and Home Theaters
DVD Recorders and Players
Embedded PCs
MP3 Players and Recorders (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid-State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablets: Enterprise
Video Analytics: Servers
Wireless Headsets, Keyboards, and Mice
BODY SIZE (NOM)
2.95 mm × 2.80 mm
SN74LVC3G34DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC3G34YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1A
2 Applications
•
•
•
•
•
•
•
•
PACKAGE
SN74LVC3G34DCT SM8 (8)
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC3G34
SCES366L – AUGUST 2001 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
4
5
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics .........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (Feburary 2007) to Revision K
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Features section ...................................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 4
Changes from Revision K (November 2013) to Revision L
Page
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal
Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Deleted part number from Switching Characteristics table headers. ..................................................................................... 5
2
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SCES366L – AUGUST 2001 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
1A
DCU Package
8-Pin VSSOP
Top View
VCC
8
1
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
1A
3Y
2A
GND
1
8
VCC
2
7
1Y
3A
2Y
3
6
4
5
YZP Package
8-Pin DSBGA
Bottom View
GND
2A
3Y
1A
4 5
3 6
2 7
1 8
2Y
3A
1Y
VCC
Pin Functions (1)
PIN
NAME
NO.
I/O
DESCRIPTION
1A
1
I
Buffer Input 1
1Y
7
O
Buffer Output 1
2A
3
I
Buffer Input 2
2Y
5
O
Buffer Output 2
3A
6
I
Buffer Input 3
3Y
2
O
Buffer Output 3
GND
4
—
Ground pin
VCC
8
—
Power pin
(1)
See mechanical drawings for dimensions
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
(2)
VO
Voltage applied to any output in the high-impedance or power-off state
VO
Voltage applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
-65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2500
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
Data retention only
5.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
Low-level output current
Δt/Δv
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
DCT, DCU Package
–40
125
YZP Package
-40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC3G34
THERMAL METRIC
RθJA
(1)
4
(1)
Junction-to-ambient thermal resistance
DCT (SM8)
DCU (VSSOP)
YZP (DSBGA)
8 PINS
8 PINS
8 PINS
220
227
140
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
A inputs
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3V
0.4
TA = –40°C to
85°C
0.55
0.55
4.5 V
TA = –40°C to
125°C
0.75
VI = 5.5 V or GND
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
CI
VI = VCC or GND
IO = 0
V
0.75
TA = –40°C to
85°C
VI or VO = 5.5 V
3.8
3V
TA = –40°C to
125°C
Ioff
(1)
2.3
4.5 V
IOL = 24 mA
UNIT
V
IOH = –32 mA
IOL = 32 mA
II
MAX
2.4
3V
IOH = –24 mA
TYP (1)
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
TA = –40°C to
85°C
3.3 V
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
tpd
A
Y
Y
OPERATING FREE-AIR
TEMPERATURE (TA)
–40°C to 85°C
–40°C to 125°C
VCC
MIN
MAX
VCC = 1.8 V ± 0.15 V
3.2
7.9
VCC = 2.5 V ± 0.2 V
1.5
4.4
VCC = 3.3 V ± 0.3 V
1.4
4.1
VCC = 5 V ± 0.5 V
1.1
3.2
VCC = 1.8 V ± 0.15 V
3.2
8.9
VCC = 2.5 V ± 0.2 V
1.5
5.4
VCC = 3.3 V ± 0.3 V
1.4
5.1
VCC = 5 V ± 0.5 V
1.1
3.8
UNIT
ns
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
VCC = 1.8 V
19
VCC = 2.5 V
19
VCC = 3.3 V
19
VCC = 5 V
21
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UNIT
pF
5
SN74LVC3G34
SCES366L – AUGUST 2001 – REVISED OCTOBER 2015
www.ti.com
6.8 Typical Characteristics
2.5
TPD
TPD - ns
2
1.5
1
0.5
0
-100
-50
0
50
Temperature - °C
100
150
D001
Figure 1. TPD Across Temperature at 3.3-V VCC
6
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC3G34 device contains three buffer gates that each perform the Boolean function Y = A. This
device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
8.3 Feature Description
The SN74LVC3G34 device has a wider operating voltage range, operating from 1.65 V to 5.5 V, and allows
down voltage translation. The SN74LVC3G34 Ioff feature allows voltages on the inputs and outputs when VCC is
0 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC3G34.
Table 1. Function Table
8
INPUT
A
OUTPUT
Y
H
H
L
L
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9 Application and Implementation
9.1 Application Information
The SN74LVC3G34 is a high-drive CMOS device that can be used as a buffer with a high output drive, such as
an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal for driving multiple outputs
and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant, allowing it to translate down
to VCC.
9.2 Typical Application
Buffer Function
Basic LED Driver
VCC
VCC
Microcontroller or
Logic
SN74LVC3G34
Microcontroller or
Logic
Microcontroller or
Logic
SN74LVC3G34
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in the Recommended Operating Conditions
table.
– Outputs must not be pulled above VCC under normal operating conditions.
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Typical Application (continued)
9.2.3 Application Curve
5
TPD
TPD - ns
4
3
2
1
0
0
1
2
3
Vcc - V
4
5
6
D002
Figure 3. TPD Across VCC at 25°C
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is
recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise.
0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to
the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on
the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
10
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Documentation Support
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC3G34DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C34
(R, Z)
Samples
SN74LVC3G34DCTRG4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C34
(R, Z)
Samples
SN74LVC3G34DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(34, C34J, C34Q, C
34R)
(CR, CZ)
SN74LVC3G34DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C34R
Samples
SN74LVC3G34DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C34J, C34Q, C34R)
Samples
SN74LVC3G34DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C34R
Samples
SN74LVC3G34YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C9N
Samples
Samples
CR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of