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SN54LVC573A, SN74LVC573A
SCAS300S – JANUARY 1993 – REVISED MAY 2014
SNx4LVC573A Octal Transparent D-Type Latches With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.9 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC)
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Servers
PC, Notebook
Network Switch
Health & Fitness/Wearables
Telecom Infrastructure
Electronic Point of Sales
3 Description
The SN54LVC573A octal transparent D-type latch is
designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC573A octal transparent D-type latch is
designed for 1.65-V to 3.6-V VCC operation. These
devices feature 3-state outputs designed specifically
for driving highly capacitive or relatively lowimpedance loads. They are particularly suitable for
implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
Device Information(1)
PART NUMBER
SN74LVC573A
PACKAGE
BODY SIZE (NOM)
PDIP (20)
25.40 x 6.35 mm
VQGN (20)
4.50 x 3.50 mm
SOIC (20)
12.80 x 7.50 mm
SSOP (20)
7.20 x 5.30 mm
TVSOP (20)
5.00 x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
OE
LE
1
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
SN54LVC573A, SN74LVC573A
SCAS300S – JANUARY 1993 – REVISED MAY 2014
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
7
7
7
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements, SN54LVC573A .....................
Timing Requirements, SN74LVC573A .....................
Switching Characteristics, SN54LVC573A ..............
Switching Characteristics, SN74LVC573A ...............
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Applications and Implementation...................... 10
10.1 Application Information.......................................... 10
10.2 Typical Application ................................................ 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision R (September 2005) to Revision S
Page
•
Removed Ordering Information table. ................................................................................................................................... 1
•
Updated device temperature ratings. .................................................................................................................................... 4
•
Added Handling Ratings. ....................................................................................................................................................... 4
•
Added Typical Characteristics. .............................................................................................................................................. 7
•
Added Detailed Description section. ...................................................................................................................................... 9
•
Added Applications and Implemetation section. .................................................................................................................. 10
•
Added Power Supply Recommendations section................................................................................................................. 11
•
Added Layout section. ......................................................................................................................................................... 11
2
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SCAS300S – JANUARY 1993 – REVISED MAY 2014
6 Pin Configuration and Functions
19
18
4
5
17
16
6
7
15
14
8
9
13
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1D
2D
3D
4D
5D
6D
7D
8D
2
19 1Q
3
18 2Q
4
17 3Q
5
16 4Q
6
15 5Q
7
14 6Q
8
13 7Q
12 8Q
9
10
3D
4D
5D
6D
7D
1Q
20
2D
1D
OE
VCC
1
SN54LVC573A . . . FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
6
17
16
7
8
15
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
20
2
3
VCC
1
11
LE
GND
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
SN74LVC573A . . . RGY PACKAGE
(TOP VIEW)
OE
SN54LVC573A . . . J OR W PACKAGE
SN74LVC573A . . . DB, DGV, DW, N,
NS, OR PW PACKAGE
(TOP VIEW)
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
Pin Functions
PIN
SN54LVC573A
SN74LVC573A
J, W, AND FK
DB, DGV, DW, N,
NS, PW, AND RGY
GQN AND ZQN
OE
1
1
A2
Enable Pin
1D
2
2
A1
Input 1
2D
3
3
B3
Input 2
3D
4
4
B1
Input 3
4D
5
5
C2
Input 4
5D
6
6
C1
Input 5
6D
7
7
D3
Input 6
7D
8
8
D1
Input 7
8D
9
9
E2
Input 8
GND
10
10
E1
Ground Pin
LE
11
11
E3
Latch Enable
8Q
12
12
E4
Output 8
7Q
13
13
D2
Output 7
6Q
14
14
D4
Output 6
5Q
15
15
C3
Output 5
4Q
16
16
C4
Output 4
3Q
17
17
B2
Output 3
2Q
18
18
B4
Output 2
1Q
19
19
A4
Output 1
VCC
20
20
A3
Power Pin
NAME
DESCRIPTION
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SCAS300S – JANUARY 1993 – REVISED MAY 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
(2)
MIN
MAX
–0.5
6.5
UNIT
V
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
DB package (4)
70
DGV package (4)
92
DW package (4)
θJA
Package thermal impedance
GQN or ZQN package
58
(4)
78
N package (4)
69
NS package (4)
60
PW package
(4)
83
RGY package (5)
(1)
(2)
(3)
(4)
(5)
°C/W
37
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
7.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
4
Electrostatic discharge
MAX
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
UNIT
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V
may actually have higher performance.
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SCAS300S – JANUARY 1993 – REVISED MAY 2014
7.3 Recommended Operating Conditions (1)
SN54LVC573A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
Low-level input voltage
1.7
2
Input voltage
VO
V
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Output voltage
0.8
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
VCC = 1.65 V
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
4
VCC = 2.3 V
IOL
V
–4
VCC = 2.3 V
High-level output current
V
0.8
VCC = 1.65 V
IOH
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.7 V to 3.6 V
SN74LVC573A
MIN
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
6
–55
125
–40
mA
6
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC573A
THERMAL METRIC (1)
PW
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
102.5
RθJCtop
Junction-to-case (top) thermal resistance
35.9
RθJB
Junction-to-board thermal resistance
53.5
ψJT
Junction-to-top characterization parameter
2.2
ψJB
Junction-to-board characterization parameter
52.9
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 1993–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
IOH = –4 mA
1.65 V
IOH = –8 mA
2.3 V
IOH = –12 mA
IOH = –24 mA
II
(1)
(2)
MAX
VCC – 0.2
1.2
1.7
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
V
0.2
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
3.6 V
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
UNIT
VCC – 0.2
2.7 V to 3.6 V
VI = 0 to 5.5 V
ΔICC
MIN TYP (1)
MAX
2.7 V
Ioff
ICC
SN74LVC573A
1.65 V to 3.6 V
IOL = 100 µA
VOL
MIN TYP
(1)
1.65 V to 3.6 V
IOH = –100 µA
VOH
SN54LVC573A
VCC
±5
3.6 V
2.7 V to 3.6 V
V
±5
µA
±10
µA
±15
±10
µA
10
10
10
10
500
500
µA
µA
Ci
VI = VCC or GND
3.3 V
4
4
pF
Co
VO = VCC or GND
3.3 V
5.5
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Timing Requirements, SN54LVC573A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC573A
VCC = 2.7 V
MIN
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
MAX
3.3
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
ns
2
2
ns
2.5
2.5
ns
7.7 Timing Requirements, SN74LVC573A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC573A
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
Pulse duration, LE high
9
4
3.3
3.3
ns
tsu
Setup time, data before LE↓
6
4
2
2
ns
th
Hold time, data after LE↓
4
2
1.5
1.5
ns
6
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7.8 Switching Characteristics, SN54LVC573A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC573A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
MIN
D
tpd
Q
LE
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MAX
MIN
MAX
7.7
1
6.9
8.4
1
7.7
ns
ten
OE
Q
8.5
1
7.5
ns
tdis
OE
Q
7
0.5
6.7
ns
7.9 Switching Characteristics, SN74LVC573A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC573A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
D
tpd
VCC = 1.8 V
± 0.15 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
19.1
1
9.6
1
7.7
1.5
6.9
1
22.8
1
10.5
1
8.4
2
7.7
Q
LE
VCC = 2.5 V
± 0.2 V
ns
ten
OE
Q
1
20
1
10.5
1
8.5
1.5
7.5
ns
tdis
OE
Q
1
19.3
1
7.8
1
7
1.6
6.5
ns
1
ns
tsk(o)
7.10 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation
capacitance
per latch
Cpd
Outputs
enabled
Outputs
disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
61
56
37
3
3
4
UNIT
f = 10 MHz
pF
7.11 Typical Characteristics
6
8
TDP
TPD in ns
7
5
6
4
TPD
TDP
5
4
3
3
2
2
1
1
0
0
0.5
1
1.5
2
Vcc - Volts
2.5
3
3.5
0
-100
-50
Figure 1. SN74LVC573A LE to Q TDP Vcc vs TPD at 25°C
0
50
100
Temp - °C
D001
150
D001
Figure 2. SN74LVC573A LE to Q Across Temp 3.3V Vcc
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. These devices
feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They
are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and
working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered output-enable (OE) input can
be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without interface or pullup
components. OE does not affect the internal operations of the latches. Old data can be retained or new data can
be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through
the device when it is powered down.
9.2 Functional Block Diagram
OE
LE
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff Feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Function Table
(Each Latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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10 Applications and Implementation
10.1 Application Information
The SN74LVC573A is a high drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched . It can produce 24 mA of drive current at 3.3 V
making it Ideal for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are
5.5 V tolerant allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.6 V
OE
Vcc
LE
1D
uC or
System Logic
8D
1Q
uC
System Logic
LEDs
8Q
GND
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specifications. See (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5V at any valid VCC.
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC573A SN74LVC573A
SN54LVC573A, SN74LVC573A
www.ti.com
SCAS300S – JANUARY 1993 – REVISED MAY 2014
Typical Application (continued)
10.2.3 Application Curves
3
ICC 1.8V
ICC 2.5V
ICC 3.3V
2.5
ICC - mA
2
1.5
1
0.5
0
0
20
40
Frequency - MHz
60
D001
Figure 4. SN74LVC573A ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. A 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IOs so they also cannot float when disabled.
12.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC573A SN74LVC573A
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11
SN54LVC573A, SN74LVC573A
SCAS300S – JANUARY 1993 – REVISED MAY 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC573A
Click here
Click here
Click here
Click here
Click here
SN74LVC573A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC573A SN74LVC573A
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9757501Q2A
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757501Q2A
SNJ54LVC
573AFK
5962-9757501QRA
ACTIVE
CDIP
J
20
20
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757501QR
A
SNJ54LVC573AJ
5962-9757501QSA
ACTIVE
CFP
W
20
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757501QS
A
SNJ54LVC573AW
SN74LVC573ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC573A
Samples
SN74LVC573ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC573A
Samples
SN74LVC573ADWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC573A
Samples
SN74LVC573AN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC573AN
Samples
SN74LVC573ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC573A
Samples
SN74LVC573ANSRE4
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC573A
Samples
SN74LVC573APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573APWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573APWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
SN74LVC573APWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC573A
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Dec-2023
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC573ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC573A
SNJ54LVC573AFK
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629757501Q2A
SNJ54LVC
573AFK
SNJ54LVC573AJ
ACTIVE
CDIP
J
20
20
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757501QR
A
SNJ54LVC573AJ
SNJ54LVC573AW
ACTIVE
CFP
W
20
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9757501QS
A
SNJ54LVC573AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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