SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
FEATURES
•
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 7.4 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
xxxx
SN54LVC646A . . . JT OR W PACKAGE
SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
DIR
SAB
CLKAB
NC
VCC
CLKBA
SBA
1
4
A1
A2
A3
NC
A4
A5
A6
5
3
2 1 28 27 26
25
6
7
24
23
8
22
21
9
20
10
19
11
12 13 14 15 16 17 18
OE
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
ORDERING INFORMATION
PACKAGE (1)
TA
Reel of 2000
SN74LVC646ADWR
SOP – NS
Reel of 2000
SN74LVC646ANSR
LVC646A
SSOP – DB
Reel of 2000
SN74LVC646ADBR
LC646A
Tube of 60
SN74LVC646APW
Reel of 2000
SN74LVC646APWR
Reel of 250
SN74LVC646APWT
CDIP – JT
Tube of 15
SNJ54LVC646AJT
SNJ54LVC646AJT
CFP – W
Tube of 85
SNJ54LVC646AW
SNJ54LVC646AW
LCCC – FK
Tube of 42
SNJ54LVC646AFK
SNJ54LVC646AFK
TSSOP – PW
–55°C to 125°C
(1)
TOP-SIDE MARKING
SN74LVC646ADW
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
Tube of 25
LVC646A
LC646A
Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
(1)
2
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
OPERATION OR
FUNCTION
X
X
↑
X
X
X
Input
Unspecified (1)
Store A, B unspecified (1)
X
X
X
↑
X
X
Unspecified (1)
Input
Store B, A unspecified (1)
H
X
↑
↑
X
X
Input
Input
Store and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
21
OE
L
3
DIR
L
1
23
CLKAB CLKBA
X
X
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
22
SBA
L
21
OE
L
3
DIR
H
3
DIR
X
X
X
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
X
X
X
STORAGE FROM
A, B, OR A AND B
2
SAB
L
22
SBA
X
BUS B
BUS A
BUS A
21
OE
X
X
H
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
1
CLKAB
X
22
SBA
X
X
X
21
OE
L
L
3
DIR
1
CLKAB
23
CLKBA
2
SAB
22
SBA
L
H
X
H or L
H or L
X
X
H
H
X
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
DIR
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages.
4
B1
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
(1)
(2)
(3)
(4)
DB package
63
DW package
46
NS package
65
PW package
88
Storage temperature range
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
SN54LVC646A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
SN74LVC646A
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
VCC = 2.3 V to 2.7 V
1.7
2
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
0.8
High-level output current
0
5.5
5.5
High or low state
0
VCC
VCC
3-state
0
5.5
5.5
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
VCC = 1.65 V
IOL
V
0.8
VCC = 1.65 V
IOH
V
2
VCC = 1.65 V to 1.95 V
VIL
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.7 V to 3.6 V
UNIT
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
–55
125
–40
mA
10
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
UNIT
VCC – 0.2
1.2
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
V
1.65 V to 3.6 V
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
±5
±5
µA
VI = 0 to 5.5 V
3.6 V
VI or VO = 5.5 V
0
IOZ (2)
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (3)
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
TYP (1) MAX
VCC – 0.2
2.3 V
Ioff
ICC
MIN
IOH = –8 mA
IOL = 100 µA
Control
inputs
SN74LVC646A
TYP (1) MAX
1.65 V
IOH = –24 mA
II
MIN
IOH = –4 mA
IOH = –12 mA
VOL
SN54LVC646A
1.65 V to 3.6 V
IOH = –100 µA
VOH
VCC
3.6 V
2.7 V to 3.6 V
V
±10
µA
±15
±10
µA
10
10
10
10
500
500
µA
µA
Ci
Control
inputs
VI = VCC or GND
3.3 V
4.5
4.5
pF
Cio
A or B
port
VO = VCC or GND
3.3 V
7.5
7.5
pF
VCC = 3.3 V
± 0.3 V
UNIT
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVC646A
VCC = 2.7 V
MIN
MAX
MIN
Clock frequency
tw
Pulse duration
3.3
3.3
ns
tsu
Setup time, data before CLK↑
1.6
1.5
ns
th
Hold time, data after CLK↑
1.7
1.7
ns
6
150
MAX
fclock
150
MHz
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN74LVC646A
VCC = 1.8 V
± 0.18 V
VCC = 2.5 V
± 0.2 V
MIN
MIN
MAX
MAX
(1)
VCC = 2.7 V
MIN
MAX
(1)
VCC = 3.3 V
± 0.3 V
MIN
MAX
fclock
Clock frequency
tw
Pulse duration
(1)
(1)
3.3
3.3
ns
tsu
Setup time, data before CLK↑
(1)
(1)
1.6
1.5
ns
th
Hold time, data after CLK↑
(1)
(1)
1.7
1.7
ns
(1)
150
UNIT
150
MHz
This information was not available at the time of publication.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVC646A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 2.7 V
MIN
fmax
MAX
150
A or B
tpd
B or A
CLK
A or B
SBA or SAB
ten
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
7.9
1
7.4
8.8
1
8.4
9.9
1
8.6
10.2
1
8.2
ns
ns
OE
A
tdis
OE
A
8.9
1
7.5
ns
ten
DIR
B
10.4
1
8.3
ns
tdis
DIR
B
8.7
1
7.9
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN74LVC646A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
A or B
tpd
CLK
SBA or SAB
(1)
MAX
(1)
fmax
B or A
A or B
VCC = 2.5 V
± 0.2 V
MIN
MAX
(1)
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
(1)
(1)
(1)
(1)
7.9
1
7.4
(1)
(1)
(1)
(1)
8.8
1
8.4
(1)
(1)
(1)
(1)
ns
9.9
1
8.6
ten
OE
A
(1)
(1)
(1)
(1)
10.2
1
8.2
ns
tdis
OE
A
(1)
(1)
(1)
(1)
8.9
1
7.5
ns
(1)
(1)
(1)
10.4
1
8.3
ns
(1)
(1)
(1)
8.7
1
7.9
ns
ten
DIR
B
(1)
tdis
DIR
B
(1)
This information was not available at the time of publication.
7
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
(1)
8
Power dissipation capacitance
per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
(1)
75
(1)
(1)
9
UNIT
pF
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J – JANUARY 1993 – REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC646ADBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC646A
Samples
SN74LVC646ADW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC646A
Samples
SN74LVC646APW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC646A
Samples
SN74LVC646APWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LC646A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of