SN74LVC7001A
SCLS994A – FEBRUARY 2024 – REVISED MARCH 2024
SN74LVC7001A Quad 2-Input AND Gates with Schmitt-Trigger Inputs
1 Features
3 Description
•
•
•
•
The SN74LVC7001A contains four independent 2input AND gates with Schmitt-trigger inputs. Each
gate performs the Boolean function Y = A ● B in
positive logic.
•
Operating range from 1.1V to 3.6V
5.5V tolerant input pins
Supports standard pinouts
Latch-up performance exceeds 250mA
per JESD 17
ESD protection exceeds JESD 22
– 2000V Human-Body Model (A114-A)
– 1000V Charged-Device Model (C101)
2 Applications
•
•
Combining power good signals
Enable digital signals
Package Information
PART NUMBER
SN74LVC7001A
(1)
(2)
(3)
PACKAGE(1)
PACKAGE SIZE(2)
BODY SIZE (NOM)(3)
BQA (WQFN, 14)
3mm × 2.5mm
3mm × 2.5mm
PW (TSSOP, 14)
5mm × 6.4mm
5mm × 4.4mm
For more information, see Section 11.
The package size (length × width) is a nominal value and
includes pins, where applicable.
The body size (length × width) is a nominal value and does
not include pins.
Logic Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Electrical Characteristics.............................................5
5.6 Switching Characteristics............................................6
5.7 Noise Characteristics.................................................. 6
5.8 Typical Characteristics................................................ 7
6 Parameter Measurement Information............................ 9
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
2
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
8.3 Power Supply Recommendations.............................14
8.4 Layout....................................................................... 14
9 Device and Documentation Support............................15
9.1 Documentation Support............................................ 15
9.2 Receiving Notification of Documentation Updates....15
9.3 Support Resources................................................... 15
9.4 Trademarks............................................................... 15
9.5 Electrostatic Discharge Caution................................15
9.6 Glossary....................................................................15
10 Revision History.......................................................... 15
11 Mechanical, Packaging, and Orderable
Information.................................................................... 15
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2
1Y
3
2A
4
VCC
14
1B
1
1A
4 Pin Configuration and Functions
Thermal
Pad
1A
1
14
VCC
1B
2
13
4B
13
4B
1Y
3
12
4A
12
4A
2A
4
11
4Y
11
4Y
2B
5
10
3B
6
9
3A
7
8
3Y
10
3B
2Y
6
9
3A
GND
8
5
7
2B
2Y
3Y
GND
Figure 4-2. PW Package, 14 Pin TSSOP (Top View)
Not to scale
Figure 4-1. BQA Package, 14 Pin WQFN (Top View)
Table 4-1. Pin Functions
PIN
NAME
NO.
1A
1
1B
1Y
TYPE(1)
DESCRIPTION
I
Channel 1, Input A
2
I
Channel 1, Input B
3
O
Channel 1, Output Y
2A
4
I
Channel 2, Input A
2B
5
I
Channel 2, Input B
2Y
6
O
Channel 2, Output Y
GND
7
—
Ground
3Y
8
O
Channel 3, Output Y
3A
9
I
Channel 3, Input A
3B
10
I
Channel 3, Input B
4Y
11
O
Channel 4, Output Y
4A
12
I
Channel 4, Input A
4B
13
I
Channel 4, Input B
VCC
14
—
Positive Supply
—
The thermal pad can be connected to GND or left floating. Do not connect to any other
signal or supply.
Thermal Information(2)
(1)
(2)
I = input, O = output
For BQA package only.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
6.5
V
VI
Input voltage range(2)
-0.5
6.5
V
-0.5
VCC + 0.5
range(2)
VO
Output voltage
IIK
Input clamp current
VI < 0V
IOK
Output clamp current
VO < 0V
IO
Continuous output current
IO
Continuous output current through VCC or GND
TJ
Junction temperature
-65
Tstg
Storage temperature
-65
(1)
(2)
V
-50
mA
-50
mA
±50
mA
±100
mA
150
°C
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC
Electrostatic
discharge
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Specifications
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
IOL
4
Description
VCC
High-level output current
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
Condition
MIN
MAX
1.1
3.6
V
5.5
V
VCC
V
(High or low state)
VCC = 1.8V
-4
VCC = 2.3V
-8
VCC = 2.7V
-12
VCC = 3V
-24
VCC = 1.8V
4
VCC = 2.3V
8
VCC = 2.7V
12
VCC = 3V
24
-40
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UNIT
mA
mA
10
ns/V
125
°C
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5.4 Thermal Information
Package Options
THERMAL
METRIC(1)
PW (TSSOP)
BQA (WQFN)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
150.8
102.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
78.3
96.8
°C/W
RθJB
Junction-to-board thermal resistance
93.8
70.9
°C/W
ΨJT
Junction-to-top characterization parameter
24.7
16.6
°C/W
YJB
Junction-to-board characterization parameter
93.2
70.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
-
50.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
-40°C to 125°C
MIN
TYP
MAX
UNIT
VT+
Positive-going input threshold voltage
1.1V
0.5
0.8
V
VT+
Positive-going input threshold voltage
1.5V
0.7
1.11
V
VT+
Positive-going input threshold voltage
1.65V
0.4
1.3
V
VT+
Positive-going input threshold voltage
1.95V
0.6
1.5
V
VT+
Positive-going input threshold voltage
2.3V
0.8
1.7
V
VT+
Positive-going input threshold voltage
2.5V
0.8
1.7
V
VT+
Positive-going input threshold voltage
2.7V
0.8
2
V
VT+
Positive-going input threshold voltage
3V
0.9
2
V
VT+
Positive-going input threshold voltage
3.6V
1.1
2
V
VT-
Negative-going input threshold voltage
1.1V
0.2
0.6
V
VT-
Negative-going input threshold voltage
1.5V
0.34
0.75
V
VT-
Negative-going input threshold voltage
1.65V
0.2
0.9
V
VT-
Negative-going input threshold voltage
1.95V
0.3
1
V
VT-
Negative-going input threshold voltage
2.3V
0.4
1.2
V
VT-
Negative-going input threshold voltage
2.5V
0.4
1.2
V
VT-
Negative-going input threshold voltage
2.7V
0.4
1.4
V
VT-
Negative-going input threshold voltage
3V
0.6
1.5
V
VT-
Negative-going input threshold voltage
3.6V
0.8
1.7
V
ΔVT
Hysteresis (VT+ − VT−)
1.1V
0.07
0.53
V
ΔVT
Hysteresis (VT+ − VT−)
1.5V
0.18
0.60
V
ΔVT
Hysteresis (VT+ − VT−)
1.65V
0.1
1.2
V
ΔVT
Hysteresis (VT+ − VT−)
1.95V
0.2
1.3
V
ΔVT
Hysteresis (VT+ − VT−)
2.3V
0.3
1.3
V
ΔVT
Hysteresis (VT+ − VT−)
2.5V
0.3
1.3
V
ΔVT
Hysteresis (VT+ − VT−)
2.7V
0.3
1.1
V
ΔVT
Hysteresis (VT+ − VT−)
3V
0.3
1.2
V
ΔVT
Hysteresis (VT+ − VT−)
3.6V
0.3
1.2
V
VOH
IOH= –100μA
1.1V to 3.6V
VCC - 0.2
V
VOH
IOH= –4mA
1.65V
1.2
V
VOH
IOH= –8mA
2.3V
1.75
V
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5.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
IOH= –12mA
VOH
-40°C to 125°C
VCC
MIN
TYP
MAX
UNIT
2.7V
2.2
V
3V
2.4
V
2.2
VOH
IOH= –24mA
3V
VOL
IOH= 100μA
1.1V to 3.6V
0.15
V
V
VOL
IOH= 4mA
1.65V
0.45
V
VOL
IOH= 8mA
2.3V
0.7
V
VOL
IOH= 12mA
2.7V
VOL
IOH= 24mA
3V
II
VI = VCC or GND
3.6V
Ioff
VI or VO = VCC
0V
ICC
VI = VCC or GND, IO = 0
3.6V
ΔICC
One input at VCC - 0.6V, other inputs at
VCC or GND
2.7V to 3.6V
CI
VI = VCC or GND
3.3V
CO
VO = VCC or GND
3.3V
CPD
f = 10MHz
1.8V
31
pF
CPD
f = 10MHz
2.5V
31
pF
CPD
f = 10MHz
3.3V
32
pF
0.4
V
0.55
V
±5
µA
±10
µA
40
µA
500
µA
pF
pF
5.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information
PARAMETER
FROM
(INPUT)
TO (OUTPUT)
LOAD CAPACITANCE
VCC
-40°C to 125°C
MIN
TYP
MAX
UNIT
tpd
A or B
Y
CL = 15pF
1.2V ± 0.1V
12
44
ns
tpd
A or B
Y
CL = 15pF
1.5V ± 0.12V
9
15
ns
tpd
A or B
Y
CL = 30pF
1.8V ± 0.15V
10.2
ns
tpd
A or B
Y
CL = 30pF
2.5V ± 0.2V
6.9
ns
tpd
A or B
Y
CL = 50pF
2.7V
6.4
ns
tpd
A or B
Y
CL = 50pF
3.3V ± 0.3V
5.6
ns
3.3V ± 0.3V
1.5
ns
tsk(o)
5.7 Noise Characteristics
VCC = 3.3V, CL = 50pF, TA = 25°C
PARAMETER
6
DESCRIPTION
MIN
TYP
MAX
0.9
0.8
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
VOL(V)
Quiet output, minimum dynamic VOL
-0.8
-0.3
V
VOH(V)
Quiet output, minimum dynamic VOH
2.2
3.3
V
VIH(D)
High-level dynamic input voltage
2.0
VIL(D)
Low-level dynamic input voltage
V
0.8
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5.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
60
1.8 V
2.5 V
48
42
36
VOH (V)
ICC - Supply Current (µA)
54
30
24
18
12
6
0
0
0.25
0.5
0.75 1 1.25 1.5 1.75
VIN - Input Voltage (V)
2
2.25
2.5
0.6
2.5
0.55
2.45
0.5
2.4
0.45
2.35
0.4
2.3
0.35
2.25
0.3
0.25
2.1
2.05
-40°C
25°C
125°C
2.5
5
7.5
10
12.5 15
IOL (mA)
17.5
20
22.5
1.9
-16
25
Figure 5-3. Output Voltage vs Current in LOW State; 3.3V
Supply
0.4
0.3
VOH (V)
VOL (V)
0.25
0.15
0.1
-40°C
25°C
125°C
0.05
0
0
2
4
6
8
10
IOL (mA)
12
14
16
Figure 5-5. Output Voltage vs Current in LOW State; 2.5V
Supply
0
-14
-12
-10
-8
IOH (mA)
-6
-4
-2
0
Figure 5-4. Output Voltage vs Current in HIGH State; 2.5V
Supply
0.35
0.2
-2.5
-40°C
25°C
125°C
2
1.95
0
0
-5
2.2
0.2
0.1
-7.5
2.15
0.15
0.05
-40°C
25°C
125°C
Figure 5-2. Output Voltage vs Current in HIGH State; 3.3V
Supply
VOH (V)
VOL (V)
Figure 5-1. Supply Current Across Input Voltage 1.8V and 2.5V
Supply
3.3
3.25
3.2
3.15
3.1
3.05
3
2.95
2.9
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
-25 -22.5 -20 -17.5 -15 -12.5 -10
IOH (mA)
1.8
1.775
1.75
1.725
1.7
1.675
1.65
1.625
1.6
1.575
1.55
1.525
1.5
1.475
1.45
1.425
1.4
-8
-40°C
25°C
125°C
-7
-6
-5
-4
IOH (mA)
-3
-2
-1
Figure 5-6. Output Voltage vs Current in HIGH State; 1.8V
Supply
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5.8 Typical Characteristics (continued)
VOL (V)
TA = 25°C (unless otherwise noted)
0.28
0.26
0.24
0.22
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
0.5
-40°C
25°C
125°C
1.5
2.5
3.5
4.5
IOL (mA)
5.5
6.5
7.5
Figure 5-7. Output Voltage vs Current in LOW State; 1.8V Supply
8
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
VCC
Input
50%
50%
0V
From Output
Under Test
tPHL(1)
tPLH(1)
VOH
CL(1)
Output
50%
50%
VOL
(1) CL includes probe and test-fixture capacitance.
tPLH(1)
tPHL(1)
Figure 6-1. Load Circuit for Push-Pull Outputs
VOH
Output
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-3. Voltage Waveforms, Input and Output Transition Times
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7 Detailed Description
7.1 Overview
This device contains four independent 2-input AND gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A ● B in positive logic.
7.2 Functional Block Diagram
xA
xY
xB
7.3 Feature Description
7.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74LVC7001A can drive a load with a total capacitance less than or equal to the maximum load listed in
the Switching Characteristics connected to a high-impedance CMOS input while still meeting all of the datasheet
specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided
load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output
and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
7.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated
with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage
current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs slowly will also increase dynamic current consumption of the device. For additional information regarding
Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
7.3.3 Clamp Diode Structure
Figure 7-1 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
10
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VCC
Device
Logic
Input
-IIK
Output
-IOK
GND
Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output
7.4 Device Functional Modes
Table 7-1. Function Table
INPUTS
OUTPUT
A
B
Y
H
H
H
L
X
L
X
L
L
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in
Figure 8-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
This device is used to directly control the RESET pin of a motor controller. The controller requires four input
signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes LOW.
The 4-input AND gate function combines the four individual reset signals into a single active-low reset signal.
8.2 Typical Application
Power Supply
Over Current
Detection
Motor Controller
OC
PG
RESET
ON/OFF
OT
On/Off Switch
Over
Temp
Detection
Figure 8-1. Typical Application Schematic
8.2.1 Design Requirements
8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74LVC7001A plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
12
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8.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings .
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74LVC7001A, as specified in the Electrical Characteristics , and the desired input transition rate. A 10kΩ
resistor value is often used due to these factors.
The SN74LVC7001A has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics . This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to Section 7.3 for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 7.3 for additional information regarding the outputs for this device.
8.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 8.4.
2. Ensure the capacitive load at the output is ≤ 70pF. This is not a hard limit; however, it will
optimize performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LVC7001A to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will not violate the maximum
output current from the Absolute Maximum Ratings. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
8.2.3 Application Curves
OC
PG
ON/OFF
OT
RESET
Figure 8-2. Typical Application Timing Diagram
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8.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass
caps to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 8-3.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
8.4.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to the
device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused
inputs tied to
VCC
Unused
output left
floating
Figure 8-3. Example Layout for the SN74LVC7001A
14
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Introduction to Logic application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2024) to Revision A (March 2024)
Page
• Changed the status of the PW package from: preview to: active ......................................................................1
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC7001ABQAR
ACTIVE
WQFN
BQA
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC701A
Samples
SN74LVC7001APWR
ACTIVE
TSSOP
PW
14
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LVC7001
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of