SN54LVC74A, SN74LVC74A
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SCAS287T – JANUARY 1993 – REVISED JULY 2013
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
Check for Samples: SN54LVC74A, SN74LVC74A
FEATURES
DESCRIPTION
•
•
•
•
The SN54LVC74A dual positive-edge-triggered Dtype flip-flop is designed for 2.7-V to 3.6-V VCC
operation, and the SN74LVC74A dual positive-edgetriggered D-type flip-flop is designed for 1.65-V to 3.6V VCC operation.
1
3
12
4
11
5
10
6
9
7
8
1D
1CLK
1PRE
1Q
1Q
1
14
2
13 2CLR
3
4
12 2D
5
6
10 2PRE
9 2Q
11 2CLK
7
8
1CLK
NC
1PRE
NC
1Q
3
2CLR
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
4
2 1 20 19
18
5
6
17
16
7
8
15
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
2Q
2Q
13
1CLR
NC
VCC
14
2
1D
1
SN54LVC74A . . . FK PACKAGE
(TOP VIEW)
1Q
GND
NC
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
SN74LVC74A . . . RGY PACKAGE
(TOP VIEW)
VCC
SN54LVC74A . . . J OR W PACKAGE
SN74LVC74A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
The data I/Os and control inputs are overvoltage
tolerant. This feature allows the use of these devices
for down-translation in a mixed-voltage environment.
2Q
•
1CLR
•
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
GND
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
NC - No internal connection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2013, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC74A, SN74LVC74A
SCAS287T – JANUARY 1993 – REVISED JULY 2013
www.ti.com
FUNCTION TABLE
INPUTS
(1)
OUTPUTS
PRE
CLR
CLK
D
Q
L
H
X
X
H
Q
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP
(POSITIVE LOGIC)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
2
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Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
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SCAS287T – JANUARY 1993 – REVISED JULY 2013
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Output voltage range (2)
–0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through VCC or GND
D package
θJA
Package thermal impedance
(4)
86
DB package (4)
96
NS package (4)
76
PW package
(4)
(1)
(2)
(3)
(4)
(5)
°C/W
113
RGY package (5)
Tstg
V
47
Storage temperature range
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions (1)
SN54LVC74A
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
VCC = 1.65 V to 1.95 V
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
SN74LVC74A
MIN
1.7
2
V
2
VCC = 1.65 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2.7 V to 3.6 V
0.8
0.8
VCC = 1.65 V
IOH
–4
VCC = 2.3 V
High-level output current
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
VCC = 1.65 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
10
–55
125
–40
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
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SN54LVC74A, SN74LVC74A
SCAS287T – JANUARY 1993 – REVISED JULY 2013
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
–55°C TO 125°C (1)
–40°C TO 85°C (1)
SN54LVC74A
SN74LVC74A
MIN
IOH = –100 μA
2.7 V to 3.6 V
VOH
TYP
(1)
MAX
MIN TYP
VCC –
0.2
VCC –
0.2
1.65 V
1.2
1.2
IOH = –8 mA
2.3 V
1.7
1.7
2.7 V
2.2
2.2
2.2
3V
2.4
2.4
2.4
IOH = –24 mA
3V
2.2
2.2
2.2
IOL = 100 μA
1.65 V to 3.6
V
MAX
V
0.2
0.2
0.2
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.7
0.7
IOL = 12 mA
2.7 V
0.4
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
0.55
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ci
TYP
UNIT
VCC –
0.2
2.7 V to 3.6 V
ΔICC
MIN
SN74LVC74A
Recommended
IOH = –4 mA
IOH = –12 mA
VOL
MAX
1.65 V to 3.6
V
–40°C TO 125°C
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
V
3.6 V
±5
±5
±5
μA
3.6 V
10
10
10
μA
2.7 V to 3.6 V
500
500
500
μA
3.3 V
5
5
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC74A
fclock
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
4
VCC = 2.7 V
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83
100
PRE or CLR low
3.3
3.3
CLK high or low
3.3
3.3
Data
3.4
3
PRE or CLR inactive
2.2
2
1
1
UNIT
MHz
ns
ns
ns
Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
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SCAS287T – JANUARY 1993 – REVISED JULY 2013
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 85°C
VCC = 1.8 V
± 0.15 V
MIN
fclock
Recommended
VCC = 1.8 V
± 0.15 V
MAX
Clock frequency
–40°C to 125°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
VCC = 2.5 V
± 0.2 V
MAX
83
–40°C to 85°C
MIN
UNIT
VCC = 2.5 V
± 0.2 V
MAX
83
–40°C to 125°C
Recommended
MIN
MAX
83
83
PRE or CLR low
4.1
4.1
3.3
3.3
CLK high or low
4.1
4.1
3.3
3.3
Data
3.6
3.6
2.3
2.3
PRE or CLR inactive
2.7
2.7
1.9
1.9
1
1
1
1
MHz
ns
ns
ns
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 85°C
VCC = 2.7 V
MIN
fclock
Recommended
MIN
MAX
83
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
–40°C to 85°C
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
Clock frequency
–40°C to 125°C
MIN
UNIT
VCC = 3.3 V
± 0.3 V
MAX
83
–40°C to 125°C
Recommended
MIN
150
MAX
100
PRE or CLR low
3.3
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
3.3
Data
3.4
3.4
3
3
PRE or CLR inactive
2.2
2.2
2
2
1
1
0
1
MHz
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC74A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
fmax
MAX
83
CLK
tpd
Q or Q
PRE or CLR
MIN
UNIT
MAX
100
MHz
6
1
5.2
6.4
1
5.4
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–40°C to 85°C
VCC = 1.8 V
± 0.15 V
MIN
fmax
tpd
MAX
83
CLK
PRE or CLR
Q or Q
–40°C to 125°C
Recommended
VCC = 1.8 V
± 0.15 V
MIN
MAX
83
–40°C to 85°C
VCC = 2.5 V
± 0.2 V
MIN
MAX
83
–40°C to 125°C
Recommended
UNIT
VCC = 2.5 V
± 0.2 V
MIN
MAX
83
MHz
1
7.1
1
7.1
1
4.4
1
4.4
1
6.9
1
6.9
1
4.6
1
4.6
tsk(o)
ns
ns
Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
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SN54LVC74A, SN74LVC74A
SCAS287T – JANUARY 1993 – REVISED JULY 2013
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–40°C to 125°C
–40°C to 85°C
Recommended
VCC = 2.7 V
MIN
fmax
tpd
MAX
CLK
PRE or CLR
Q or Q
MIN
Recommended
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
83
–40°C to 125°C
–40°C to 85°C
MAX
83
MIN
MAX
150
MIN
MAX
100
MHz
1
6
6
1
5.2
5.2
1
6.4
6.4
1
5.4
5.4
tsk(o)
UNIT
VCC = 3.3 V
± 0.3 V
1
ns
ns
Operating Characteristics
TA = 25°C
Cpd
6
PARAMETER
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
Power dissipation capacitance per flip-flop
f = 10 MHz
24
24
26
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UNIT
pF
Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
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SCAS287T – JANUARY 1993 – REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1993–2013, Texas Instruments Incorporated
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SCAS287T – JANUARY 1993 – REVISED JULY 2013
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REVISION HISTORY
Changes from Revision S (May 2005) to Revision T
•
8
Page
Extended maximum temperature operating range from 85°C to 125°C. .............................................................................. 3
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9761601Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629761601Q2A
SNJ54LVC
74AFK
5962-9761601QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601QC
A
SNJ54LVC74AJ
5962-9761601QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601QD
A
SNJ54LVC74AW
5962-9761601V2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629761601V2A
SNV54LVC
74AFK
5962-9761601VCA
ACTIVE
CDIP
J
14
25
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601VC
A
SNV54LVC74AJ
5962-9761601VDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601VD
A
SNV54LVC74AW
SN74LVC74AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
-40 to 125
SN74LVC74ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74ADBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Orderable Device
20-Jan-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC74ADRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADTE4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ADTG4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74ANSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC74A
SN74LVC74APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
SN74LVC74APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74APWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC74A
SN74LVC74ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC74A
SN74LVC74ARGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC74A
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
20-Jan-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54LVC74AFK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629761601Q2A
SNJ54LVC
74AFK
SNJ54LVC74AJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601QC
A
SNJ54LVC74AJ
SNJ54LVC74AW
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9761601QD
A
SNJ54LVC74AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A :
• Catalog: SN74LVC74A, SN54LVC74A
• Automotive: SN74LVC74A-Q1, SN74LVC74A-Q1
• Enhanced Product: SN74LVC74A-EP, SN74LVC74A-EP
• Military: SN54LVC74A
• Space: SN54LVC74A-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC74ADBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LVC74ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC74ADT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC74ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC74APWR
TSSOP
PW
14
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
SN74LVC74APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC74APWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC74APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC74ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC74ADBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74LVC74ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LVC74ADT
SOIC
D
14
250
367.0
367.0
38.0
SN74LVC74ANSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LVC74APWR
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74LVC74APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC74APWRG4
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC74APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LVC74ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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• DALLAS, TEXAS 75265
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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