SN74LVC8T245
SCES584C – JUNE 2005 – REVISED DECEMBER 2022
SN74LVC8T245 8-Bit Dual-Supply Bus Transceiver With
Configurable Voltage Translation and 3-State Outputs
1 Features
3 Description
•
The SN74LVC8T245 is an eight bit non-inverting bus
transceiver with configurable dual power supply rails
that enables bidirectional voltage level translation.
The SN74LVC8T245 is optimized to operate with
VCCA and VCCB set at 1.65 V to 5.5 V. The A port
is designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 5.5 V. The B port is designed
to track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V, 2.5V, 3.3-V, and 5.5-V voltage nodes.
•
•
•
•
Control inputs VIH/VIL levels are referenced to
VCCA voltage
VCC isolation feature – if either VCC input is at
GND, all are in the high-impedance state
Fully configurable dual-rail design allows each port
to operate over the full 1.65-V to 5.5-V powersupply range
Latch-up performance exceeds 100 mA per JESD
78, class II
ESD protection exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 100-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Personal electronic
Industrial
Enterprise
Telecom
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
Logic Diagram (Positive Logic)
The SN74LVC8T245 is designed for asynchronous
communication between two data buses. The logic
levels of the direction-control (DIR) input and the
output-enable (OE) input activate either the B-port
outputs or the A-port outputs or place both output
ports into the high-impedance mode. The device
transmits data from the A bus to the B bus when the
B-port outputs are activated, and from the B bus to
the A bus when the A-port outputs are activated. The
input circuitry on both A and B ports is always active
and must have a logic HIGH or LOW level applied to
prevent excess ICC and ICCZ.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the device when it is powered down. The VCC
isolation feature ensures that if either VCC input is
at GND, all outputs are in the high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through
a pullup resistor; the minimum value of the resistor
is determined by the current-sinking capability of the
driver.
The SN74LVC8T245 is designed so that the control
pins (DIR and OE) are supplied by VCCA.
Package Information
PART NUMBER
SN74LVC8T245
(1)
PACKAGE(1)
BODY SIZE (NOM)
DBV (SSOP, 24)
8.20 mm × 5.30 mm
DBQ (SSOP, 24)
8.65 mm × 3.90 mm
PW (TSSOP, 24)
7.80 mm × 4.40 mm
DGV (TVSOP, 24)
5.00 mm × 4.40 mm
RHL (VQFN, 24)
5.50 mm × 3.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC8T245
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SCES584C – JUNE 2005 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information DB, DBQ and DGV.................... 6
6.5 Thermal Information PW and RHL..............................6
6.6 Electrical Characteristics ............................................7
6.7 Switching Characteristics, VCCA = 1.8 V ± 0.15 V.......8
6.8 Switching Characteristics, VCCA = 2.5 V ± 0.2 V.........8
6.9 Switching Characteristics, VCCA = 3.3 V ± 0.3 V.........9
6.10 Switching Characteristics, VCCA = 5 V ± 0.5 V..........9
6.11 Operating Characteristics..........................................9
6.12 Typical Characteristics............................................ 10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................13
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Receiving Notification of Documentation Updates..17
12.2 Support Resources................................................. 17
12.3 Trademarks............................................................. 17
12.4 Electrostatic Discharge Caution..............................17
12.5 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2014) to Revision C (December 2022)
Page
• Removed Machine Model specification.............................................................................................................. 1
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the ESD Ratings section (was called Handling Ratings)......................................................................4
• Updated thermals in the Thermal Informations section. .................................................................................... 6
• Increased max switching characterisitics specs for VccB = 5V.......................................................................... 8
• Updated the Overview section..........................................................................................................................12
• Added the Balanced High-Drive CMOS Push-Pull Outputs and VCC Isolation sections...................................12
• Updated the Power Supply Recommendations section....................................................................................15
Changes from Revision A (June 2005) to Revision B (November 2014)
Page
• Added the list of Application, Pin Functions table, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section. .............................................................................................................................................................. 1
• Changed Feature From: 200-V Machine Model (A115-A) To: 100-V Machine Model (A115-A) ........................ 1
Changes from Revision * (June 2005) to Revision A (August 2005)
Page
• Changed the device From: Product Preview To: Production.............................................................................. 1
2
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23
VCCB
A1
3
22
OE
A2
4
21
B1
A3
5
20
B2
A4
6
19
B3
24
2
1
DIR
VCCB
VCCA
5 Pin Configuration and Functions
Thermal
Pad
B4
A6
8
17
B5
A7
9
16
B6
A8
10
15
B7
GND
11
14
B8
GND
13
18
12
7
GND
Figure 5-1. DW, NS, DB, DBQ, DGV, or PW
Package, 24-Pin SOIC, SO, SSOP, SSOP, TVSOP, or
TSSOP (Top View)
A5
Not to scale
Figure 5-2. RHL Package, 24-Pin VQFN (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
A1
3
I/O
Input/output A1. Referenced to VCCA.
A2
4
I/O
Input/output A2. Referenced to VCCA.
A3
5
I/O
Input/output A3. Referenced to VCCA.
A4
6
I/O
Input/output A4. Referenced to VCCA.
A5
7
I/O
Input/output A5. Referenced to VCCA.
A6
8
I/O
Input/output A6. Referenced to VCCA.
A7
9
I/O
Input/output A7. Referenced to VCCA.
A8
10
I/O
Input/output A8. Referenced to VCCA.
B1
21
I/O
Input/output B1. Referenced to VCCB.
B2
20
I/O
Input/output B2. Referenced to VCCB.
B3
19
I/O
Input/output B3. Referenced to VCCB.
B4
18
I/O
Input/output B4. Referenced to VCCB.
B5
17
I/O
Input/output B5. Referenced to VCCB.
B6
16
I/O
Input/output B6. Referenced to VCCB.
B7
15
I/O
Input/output B7. Referenced to VCCB.
B8
14
I/O
Input/output B8. Referenced to VCCB.
DIR
2
I
Direction-control signal.
GND
11, 12, 13
G
Ground
OE
22
I
3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to
VCCA.
VCCA
1
P
A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V
VCCB
23, 24
P
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V
Thermal Pad(2)
(1)
(2)
—
I = input, O = output, P = power
For the RHL package only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
–0.5
6.5
I/O ports (A port)
–0.5
6.5
I/O ports (B port)
–0.5
6.5
Control inputs
–0.5
6.5
A port
–0.5
6.5
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
Supply voltage range, VCCA, VCCB
Input voltage range(2)
VI
UNIT
V
V
VO
Voltage range applied to any output
in the high-impedance or power-off state(2)
VO
Voltage range applied to any output in the high or low state(2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through each VCCA, VCCB, and GND
Tstg
Storage temperature
TJ
Junction temperature
(1)
(2)
(3)
V
V
±50
mA
±100
mA
150
°C
150
°C
-65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
V(ESD)
(1)
(2)
4
Electrostatic discharge
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–4000
4000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
–1000
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
(1) (2) (3) (4)
VCCA
VCCI
VCCO
Supply voltage
VCCB
1.65 V to 1.95 V
High-level
input voltage
VIH
MAX
1.65
5.5
1.65
5.5
1.7
3 V to 3.6 V
VCCI × 0.7
1.65 V to 1.95 V
Low-level
input voltage
Data inputs(5)
VCCI × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
4.5 V to 5.5 V
High-level
input voltage
Control inputs
(referenced to VCCA)(6)
VCCA × 0.65
2.3 V to 2.7 V
1.7
3 V to 3.6 V
VCCA × 0.7
1.65 V to 1.95 V
Low-level
input voltage
Control inputs
(referenced to VCCA)(6)
VCCA × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
4.5 V to 5.5 V
VI
VI/O
Input voltage
Control inputs
0
5.5
V
Input/output
voltage
Active state
0
VCCO
V
0
5.5
V
3-State
High-level output current
–4
2.3 V to 2.7 V
–8
3 V to 3.6 V
–24
4.5 V to 5.5 V
–32
1.65 V to 1.95 V
IOL
Low-level output current
Δt/Δv(7)
TA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
V
VCCA × 0.3
1.65 V to 1.95 V
IOH
V
2
4.5 V to 5.5 V
VIL
V
VCCI × 0.3
1.65 V to 1.95 V
VIH
V
V
2
4.5 V to 5.5 V
VIL
UNIT
VCCI × 0.65
2.3 V to 2.7 V
Data inputs(5)
MIN
Input transition
rise or fall rate
Data inputs
4
2.3 V to 2.7 V
8
3 V to 3.6 V
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
20
2.3 V to 2.7 V
20
3 V to 3.6 V
10
4.5 V to 5.5 V
5
Operating free-air temperature
mA
–40
85
mA
ns/V
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure
proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
All unused control inputs must be held at VCCA or GND to ensure proper device operation and minimize power comsumption.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
Maximum input transition rate with < 4 channels switching simultaneously.
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6.4 Thermal Information DB, DBQ and DGV
THERMAL METRIC(1)
DB
DBQ
DGV
24 PINS
24 PINS
24 PINS
RθJA
Junction-to-ambient thermal resistance
90.7
81.2
91.1
RθJC(top)
Junction-to-case (top) thermal resistance
51.9
44.8
23.7
RθJB
Junction-to-board thermal resistance
49.7
34.5
44.5
ψJT
Junction-to-top characterization parameter
18.8
9.5
0.6
ψJB
Junction-to-board characterization parameter
49.3
37.2
44.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information PW and RHL
THERMAL METRIC(1)
RHL
24 PINS
24 PINS
RθJA
Junction-to-ambient thermal resistance
100.6
48.3
RθJC(top)
Junction-to-case (top) thermal resistance
44.7
46.1
RθJB
Junction-to-board thermal resistance
55.8
26.1
ψJT
Junction-to-top characterization parameter
6.8
4.6
ψJB
Junction-to-board characterization parameter
55.4
26.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
15.7
(1)
6
PW
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1) (2)
VOH
VOL
II
DIR
VCCA
VCCB
IOH = –100 μA,
TEST CONDITIONS
VI = VIH
1.65 V to 4.5 V
1.65 V to 4.5 V
IOH = –4 mA,
VI = VIH
1.65 V
1.65 V
1.2
IOH = –8 mA,
VI = VIH
2.3 V
2.3 V
1.9
IOH = –24 mA,
VI = VIH
3V
3V
2.4
IOH = –32 mA,
VI = VIH
4.5 V
4.5 V
3.8
IOL = 100 μA,
VI = VIL
1.65 V to 4.5 V
1.65 V to 4.5 V
0.1
IOL = 4 mA,
VI = VIL
1.65 V
1.65 V
0.45
IOL = 8 mA,
VI = VIL
2.3 V
2.3 V
0.3
IOL = 24 mA,
VI = VIL
3V
3V
0.55
IOL = 32 mA,
VI = VIL
4.5 V
4.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
0V
0 to 5.5 V
±1
±2
0 to 5.5 V
0V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
15
5V
0V
15
0V
5V
–2
1.65 V to 5.5 V
1.65 V to 5.5 V
15
5V
0V
–2
0V
5V
15
1.65 V to 5.5 V
1.65 V to 5.5 V
25
VI = VCCA or GND
Ioff
A or B
port
VI or VO = 0 to 5.5 V
IOZ
A or B
port
VO = VCCO or GND,
OE = VIH
ICCA
VI = VCCI or GND,
ICCB
VI = VCCI or GND,
ICCA + ICCB
VI = VCCI or GND,
IO = 0
IO = 0
IO = 0
A port
One A port at VCCA – 0.6 V,
DIR at VCCA, B port = open
DIR
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
ΔICCB
B port
One B port at VCCB – 0.6 V,
DIR at GND, A port = open
Ci
Control
inputs
Cio
A or B
port
ΔICCA
(1)
(2)
MIN
TYP
MAX
MIN
MAX
UNIT
VCCO – 0.1
V
V
0.55
μA
μA
μA
μA
μA
μA
50
3 V to 5.5 V
3 V to 5.5 V
μA
50
3 V to 5.5 V
3 V to 5.5 V
VI = VCCA or GND
3.3 V
3.3 V
VO = VCCA/B or GND
3.3 V
3.3 V
50
μA
4
5
pF
8.5
10
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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6.7 Switching Characteristics, VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN MAX
B
1.7
21.9
1.3
9.2
1
7.4
0.8
7.1
ns
B
A
0.9
23.8
0.8
23.6
0.7
23.4
0.7
23.4
ns
OE
A
1.5
29.6
1.5
29.4
1.5
29.3
1.4
29.2
ns
OE
B
2.4
32.2
1.9
13.1
1.7
12
1.3
10.3
ns
OE
A
0.4
24
0.4
23.8
0.4
23.7
0.4
23.7
ns
OE
B
1.8
32
1.5
16
1.2
12.6
0.9
12
ns
6.8 Switching Characteristics, VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
8
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
1.5
B
A
OE
MIN MAX
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
21.4
1.2
9
0.8
6.2
0.6
4.8
ns
1.2
9.3
1
9.1
1
8.9
0.9
8.8
ns
A
1.4
9
1.4
9
1.4
9
1.4
9
ns
OE
B
2.3
29.6
1.8
11
1.7
9.3
0.9
6.9
ns
OE
A
1
10.9
1
10.9
1
10.9
1
10.9
ns
OE
B
1.7
28.2
1.5
12.9
1.2
9.4
1
7.5
ns
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6.9 Switching Characteristics, VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
1.5
B
A
OE
VCCB = 2.5 V
± 0.2 V
MIN MAX
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN MAX
21.2
1.1
8.8
0.8
6.3
0.5
4.4
ns
0.8
7.2
0.8
6.2
0.7
6.1
0.6
6
ns
A
1.6
8.2
1.6
8.2
1.6
8.2
1.6
8.2
ns
OE
B
2.1
29
1.7
10.3
1.5
8.6
0.8
6.3
ns
OE
A
0.8
8.1
0.8
8.1
0.8
8.1
0.8
8.1
ns
OE
B
1.8
27.7
1.4
12.4
1.1
8.8
0.9
6.8
ns
6.10 Switching Characteristics, VCCA = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN MAX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
B
1.5
21.4
1
8.8
0.7
6
0.4
4.2
ns
B
A
0.7
7
0.4
4.8
0.3
4.5
0.3
4.3
ns
OE
A
0.3
5.4
0.3
5.4
0.3
5.4
0.3
5.4
ns
OE
B
2
28.7
1.6
9.7
1.4
8
0.7
5.7
ns
OE
A
0.7
6.4
0.7
6.4
0.7
6.4
0.7
6.4
ns
OE
B
1.5
27.6
1.3
11.4
1
8.8
0.9
6.6
ns
6.11 Operating Characteristics
TA = 25°C
PARAMETER
CpdA (1)
CpdB
(1)
(1)
TEST
CONDITIONS
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
B-port input, A-port output
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
VCCA =
VCCB = 5 V
TYP
TYP
TYP
TYP
2
2
2
3
12
13
13
16
13
13
14
16
2
2
2
3
UNIT
pF
Power dissipation capacitance per transceiver
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1.4
5.6
1.2
5.4
1.0
5.2
VOH Voltage (V)
VOL Voltage (V)
6.12 Typical Characteristics
0.8
0.6
0.4
4.8
4.6
o
-40 C
o
25 C
0.2
5.0
o
-40 C
o
25 C
4.4
o
o
85 C
85 C
4.2
0
0
20
40
60
80
100
0
-20
IOL Current (mA)
Figure 6-1. Voltage vs Current
10
-40
-60
-80
-100
IOH Current (mA)
Figure 6-2. Voltage vs Current
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7 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC8T245 is an eight bit non-inverting bus transceiver with configurable dual power supply rails that
enables bidirectional voltage level translation. Pin Ax and direction control pin are support by VCCA and pin Bx
is support by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can
accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data transmission from A to B and a low on
DIR allows data transmission from B to A. For voltage level translation below 1.65 V, see TI AXC products.
8.2 Functional Block Diagram
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for
translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V, and 5 V).
8.3.2 Ioff Supports Partial-Power-Down Mode Operation
Ioff prevents backflow current by disabling I/O output circuits when device is in partial-power-down mode.The
inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.3 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. Two outputs can be connected together for 2X stronger output drive strength. The electrical and
thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.4 Vcc Isolation
The I/O's of both ports will enter a high-impedance state when either of the supplies are at GND, while the other
supply is still connected to the device. The maximum leakage into or out of any input or output pin on the device
is specified by Ioff in the Electrical Characteristics.
12
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8.4 Device Functional Modes
The SN74LVC8T245 is voltage level translator that can operate from 1.65 V to 5.5 V (VCCA and VCCB). The
signal translation between 1.65 V and 5.5 V requires direction control and output enable control. When OE is low
and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data transmission is from B to
A. When OE is high, both output ports will be high-impedance. For voltage level translation below 1.65V, see TI
AXC products.
Table 8-1. Function Table
(Each 8-Bit Section)
CONTROL INPUTS(1)
OE
(1)
OUTPUT CIRCUITS
DIR
A PORT
OPERATION
B PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os are always active.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC8T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The maximum output current can be up to 32 mA when
device is powered by 5 V. It is recommended to tie all unused I/Os to GND. The device should not have any
floating I/Os when changing translation direction.
9.2 Typical Application
1.8V
5V
0.1 F
0.1 F
VCCA
1 µF
VCCB
DIR
OE
1.8V
Controller
Data
GND
5V
System
SN74LVC8T245
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
GND
Data
GND
Figure 9-1. Typical Application Circuit
14
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9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
VALUES
Input voltage range
1.65 V to 5.5 V
Output voltage
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVC8T245 device to determine the input
voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low,
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVC8T245 device is driving to determine the output
voltage range.
9.2.3 Application Curve
Voltage (V)
Output (5 V)
Input (1.8 V)
Time (200 ns/div)
Figure 9-2. Translation Up (1.8 V to 5 V) at 2.5 MHz
10 Power Supply Recommendations
The SN74LVC8T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port
and B port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation
between any of the 1.8-V, 2.5 -V, 3.3-V and 5-V voltage nodes. The recommendation is to first power-up the
input supply rail to help avoid internal floating while the output supply rail ramps up. However, both power-supply
rails can be ramped up simultaneously.
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11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
•
•
•
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCC
VCC
B
A
Bypass Capacitor
Bypass Capacitor
VCC
1
VCC 24
VCC
A
2
A
B
Keep OE high until VCCA
and VCCB are powered up
VCC 23
DIR
B
From
Controller
3
A1
OE 22
From
Controller
4
A2
B1
21
To
System
From
Controller
5
A3
B2
20
To
System
From
Controller
6
A4
B3
19
To
System
From
Controller
7
A5
B4
18
To
System
From
Controller
8
A6
B5
17
To
System
From
Controller
9
A7
B6
16
To
System
From
Controller
10
A8
B7
15
To
System
11 GND
B8
14
To
System
12 GND
GN
D
13
SN74LVC8T245-Q1
Figure 11-1. SN74LVC8T245 Layout
16
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74LVC8T245DBQRG4
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVC8T245
Samples
74LVC8T245RHLRG4
ACTIVE
VQFN
RHL
24
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
NH245
Samples
SN74LVC8T245DBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVC8T245
Samples
SN74LVC8T245DBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245DBRG4
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245DGVR
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245DGVRG4
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC8T245
Samples
SN74LVC8T245DWRG4
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC8T245
Samples
SN74LVC8T245NSR
ACTIVE
SO
NS
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC8T245
Samples
SN74LVC8T245PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245PWG4
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245PWRE4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245PWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
NH245
Samples
SN74LVC8T245RHLR
ACTIVE
VQFN
RHL
24
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
NH245
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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13-Dec-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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