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SN74LVCC3245A
SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
SN74LVCC3245A Octal Bus Transceiver With Adjustable Output Voltage
and 3-State Outputs
1 Features
3 Description
•
•
The SN74LVCC3245A device is 8-bit (octal)
noninverting bus transceiver contains two separate
supply rails. The B port is designed to track VCCB,
which accepts voltages from 3 V to 5.5 V, and the A
port is designed to track VCCA, which operates at 2.3
V to 3.6 V. This allows for translation from a 3.3-V to
a 5-V system environment and vice versa, from a
2.5-V to a 3.3-V system environment and vice versa.
1
•
•
•
Bidirectional Voltage Translator
2.3 V to 3.6 V on A Port and 3 V to 5.5 V
on B Port
Control Inputs VIH and VIL Levels Are Referenced
to VCCA Voltage
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Level translation
USB
Interfacing
Analog and Digital Applications
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVCC3245ADBQ SSOP (24)
8.65 mm × 3.90 mm
SN74LVCC3245ADW
SOIC (24)
15.40 mm × 7.50 mm
SN74LVCC3245ADB
SSOP (24)
8.20 mm × 5.30 mm
SN74LVCC3245ANS
SO (24)
15.00 mm × 5.30 mm
SN74LVCC3245APW
TSSOP (24)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
DIR
2
22
OE
A1
3
21
B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCC3245A
SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
6
7
8
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
7.1 A Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3
V)................................................................................ 9
7.2 B Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3
V).............................................................................. 10
7.3 B Port (VCCA = 3.6 V and VCCB = 5.5 V)................. 11
7.4 A and B Port (VCCA and VCCB = 3.6 V) ................... 12
8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
11.3 Power-Up Considerations .................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (March 2005) to Revision P
Page
•
Added Applications section, Device Information table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
2
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SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
DB, DBQ, DW, NS, or PW Package
24-Pin SSOP, SOIC, SO, or TSSOP
Top View
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC – No internal connection
See Mechanical, Packaging, and Orderable Information for dimensions.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A1
3
I/O
A1 port
A2
4
I/O
A2 port
A3
5
I/O
A3 port
A4
6
I/O
A4 port
A5
7
I/O
A5 port
A6
8
I/O
A6 port
A7
9
I/O
A7 port
A8
10
I/O
A8 port
B1
21
I/O
B1 port
B2
20
I/O
B2 port
B3
19
I/O
B3 port
B4
18
I/O
B4 port
B5
17
I/O
B5 port
B6
16
I/O
B6 port
B7
15
I/O
B7 port
B8
14
I/O
B8 port
2
I
Dir input
--
Ground
DIR
11
GND
12
13
NC
23
--
Unconnected
OE
22
I
Output Enable active low
VCCA
1
--
A port power
VCCB
24
--
B port power
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SN74LVCC3245A
SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
VCCB
Supply voltage
Input voltage
MAX
UNIT
V
–0.5
6
(2)
–0.5
VCCA + 0.5
All B ports (3)
–0.5
VCCB + 0.5
All A ports
VI
MIN
Except I/O ports
(2)
–0.5
VCCA + 0.5
All A ports
–0.5
VCCA + 0.5
All B ports
–0.5
VCCB + 0.5
V
VO
Output voltage (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
±100
mA
150
°C
150
°C
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 4.6 V maximum.
This value is limited to 6 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCCA
VCCB
MIN
NOM
MAX
UNIT
VCCA
Supply voltage
2.3
3.3
3.6
V
VCCB
Supply voltage
3
5
5.5
V
VIHA
VIHB
VILA
(1)
4
High-level input voltage
High-level input voltage
Low-level input voltage
2.3 V
3V
1.7
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
2
2.3 V
3V
2
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
3.85
2.3 V
3V
0.7
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
0.8
V
V
V
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, SCBA004.
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Recommended Operating Conditions(1) (continued)
VILB
Low-level input voltage
High-level input voltage (control terminals)
(referenced to VCCA)
VIH
Low-level input voltage (control terminals)
(referenced to VCCA)
VIL
VCCA
VCCB
2.3 V
3V
MIN
NOM
MAX
0.8
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
2.3 V
3V
1.7
2.7 V
3V
2
3V
3.6 V
2
3.6 V
5.5 V
2
2.3 V
3V
0.7
2.7 V
3V
0.8
3V
3.6 V
0.8
3.6 V
5.5 V
0.8
UNIT
V
1.65
V
V
VIA
Input voltage
0
VCCA
V
VIB
Input voltage
0
VCCB
V
VOA
Output voltage
0
VCCA
V
VOB
Output voltage
0
VCCB
V
IOHA
IOHB
IOLA
High-level output current
High-level output current
Low-level output current
IOLB
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
2.3 V
3V
–8
2.7 V
3V
–12
3V
3V
–24
2.7 V
4.5 V
–24
2.3 V
3V
–12
2.7 V
3V
–12
3V
3V
–24
2.7 V
4.5 V
–24
2.3 V
3V
8
2.7 V
3V
12
3V
3V
24
2.7 V
4.5 V
24
2.3 V
3V
12
2.7 V
3V
12
3V
3V
24
2.7 V
4.5 V
24
–40
mA
mA
mA
mA
10
ns/V
85
°C
6.4 Thermal Information
SN74LVCC3245A
THERMAL METRIC
RθJA
(1)
(2)
(1) (2)
Junction-to-ambient thermal resistance
DB (SSOP)
DBQ
(SSOP)
DW (SOIC)
NS (SO)
PW (TSSOP)
24 PINS
24 PINS
24 PINS
24 PINS
24 PINS
63
61
46
65
88
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
IOH = –8 mA
VOHA
IOH = –12 mA
TYP
3
3V
3V
2.9
2.3 V
3V
2
2.7 V
3V
2.2
2.5
3V
3V
2.4
2.8
2.2
2.6
2
2.3
3
MAX
3V
3V
3V
2.9
2.3 V
3V
2.4
2.7 V
3V
2.4
2.8
3V
3V
2.2
2.6
2.7 V
4.5 V
3.2
4.2
3V
3V
IOL = 8 mA
2.3 V
3V
IOL = 12 mA
2.7 V
3V
0.1
0.5
IOH = –24 mA
IOL = 100 μA
V
0.1
0.6
3V
3V
0.2
0.5
2.7 V
4.5 V
0.2
0.5
IOL = 100 μA
3V
3V
IOL = 12 mA
2.3 V
3V
3V
3V
0.2
0.5
2.7 V
4.5 V
0.2
0.5
3.6 V
±0.1
±1
5.5 V
±0.1
±1
IOL = 24 mA
IOL = 24 mA
0.4
Control inputs
VI = VCCA or GND
IOZ (1)
A or B ports
VO = VCCA/B or GND,
VI = VIL or VIH
3.6 V
3.6 V
±0.5
±5
A port = VCCA or GND,
IO = 0
3.6 V
Open
5
50
B port = VCCB or GND,
IO = 0
3.6 V
3.6 V
5
50
5.5 V
5
50
A to B
A port = VCCA or GND,
IO = 0
3.6 V
3.6 V
5
50
5.5 V
8
80
A port
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND and DIR at VCCA
3.6 V
3.6 V
0.35
0.5
OE
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
DIR at VCCA
3.6 V
3.6 V
0.35
0.5
DIR
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND
3.6 V
3.6 V
0.35
0.5
ΔICCB (2)
B port
VI = VCCB – 2.1 V, Other inputs at VCCB or GND,
OE at GND and DIR at GND
3.6 V
5.5 V
1
1.5
Ci
Control inputs
VI = VCCA or GND
Open
Open
Cio
A or B ports
VO = VCCA/B or GND
3.3 V
5V
B to A
ICCB
ΔICCA (2)
(1)
(2)
6
V
0.1
II
ICCA
3.6 V
UNIT
V
4.5 V
IOH = –12 mA
VOLB
MIN
3V
IOH = –100 μA
VOLA
VCCB
2.7 V
IOH = –24 mA
VOHB
VCCA
V
μA
μA
μA
μA
mA
mA
4
pF
18.5
pF
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC.
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
PARAMETER
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
A
B
B
OE
OE
OE
OE
OE
B
B
A
A
A
A
B
B
A
VCCA, VCCB
MIN
MAX
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
9.4
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
6
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
7.1
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
9.1
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
5.3
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
7.2
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
11.2
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
5.8
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
6.4
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
9.9
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
7
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
7.6
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
14.5
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
9.2
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
9.7
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
12.9
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
9.5
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
9.5
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
13
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
8.1
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
9.2
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
12.8
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
8.4
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
9.9
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
7.1
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
7
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
6.6
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UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
SN74LVCC3245A
SCAS585P – NOVEMBER 1996 – REVISED DECEMBER 2015
www.ti.com
Switching Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
FROM
(INPUT)
PARAMETER
tPHZ
TO
(OUTPUT)
OE
tPLZ
A
OE
tPHZ
VCCA, VCCB
B
OE
B
MIN
MAX
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
6.9
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
7.8
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
6.9
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
8.8
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
7.3
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
7.5
VCCA = 2.5 V ± 0.2 V, VCCB = 3.3 V ±
0.3 V
1
8.9
VCCA = 2.7 V TO 3.6 V, VCCB = 5 V ±
0.5 V
1
7
VCCA = 2.7 V TO 3.6 V, VCCB = 3.3 V ±
0.3 V
1
7.9
UNIT
ns
ns
ns
6.7 Operating Characteristics
VCCA = 3.3 V, VCCB = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per transceiver
CL = 50,
Outputs disabled
f = 10 MHz
TYP
38
4.5
UNIT
pF
6.8 Typical Characteristics
3
IOH
@0.1mA
2.75
VOHA
(min) V
2.5
VCCB@
3V
2.25
IOH
@12mA
2
IOH
@8mA
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vcca(V)
Figure 1. VOHA(min) VS VCCA
8
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7 Parameter Measurement Information
7.1 A Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V)
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC
Timing
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
Output
Control
(low-level
enabling)
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
0V
tPZL
VCC
Input
VCC/2
0V
0V
tsu
Output
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns,
tf ≤ 2 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZHare the same as ten.
G.
tPLH and tPHL are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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7.2 B Port (VCCA = 2.5 V ± 0.2 V and VCCB = 3.3 V ± 0.3 V)
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
VCC
Timing
Input
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
Output
Control
(low-level
enabling)
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
0V
tPZL
VCC
Input
VCC/2
0V
0V
tsu
Output
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns,
tf ≤ 2 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPLH and tPHL are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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7.3 B Port (VCCA = 3.6 V and VCCB = 5.5 V)
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
B-Port
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
1.5 V
Input
1.5 V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
0V
tPHL
tPLH
B-Port
Output
50% VCC
VOH
50% VCC
VOL
2.7 V
Output
Control
0V
1.5 V
1.5 V
0V
tPLZ
tPZL
VCC
50% VCC
VOL + 0.3 V
tPHZ
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOL
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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7.4 A and B Port (VCCA and VCCB = 3.6 V)
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
tw
2.7 V
1.5 V
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
1.5 V
Input
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
2.7 V
Output
Control
0V
1.5 V
1.5 V
0V
tPLZ
tPZL
3.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.3 V
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74LVCC3245A device is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA .
8.2 Functional Block Diagram
DIR
2
22
OE
A1
3
21
B1
To Seven Other Channels
8.3 Feature Description
This device is a bidirectional level translator designed to operate from 2.3 V to 3.6 V on Port A and 3 V to 5.5 V
on B port. The control inputs recommended operating specifications are referenced with respect to VCCA Voltage.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVCC3245A.
Table 1. Function Table (Each Transceiver)
INPUTS
OE
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVCC3245A device is a bidirectional level translator designed to operate from 2.3 V to 3.6 V on Port A
and 3 V to 5.5 V on B port and designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
9.2 Typical Application
3.3V
5V
0.1 F
VCCA
VCCB
0.1 F
DIR
OE
A1
Master
B1
:
:
:
:
:
:
:
:
:
:
A8
Slave
B8
GND
Figure 6. Typical Application
9.2.1 Design Requirements
This device can be used as bidirectional level translator depending on the DIR pin. The application describes the
level translation of Master with signals at 3.3 V to slave operating at 5 V. The OE pin is low and DIR pin is 3.3-V
high.
14
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Typical Application (continued)
9.2.2 Detailed Design Procedure
Use the procedure that follows for the design:
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Absolute Maximum Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– All the voltages on A and B ports should not exceed above VCCA or VCCB to prevent the biasing of
Electrostatic discharge (ESD) diodes.
9.2.3 Application Curve
3
2.75
VOHB
(min) V
2.5
IOH
@12mA
VCCB@
3V
IOH
@12mA
2.25
IOH
@24mA
2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VCCA(V)
Figure 7. VOHB(min) vs VCCA
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 8. Layout Example
11.3 Power-Up Considerations
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device terminals. To guard against such power-up problems, take these
precautions:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, SCEA021.
16
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Texas Instruments Voltage-Level-Translation Devices, SCEA021
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVCC3245ADBQR
ACTIVE
SSOP
DBQ
24
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ADBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245ADBRE4
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245ADBRG4
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245ADW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ADWE4
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ADWG4
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ADWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ADWRG4
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245ANSR
ACTIVE
SO
NS
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCC3245A
Samples
SN74LVCC3245APW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245APWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245APWRE4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245APWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245APWT
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
SN74LVCC3245APWTG4
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LH245A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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