SN74LVCC4245APWR

SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 FEATURES • • • • • DB, DW, NS, OR PW PACKAGE (TOP VIEW) Bidirectional Voltage Translator 4.5 V to 5.5 V on A Port and 2.7 V to 5.5 V on B Port Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB NC OE B1 B2 B3 B4 B5 B6 B7 B8 GND NC - No internal connection DESCRIPTION/ORDERING INFORMATION This 8-bit (octal) noninverting bus transceiver uses two separate power-supply rails. The A port, VCCA, is dedicated to accepting a 5-V supply level, and the configurable B port, which is designed to track VCCB, accepts voltages from 3 V to 5 V. This allows for translation from a 3.3-V to a 5-V environment and vice versa. The SN74LVCC4245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA. ORDERING INFORMATION PACKAGE (1) TA Reel of 2000 SN74LVCC4245ADWR SOP – NS Reel of 2000 SN74LVCC4245ANSR LVCC4245A SSOP – DB Reel of 2000 SN74LVCC4245ADBR LG245A Tube of 60 SN74LVCC4245APW Reel of 2000 SN74LVCC4245APWR Reel of 250 SN74LVCC4245APWT TSSOP – PW (1) TOP-SIDE MARKING SN74LVCC4245ADW SOIC – DW –40°C to 85°C ORDERABLE PART NUMBER Tube of 25 LVCC4245A LG245A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH TRANSCEIVER) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2005, Texas Instruments Incorporated SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) DIR 2 22 OE A1 3 21 B1 To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCCA VCCB Supply voltage range VI Input voltage range (2) MIN MAX –0.5 6 I/O ports (A port) –0.5 VCCA + 0.5 I/O ports (B port) –0.5 VCCB + 0.5 Except I/O ports –0.5 VCCA + 0.5 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 UNIT V V VO Output voltage range (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCCA, VCCB, or GND θJA Package thermal impedance (3) Tstg Storage temperature range DB package 63 DW package 46 NS package 65 PW package (1) (2) (3) 2 V °C/W 88 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This value is limited to 6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. www.ti.com SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS Recommended Operating Conditions SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 (1) VCCA VCCB MIN NOM MAX UNIT VCCA Supply voltage 4.5 5 5.5 V VCCB Supply voltage 2.7 3.3 5.5 V VIHA High-level input voltage 4.5 V 5.5 V VIHB High-level input voltage 4.5 V 5.5 V VILA Low-level input voltage 4.5 V 5.5 V VILB Low-level input voltage 4.5 V 5.5 V VIH High-level input voltage (control pins) (referenced to VCCA) 4.5 V 5.5 V VIL Low-level input voltage (control pins) (referenced to VCCA) 4.5 V 5.5 V 2.7 V 2 3.6 V 2 5.5 V 2 2.7 V 2 3.6 V 2 5.5 V 3.85 V V 2.7 V 0.8 3.6 V 0.8 5.5 V 0.8 2.7 V 0.8 3.6 V 0.8 5.5 V V V 1.65 2.7 V 2 3.6 V 2 5.5 V 2 V 2.7 V 0.8 3.6 V 0.8 5.5 V 0.8 V VIA Input voltage 0 VCCA V VIB Input voltage 0 VCCB V VOA Output voltage 0 VCCA V VOB Output voltage 0 VCCB V IOHA High-level output current 4.5 V 3V –24 mA IOHB High-level output current 4.5 V 2.7 V to 4.5 V –24 mA IOLA Low-level output current 4.5 V 3V 24 mA IOLB Low-level output current 4.5 V 2.7 V to 4.5 V 24 mA TA Operating free-air temperature 85 °C (1) –40 All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOHA VCCA VCCB MIN TYP IOH = –100 µA TEST CONDITIONS 4.5 V 3V 4.4 4.49 IOH = –24 mA 4.5 V 3V 3.76 4.25 IOH = –100 µA 4.5 V 2.99 IOH = –12 mA 4.5 V VOHB IOH = –24 mA VOLA 4.5 V 3V 2.9 2.7 V 2.2 2.5 3V 2.46 2.85 2.7 V 2.1 2.3 3V 2.25 2.65 4.5 V 3.76 4.25 IOL = 100 µA 4.5 V 3V IOL = 24 mA 4.5 V 3V IOL = 100 µA 4.5 V 3V IOL = 12 mA 4.5 V IOL = 24 mA 4.5 V Control inputs VI = VCCA or GND IOZ (1) A or B ports VO = VCCA/B or GND, ICCA B to A VI = VIL or VIH An = VCC or GND V 0.1 0.44 2.7 V 0.11 0.44 2.7 V 0.22 0.5 3V 0.21 0.44 4.5 V 0.18 0.44 3.6 V ±0.1 ±1 5.5 V ±0.1 ±1 5.5 V 3.6 V ±0.5 ±5 5.5 V Open 8 80 3.6 V 8 80 5.5 V 8 80 3.6 V 5 50 5.5 V 8 80 5.5 V UNIT V 0.21 VOLB II MAX V 0.1 V µA µA µA IO (A port) = 0, Bn = VCCB or GND 5.5 V A to B An = VCCA or GND, IO (B port) = 0 5.5 V A port VI = VCCA – 2.1 V, Other inputs at VCCA or GND, OE at GND and DIR at VCCA 5.5 V 5.5 V 1.35 1.5 OE VI = VCCA – 2.1 V, Other inputs at VCCA or GND, DIR at VCCA or GND 5.5 V 5.5 V 1 1.5 DIR VI = VCCA – 2.1 V, Other inputs at VCCA or GND, OE at VCCA or GND 5.5 V 3.6 V 1 1.5 ∆ICCB (2) B port VI = VCCB – 0.6 V, Other inputs at VCCB or GND, OE at GND and DIR at GND 5.5 V 3.6 V 0.35 0.5 Ci Control inputs VI = VCCA or GND Open Open 5 pF Cio A or B ports VO = VCCA/B or GND 5V 3.3 V 11 pF ICCB ∆ICCA (2) (1) (2) 4 µA mA mA For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated VCC. SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1 through Figure 4) PARAMETER tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPLZ tPHZ tPLZ tPHZ FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B VCCA = 5 V ± 0.5 V, VCCB = 5 V ± 0.5 V VCCA = 5 V ± 0.5 V, VCCB = 2.7 V to 3.6 V MIN MAX MIN MAX 1 7.1 1 7 1 6 1 7 1 6.8 1 6.2 1 6.1 1 5.3 1 9 1 9 1 8.3 1 8 1 8.2 1 10 1 8.1 1 10.2 1 4.7 1 5.2 1 4.9 1 5.2 1 5.4 1 5.4 1 6.3 1 7.4 UNIT ns ns ns ns ns ns Operating Characteristics VCCA = 5 V, VCCB = 3.3 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, f = 10 MHz TYP 20 6.5 UNIT pF Power-Up Considerations (1) TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (VCCA for all four of these devices). 3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. (1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. 5 SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A TO B VCCA = 4.5 V TO 5.5 V AND VCCB = 2.7 V TO 3.6 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL VOH Output 1.5 V tPZL 3V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR A TO B VCCA = 4.5 V TO 5.5 V AND VCCB = 3.6 V TO 5.5 V 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V GND LOAD CIRCUIT tw 3V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL VOH Output 1.5 V tPZL 3V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 7 SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B TO A VCCA = 4.5 V to 5.5 V AND VCCB = 2.7 V TO 3.6 V 2 × VCCA 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCCA GND LOAD CIRCUIT tw 3V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 2 × VCCA (see Note B) tPLZ VCCA 1.5 V tPZH tPHL VOH Output 1.5 V tPZL 3V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS www.ti.com SCAS584M – NOVEMBER 1996 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION FOR B TO A VCCA = 4.5 V TO 5.5 V AND VCCB = 3.6 V TO 5.5 V 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V GND LOAD CIRCUIT tw 3V 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3V 1.5 V tPZH tPHL VOH Output 1.5 V tPZL 3V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LVCC4245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC4245A SN74LVCC4245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC4245A SN74LVCC4245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LVCC4245A SN74LVCC4245ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC4245A SN74LVCC4245ANSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVCC4245A SN74LVCC4245APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245APWT ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A SN74LVCC4245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LG245A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of