SN74LVCH16240ADGGR

SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS566H – MARCH 1996 – REVISED MARCH 2005 FEATURES • • • • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE DESCRIPTION/ORDERING INFORMATION This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C SSOP – DL TSSOP – DGG (1) ORDERABLE PART NUMBER Tube SN74LVCH16240ADL Tape and reel SN74LVCH16240ADLR Tape and reel SN74LVCH16240ADGGR TOP-SIDE MARKING LVCH16240A LVCH16240A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2005, Texas Instruments Incorporated SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS566H – MARCH 1996 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (EACH 4-BIT BUFFER) INPUTS OE A OUTPUT Y L H L L L H H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 2 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com Absolute Maximum Ratings SCAS566H – MARCH 1996 – REVISED MARCH 2005 (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 70 DL package 63 –65 V °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 Low-level input voltage VI Input voltage 1.7 VCC = 2.7 V to 3.6 V 2 Output voltage 0.7 High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V IOH V 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VO V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT V V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 –40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS566H – MARCH 1996 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH 1.65 V to 3.6 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 VI = 0 to 5.5 V ±5 V µA (2) 1.65 V VI = 1.07 V VI = 0.7 V (2) 45 2.3 V VI = 1.7 V VI = 0.8 V µA –45 75 3V VI = 2 V –75 3.6 V ±500 Ioff VI or VO = 5.5 V 0 ±10 µA IOZ VO = 0 to 5.5 V 3.6 V ±10 µA VI = 0 to 3.6 ICC ∆ICC (1) (2) (3) (4) V 3.6 V VI = 0.58 V II(hold) UNIT VCC – 0.2 1.65 V IOL = 24 mA II TYP (1) MAX IOH = –4 mA IOH = –12 mA VOL MIN V (3) VI = VCC or GND IO = 0 3.6 V ≤ VI ≤ 5.5 V (4) 20 3.6 V One input at VCC – 0.6 V, Other inputs at VCC or GND 20 2.7 V to 3.6 V 500 µA µA Ci VI = VCC or GND 3.3 V 5 pF Co VO = VCC or GND 3.3 V 6 pF All typical values are at VCC = 3.3 V, TA = 25°C. This information was not available at the time of publication. This is the bus-hold maximum dynamic current required to switch the input from one state to another. This applies in the disabled state only. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd (1) 4 FROM (INPUT) TO (OUTPUT) A VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX Y (1) (1) (1) (1) (1) (1) (1) ten OE Y (1) tdis OE Y (1) This information was not available at the time of publication. VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN UNIT MAX MIN MAX (1) 5 1 4.2 ns (1) 5.8 1.5 4.7 ns (1) 6.6 1.5 5.9 ns SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS566H – MARCH 1996 – REVISED MARCH 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd (1) Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 34 (1) (1) 3 UNIT pF This information was not available at the time of publication. 5 SN74LVCH16240A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS566H – MARCH 1996 – REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74LVCH16240ADGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH16240A SN74LVCH16240ADL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH16240A SN74LVCH16240ADLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCH16240A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of