SN74LVCH16952ADLR

SN74LVCH16952A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.6 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OEAB 1CLKAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2CLKAB 2OEAB DESCRIPTION/ORDERING INFORMATION This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16952A contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CEAB or CEBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1CLKBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2CLKBA 2OEBA ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74LVCH16952ADL Tape and reel SN74LVCH16952ADLR TSSOP – DGG Tape and reel SN74LVCH16952ADGGR LVCH16952A TVSOP – DGV Tape and reel SN74LVCH16952ADGVR LDH952A SSOP – DL –40°C to 85°C ORDERABLE PART NUMBER Tube LVCH16952A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1993–2005, Texas Instruments Incorporated SN74LVCH16952A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR. FUNCTION TABLE (1) INPUTS (1) (2) 2 CEAB CLKAB OEAB A OUTPUT B H X L X B0 (2) X L L X B0 (2) L ↑ L L L L ↑ L H H X X H X Z A-to-B data flow is shown; B-to-A data flow is similar, but uses CEBA, CLKBA, and OEBA. Level of B before the indicated steady-state input conditions were established SN74LVCH16952A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1CEAB 1CLKAB 1OEBA 1A1 3 54 2 55 56 1 5 One of Eight Channels C1 CE 1D 52 1CEBA 1CLKBA 1OEAB 1B1 C1 CE 1D To Seven Other Channels 2CEAB 2CLKAB 2OEBA 26 31 27 30 29 28 One of Eight Channels 2A1 C1 CE 1D 15 42 2CEBA 2CLKBA 2OEAB 2B1 C1 CE 1D To Seven Other Channels 3 SN74LVCH16952A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) DGG package 64 DGV package 48 DL package 56 Storage temperature range –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 1.5 Low-level input voltage VI VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 1.65 V to 1.95 V VIL UNIT V V V mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 –40 mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74LVCH16952A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS320L – NOVEMBER 1993 – REVISED MARCH 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOL = 24 mA II Control inputs VI = 0 to 5.5 V VI = 0.7 V A or B ports VI = 0.8 V V (2) Ioff VI or VO = 5.5 V IOZ (3) VO = 0 V or (VCC to 5.5 V) VI = VCC or GND, IO = 0 ICC ∆ICC 45 µA –45 75 –75 3.6 V ±500 0 ±10 µA 3.6 V ±10 µA 20 3.6 V 3.6 V ≤ VI ≤ 5.5 V (4), IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND µA 15 3V VI = 2 V V –15 2.3 V VI = 1.7 V VI = 0 to 3.6 ±5 1.65 V VI = 1.07 V UNIT V 3.6 V VI = 0.58 V II(hold) MAX VCC – 0.2 IOH = –4 mA IOH = –12 mA VOL MIN TYP (1) VCC 20 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 5 pF Cio A or B ports 3.3 V 8.5 pF (1) (2) (3) (4) VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current required to switch the input from one state to another. For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI