SN74LVCH8T245PWG4

SN74LVCH8T245 SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs 1 Features 3 Description • The SN74LVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes. • • • • • • Control inputs (DIR and OE) VIH and VIL levels are referenced to VCCA Bus hold on data inputs eliminates the need for external pullup and pulldown resistors VCC isolation Fully configurable dual-rail design Ioff supports Partial-Power-Down node operation Latch-up performance exceeds 100 mA per JESD 78, class II ESD protection exceeds JESD 22 2 Applications • • • • Personal electronics Industrial Enterprise Telecommunications 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels Logic Diagram (Positive Logic) The SN74LVCH8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device. The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA. Package Information(1) PART NUMBER SN74LVCH8T245 (1) PACKAGE BODY SIZE (NOM) DB (SSOP, 24) 8.65 mm × 3.90 mm DGV (TVSOP, 24) 5.00 mm × 4.40 mm PW (TSSOP, 24) 7.80 mm × 4.40 mm RHL (VQFN, 24) 5.50 mm × 3.50 mm For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V.......7 6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V.........8 6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V.........9 6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V..........10 6.10 Operating Characteristics........................................11 6.11 Typical Characteristics.............................................11 7 Parameter Measurement Information.......................... 12 8 Detailed Description......................................................13 8.1 Overview................................................................... 13 8.2 Functional Block Diagram......................................... 13 8.3 Feature Description...................................................13 8.4 Device Functional Modes..........................................14 9 Application and Implementation.................................. 15 9.1 Application Information............................................. 15 9.2 Typical Application.................................................... 15 10 Power Supply Recommendations..............................17 11 Layout........................................................................... 18 11.1 Layout Guidelines................................................... 18 11.2 Layout Example...................................................... 18 12 Device and Documentation Support..........................19 12.1 Documentation Support.......................................... 19 12.2 Receiving Notification of Documentation Updates..19 12.3 Support Resources................................................. 19 12.4 Trademarks............................................................. 19 12.5 Electrostatic Discharge Caution..............................19 12.6 Glossary..................................................................19 13 Mechanical, Packaging, and Orderable Information.................................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2016) to Revision C (December 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated thermals for PW package.....................................................................................................................5 • Removed the Supports High-Speed Translation and added the Balanced High-Drive CMOS Push-Pull Outputs section.................................................................................................................................................13 Changes from Revision A (February 2007) to Revision B (January 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB VCCB OE B1 B2 B3 B4 B5 B6 B7 B8 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND Figure 5-1. DB, DGV, or PW Packages, 24-Pin SSOP, TVSOP, or TSSOP (Top View) VCCB 1 1 24 23 VCCB 22 OE 2 3 21 B1 20 B2 4 5 19 B3 18 B4 6 7 17 B5 16 B6 8 9 15 B7 14 B8 10 11 GND 12 13 GND VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND VCCA 5 Pin Configuration and Functions Figure 5-2. RHL Package, 24-Pin VQFN (Top View) Table 5-1. Pin Functions PIN SSOP, TVSOP, TSSOP VQFN A1 3 3 I/O Input/output A1. Referenced to VCCA. A2 4 4 I/O Input/output A2. Referenced to VCCA. A3 5 5 I/O Input/output A3. Referenced to VCCA. A4 6 6 I/O Input/output A4. Referenced to VCCA. A5 7 7 I/O Input/output A5. Referenced to VCCA. A6 8 8 I/O Input/output A6. Referenced to VCCA. A7 9 9 I/O Input/output A7. Referenced to VCCA. A8 10 10 I/O Input/output A8. Referenced to VCCA. B1 21 21 I/O Input/output B1. Referenced to VCCB. B2 20 20 I/O Input/output B2. Referenced to VCCB. B3 19 19 I/O Input/output B3. Referenced to VCCB. B4 18 18 I/O Input/output B4. Referenced to VCCB. B5 17 17 I/O Input/output B5. Referenced to VCCB. B6 16 16 I/O Input/output B6. Referenced to VCCB. B7 15 15 I/O Input/output B7. Referenced to VCCB. B8 14 14 I/O Input/output B8. Referenced to VCCB. DIR 2 2 I Direction-control signal. Referenced to VCCA. OE 22 22 I 3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA. NAME TYPE(1) DESCRIPTION VCCA 1 1 — A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V VCCB 23, 24 23, 24 — B-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V — Ground GND (1) 11, 12, 13 11, 12, 13 I = input, O = output Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 3 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Supply voltage Input voltage(2) Voltage range applied to any output in the high-impedance or power-off state(2) Voltage range applied to any output in the high or low state(2) (3) MIN MAX UNIT VCCA and VCCB –0.5 6.5 V I/O ports (A port) –0.5 6.5 I/O ports (B port) –0.5 6.5 Control inputs –0.5 6.5 A port –0.5 6.5 B port –0.5 6.5 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 V V V Input clamp current VI < 0 –50 mA Output clamp current VO < 0 –50 mA ±50 mA VCCA, VCCB, and GND ±100 mA Continuous output current, IO Continuous through current Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Machine model (MM) ±200 V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) (2) (3) VCCA VCCB Supply voltage VCCI = 1.65 V to 4.5 V VIH High-level input voltage(1) Data inputs(4) VCCI = 2.3 V to 2.7 V VCCI = 3 V to 3.6 V VCCI = 4.5 V to 5.5 V VCCI = 1.65 V to 4.5 V VIL Low-level input voltage(1) Data inputs(4) MAX 5.5 1.65 5.5 1.7 V V 2 VCCI × 0.7 VCCI × 0.35 0.7 VCCI = 3 V to 3.6 V 0.8 Submit Document Feedback UNIT VCCI × 0.65 VCCI = 2.3 V to 2.7 V VCCI = 4.5 V to 5.5 V 4 MIN 1.65 V VCCI × 0.3 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted)(1) (2) (3) MIN VCCI = 1.65 V to 4.5 V VIH High-level input voltage Control inputs (referenced to VCCA)(5) MAX VCCI = 2.3 V to 2.7 V 1.7 VCCI = 3 V to 3.6 V V 2 VCCI = 4.5 V to 5.5 V VCCA × 0.7 VCCI = 1.65 V to 4.5 V VCCA × 0.35 VCCI = 2.3 V to 2.7 V 0.7 VCCI = 3 V to 3.6 V 0.8 VIL Low-level input voltage Control inputs (referenced to VCCA)(5) VI Input voltage Control inputs(3) 0 5.5 VI/O Input/output voltage(2) Active state 0 VCCO 3-State 0 5.5 VCCI = 4.5 V to 5.5 V IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate Data inputs (1) (2) (3) (4) (5) V VCCA × 0.3 VCCO = 1.65 V to 4.5 V –4 VCCO = 2.3 V to 2.7 V –8 VCCO = 3 V to 3.6 V –24 VCCO = 4.5 V to 5.5 V –32 VCCO = 1.65 V to 4.5 V 4 VCCO = 2.3 V to 2.7 V 8 VCCO = 3 V to 3.6 V 24 VCCO = 4.5 V to 5.5 V 32 VCCI = 1.65 V to 4.5 V 20 VCCI = 2.3 V to 2.7 V 20 VCCI = 3 V to 3.6 V 10 VCCI = 4.5 V to 5.5 V TA UNIT VCCA × 0.65 V V mA mA ns/V 5 Operating free-air temperature –40 85 °C VCCI is the VCC associated with the data input port. VCCO is the VCC associated with the output port. All unused control inputs of the device must be held at VCCA or GND to ensure proper device operation and minimize power consumption. See Implications of Slow or Floating CMOS Inputs, SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL (max) = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL (max) = VCCA × 0.3 V. 6.4 Thermal Information SN74LVCH8T245 THERMAL METRIC(1) DB (SSOP) DGV (TVSOP) PW (TSSOP) RHL (VQFN) 24 PINS 24 PINS 24 PINS 24 PINS UNIT RθJA Junction-to-ambient thermal resistance 88.5 91.1 100.6 37.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.7 23.7 44.7 38.1 °C/W RθJB Junction-to-board thermal resistance 44.1 44.5 55.8 15.2 °C/W ψJT Junction-to-top characterization parameter 12.8 0.6 6.8 0.7 °C/W ψJB Junction-to-board characterization parameter 43.6 44.1 55.4 15.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — — 4.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 5 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.5 Electrical Characteristics All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise noted).(1) (2) PARAMETER TEST CONDITIONS IOH = –100 μA, VI = VIH High-level output voltage(1) VOH Low-level output voltage VOL II Control inputs IBHL (3) IBHH (4) IBHLO (5) IBHHO (6) Ioff Bus-hold low sustaining current Bus-hold high sustaining current Bus-hold low overdrive current Bus-hold high overdrive current Input and output power-off leakage current IOH = –4 mA, VI = VIH VCCA = VCCB = 1.65 V 1.2 VCCA = VCCB = 2.3 V 1.9 IOH = –24 mA, VI = VIH VCCA = VCCB = 3 V 2.4 IOH = –32 mA, VI = VIH VCCA = VCCB = 4.5 V 3.8 IOL = 100 μA, VI = VIL VCCA = VCCB = 1.65 V to 4.5 V IOL = 4 mA, VI = VIL VCCA = VCCB = 1.65 V IOL = 8 mA, VI = VIL VCCA = VCCB = 2.3 V IOL = 24 mA, VI = VIL VCCA = VCCB = 3 V IOL = 32 mA, VI = VIL VCCA = VCCB = 4.5 V VI = VCCA or GND VCCA = VCCB = 1.65 V to 4.5 V VI = 0.58 V VCCA = VCCB = 1.65 V 15 VI = 0.7 V VCCA = VCCB = 2.3 V 45 VI = 0.8 V VCCA = VCCB = 3 V 75 VI = 1.35 V VCCA = VCCB = 4.5 V 100 VI = 1.07 V VCCA = VCCB = 1.65 V –15 VI = 1.7 V VCCA = VCCB = 2.3 V –45 VI = 2 V VCCA = VCCB = 3 V –75 VI = 3.15 V VCCA = VCCB = 4.5 V –100 VCCA = VCCB = 1.95 V 200 VCCA = VCCB = 2.7 V 300 VCCA = VCCB = 3.6 V 500 VCCA = VCCB = 5.5 V 900 VCCA = VCCB = 1.95 V –200 VCCA = VCCB = 2.7 V –300 VCCA = VCCB = 3.6 V –500 VCCA = VCCB = 5.5 V –900 VI = 0 to VCC VI = 0 to VCC VI or VO = 0 to 5.5 V ICCA ICCB Off-state output current Supply current A port Supply current B port Combined supply current 6 VO = VCCO or GND, VI = VCCI or GND OE = X VI = VCCI or GND, IO = 0 VI = VCCI or GND, IO = 0 VI = VCCI or GND, IO = 0 TYP MAX UNIT VCCO = 0.1 IOH = –8 mA, VI = VIH OE = VIH IOZ MIN VCCA = VCCB = 1.65 V to 4.5 V V 0.1 0.45 0.3 V 0.55 0.55 ±0.5 ±2 μA μA μA μA μA VCCA = 0 V, VCCB = 0 to 5.5 V A Port ±0.5 ±2 VCCA = 0 to 5.5 V, VCCB = 0 V B Port ±0.5 ±2 VCCA = VCCB = 1.65 V to 4.5 V A Port, B Port ±2 VCCA = 0 V, VCCB = 5.5 V B Port ±2 VCCA = 5.5 V, VCCB = 0 V A Port ±2 μA VCCA = VCCB = 1.65 V to 4.5 V 20 VCCA = 5 V, VCCB = 0 V 20 VCCA = 0 V, VCCB = 5 V –2 VCCA = VCCB = 1.65 V to 4.5 V 20 VCCA = 5 V, VCCB = 0 V –2 VCCA = 0 V, VCCB = 5 V 20 VCCA = VCCB = 1.65 V to 4.5 V 30 Submit Document Feedback μA μA μA μA Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.5 Electrical Characteristics (continued) All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise noted).(1) (2) PARAMETER TEST CONDITIONS ΔICCA Supply-current change DIR DIR at VCCA - 0.6 V, B port = open, A port at VCCA or GND Ci Input capacitance control inputs VI = VCCA or GND VCCA = VCCB = 3.3 V Cio Input and output capacitance A or B port VO = VCCA/B or GND VCCA = VCCB = 3.3 V (1) (2) (3) (4) (5) (6) VCCA = VCCB = 3 to 5.5 V MIN TYP MAX UNIT 50 μA 4 5 pF 8.5 10 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. The bus-hold circuit can sink at least the minimum low sustaining current at the VIL maximum. IBHL should be measured after lowering VIN to GND and then raising it to VIL maximum. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. 6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH, tPHL tPLH, tPHL tPHZ, tPLZ tPHZ, tPLZ tPZH, tPZL tPZH, tPZL FROM (INPUT) A B OE OE OE OE TO (OUTPUT) B A A B A B TEST CONDITIONS MIN MAX VCCB = 1.8 V ± 0.15 V 1.7 21.9 VCCB = 2.5 V ± 0.2 V 1.3 9.2 VCCB = 3.3 V ± 0.3 V 1 7.4 VCCB = 5 V ± 0.5 V 0.4 7.1 VCCB = 1.8 V ± 0.15 V 0.9 23.8 VCCB = 2.5 V ± 0.2 V 0.8 23.6 VCCB = 3.3 V ± 0.3 V 0.7 23.4 VCCB = 5 V ± 0.5 V 0.7 23.4 VCCB = 1.8 V ± 0.15 V 1.5 29.6 VCCB = 2.5 V ± 0.2 V 1.5 29.4 VCCB = 3.3 V ± 0.3 V 1.5 29.3 VCCB = 5 V ± 0.5 V 1.4 29.2 VCCB = 1.8 V ± 0.15 V 2.4 32.2 VCCB = 2.5 V ± 0.2 V 1.9 13.1 VCCB = 3.3 V ± 0.3 V 1.7 12 VCCB = 5 V ± 0.5 V 1.3 10.3 VCCB = 1.8 V ± 0.15 V 0.4 24 VCCB = 2.5 V ± 0.2 V 0.4 23.8 VCCB = 3.3 V ± 0.3 V 0.4 23.7 VCCB = 5 V ± 0.5 V 0.4 23.7 VCCB = 1.8 V ± 0.15 V 1.8 32 VCCB = 2.5 V ± 0.2 V 1.5 16 VCCB = 3.3 V ± 0.3 V 1.2 12.6 VCCB = 5 V ± 0.5 V 0.9 10.8 UNIT ns ns ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 7 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH, tPHL tPLH, tPHL tPHZ, tPLZ tPHZ, tPLZ tPZH, tPZL tPZH, tPZL FROM (INPUT) A B OE OE OE OE TO (OUTPUT) B A A B A B TEST CONDITIONS MIN MAX VCCB = 1.8 V ± 0.15 V 1.5 21.4 VCCB = 2.5 V ± 0.2 V 1.2 9 VCCB = 3.3 V ± 0.3 V 0.8 6.2 VCCB = 5 V ± 0.5 V 0.6 4.8 VCCB = 1.8 V ± 0.15 V 1.2 9.3 VCCB = 2.5 V ± 0.2 V 1 9.1 VCCB = 3.3 V ± 0.3 V 1 8.9 VCCB = 5 V ± 0.5 V 0.9 8.8 VCCB = 1.8 V ± 0.15 V 1.4 9 VCCB = 2.5 V ± 0.2 V 1.4 9 VCCB = 3.3 V ± 0.3 V 1.4 9 VCCB = 5 V ± 0.5 V 1.4 9 VCCB = 1.8 V ± 0.15 V 2.3 29.6 VCCB = 2.5 V ± 0.2 V 1.8 11 VCCB = 3.3 V ± 0.3 V 1.7 9.3 VCCB = 5 V ± 0.5 V 0.9 6.9 VCCB = 1.8 V ± 0.15 V 1 10.9 VCCB = 2.5 V ± 0.2 V 1 10.9 VCCB = 3.3 V ± 0.3 V 1 10.9 VCCB = 5 V ± 0.5 V 1 10.9 VCCB = 1.8 V ± 0.15 V 1.7 28.2 VCCB = 2.5 V ± 0.2 V 1.5 12.9 VCCB = 3.3 V ± 0.3 V 1.2 9.4 1 6.9 VCCB = 5 V ± 0.5 V 8 Submit Document Feedback UNIT ns ns ns ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 7-1) PARAMETER tPLH, tPHL tPLH, tPHL tPHZ, tPLZ tPHZ, tPLZ tPZH, tPZL tPZH, tPZL FROM (INPUT) A B OE OE OE OE TO (OUTPUT) B A A B A B TEST CONDITIONS MIN MAX VCCB = 1.8 V ± 0.15 V 1.5 21.2 VCCB = 2.5 V ± 0.2 V 1.1 8.8 VCCB = 3.3 V ± 0.3 V 0.8 6.2 VCCB = 5 V ± 0.5 V 0.5 4.4 VCCB = 1.8 V ± 0.15 V 0.8 7.2 VCCB = 2.5 V ± 0.2 V 0.8 6.2 VCCB = 3.3 V ± 0.3 V 0.7 6.1 VCCB = 5 V ± 0.5 V 0.6 6 VCCB = 1.8 V ± 0.15 V 1.6 8.2 VCCB = 2.5 V ± 0.2 V 1.6 8.2 VCCB = 3.3 V ± 0.3 V 1.6 8.2 VCCB = 5 V ± 0.5 V 1.6 8.2 VCCB = 1.8 V ± 0.15 V 2.1 29 VCCB = 2.5 V ± 0.2 V 1.7 10.3 VCCB = 3.3 V ± 0.3 V 1.5 8.6 VCCB = 5 V ± 0.5 V 0.8 6.3 VCCB = 1.8 V ± 0.15 V 0.8 8.1 VCCB = 2.5 V ± 0.2 V 0.8 8.1 VCCB = 3.3 V ± 0.3 V 0.8 8.1 VCCB = 5 V ± 0.5 V 0.8 8.1 VCCB = 1.8 V ± 0.15 V 1.8 27.7 VCCB = 2.5 V ± 0.2 V 1.4 12.4 VCCB = 3.3 V ± 0.3 V 1.1 8.5 VCCB = 5 V ± 0.5 V 0.9 6.4 UNIT ns ns ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 9 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCCB = 1.8 V ± 0.15 V tPLH, tPHL tPLH, tPHL tPHZ, tPLZ A B OE B A A tPZH, tPZL tPZH, tPZL OE OE OE B A B 1.5 21.4 1 8.8 VCCB = 3.3 V ± 0.3 V 0.7 6 VCCB = 5 V ± 0.5 V 0.4 4.2 VCCB = 1.8 V ± 0.15 V 0.7 7 VCCB = 2.5 V ± 0.2 V 0.4 4.8 VCCB = 3.3 V ± 0.3 V 0.3 4.5 VCCB = 5 V ± 0.5 V 0.3 4.3 VCCB = 1.8 V ± 0.15 V 0.3 5.4 VCCB = 2.5 V ± 0.2 V 0.3 5.4 VCCB = 3.3 V ± 0.3 V 0.3 5.4 VCCB = 5 V ± 0.5 V 0.3 5.4 2 28.7 VCCB = 2.5 V ± 0.2 V 1.6 9.7 VCCB = 3.3 V ± 0.3 V 1.4 8 VCCB = 5 V ± 0.5 V 0.7 5.7 VCCB = 1.8 V ± 0.15 V 0.7 6.4 VCCB = 2.5 V ± 0.2 V 0.7 6.4 VCCB = 3.3 V ± 0.3 V 0.7 6.4 VCCB = 5 V ± 0.5 V 0.7 6.4 VCCB = 1.8 V ± 0.15 V 1.5 27.6 VCCB = 2.5 V ± 0.2 V 1.3 11.4 VCCB = 3.3 V ± 0.3 V 1 8.1 0.9 6.5 VCCB = 5 V ± 0.5 V 10 MAX VCCB = 2.5 V ± 0.2 V VCCB = 1.8 V ± 0.15 V tPHZ, tPLZ MIN Submit Document Feedback UNIT ns ns ns ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 6.10 Operating Characteristics TA = 25°C PARAMETER(1) TEST CONDITIONS A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns CpdA (2) B-port input, A-port output CL = 0, f = 10 MHz, tr = tf = 1 ns A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns CpdB (2) B-port input, A-port output (1) (2) CL = 0, f = 10 MHz, tr = tf = 1 ns TYP VCCA = VCCB = 1.8 V 2 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2 VCCA = VCCB = 5 V 3 VCCA = VCCB = 1.8 V 12 VCCA = VCCB = 2.5 V 13 VCCA = VCCB = 3.3 V 13 VCCA = VCCB = 5 V 16 VCCA = VCCB = 1.8 V 13 VCCA = VCCB = 2.5 V 13 VCCA = VCCB = 3.3 V 14 VCCA = VCCB = 5 V 16 VCCA = VCCB = 1.8 V 2 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2 VCCA = VCCB = 5 V 3 UNIT pF pF See CMOS Power Consumption and Cpd Calculation, SCAA035. Power dissipation capacitance per transceiver. 1.4 5.6 1.2 5.4 1.0 5.2 VOH Voltage (V) VOL Voltage (V) 6.11 Typical Characteristics 0.8 0.6 0.4 4.8 4.6 o -40 C o 25 C 0.2 5.0 o -40 C o 25 C 4.4 o o 85 C 85 C 4.2 0 0 20 40 60 80 100 0 -20 IOL Current (mA) -40 -60 -80 -100 IOH Current (mA) Figure 6-1. Voltage vs Current Figure 6-2. Voltage vs Current Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 11 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 7 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 t pd t PLZ/t PZL t PHZ/t PZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kW 2 kW 2 kW 2 kW 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V t PLZ t PZL VCCI Input VCCI/2 VCCI/2 0V t PLH t PHL Output VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL t PHZ t PZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The SN74LVCH8T245 is an 8-bit, dual supply noninverting voltage level translator. Pins A1 through A4, and the control pins (DIR and OE) are referenced to VCCA, while pins B1 through B4 are referenced to VCCB. Both the A port and B port can accept I/O voltages ranging from 1.65 V to 5.5 V. The high on DIR allows data transmission from Port A to Port B, and a low on DIR allows data transmission from Port B to Port A. For more information, see AVC Logic Family Technology and Applications. 8.2 Functional Block Diagram 2 DIR 22 OE 3 A1 21 B1 To Seven Other Channels 8.3 Feature Description 8.3.1 Fully Configurable Dual-Rail Design Both VCCA and VCCB can be supplied at any voltage from 1.65 V to 5.5 V, making the device suitable for translating between any of the voltage nodes: 1.8 V, 2.5 V, 3.3 V, and 5 V. 8.3.2 Partial-Power-Down Mode Operation Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This can occur in applications where subsections of a system are powered down (partial power down) to reduce power consumption. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics. 8.3.3 Active Bus Hold Circuitry Active bus-hold circuitry holds unused or undriven inputs at a valid logic state, which helps with board space savings and reduced component costs. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended as this eliminates the bus-hold feature. 8.3.4 Balanced High-Drive CMOS Push-Pull Outputs A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Two outputs can be connected together for 2X stronger output drive strength. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. 8.3.5 VCC Isolation The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports will be in a high-impedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 13 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74LVCH8T245. Table 8-1. Function Table (Each 8-Bit Section) CONTROL INPUTS(1) OUTPUT CIRCUITS OE (1) 14 DIR A PORT B PORT OPERATION L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os are always active. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LVCH8T245 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum output current can be up to 32 mA when device is powered by 5 V. 9.2 Typical Application 1.8 V 5V 0.1 μF 0.1 μF VCCA 1 μF VCCB DIR OE 1.8-V 5-V SN74LVCH8T245 Controller Data GND System B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 GND Data GND Figure 9-1. Typical Application Circuit Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 15 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 9.2.1 Design Requirements For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters PARAMETERS VALUES Input voltage 1.65 V to 5.5 V Output voltage 1.65 V to 5.5 V 9.2.2 Detailed Design Procedure To begin the design process, determine the following: • Input voltage range – Use the supply voltage of the device that is driving the SN74LVCH8T245 to determine the input voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the value must be less than the VIL of the input port. • Output voltage range – Use the supply voltage of the device that the SN74LVCH8T245 is driving to determine the output voltage range. 9.2.2.1 Enable Times Calculate the enable times for the SN74LVCH8T245 using Equation 1, Equation 2, Equation 3, and Equation 4: tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) (1) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) (2) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) (3) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) (4) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the device initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 9.2.3 Application Curve Voltage (V) Output (5 V) Input (1.8 V) Time (200 ns/div) Figure 9-2. Translation Up (1.8 V to 5 V) at 2.5 MHz 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 10 Power Supply Recommendations The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the OE input is high, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by the current-sinking capability of the driver. VCCA or VCCB can be powered up first. If the SN74LVCH8T245 is powered up in a permanently enabled state (for example OE is always kept low), pullup resistors are recommended at the input. This ensures proper, glitch-free, power-up. For more information, see Designing with SN4LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage Translators/Level-Shifters. In addition, the OE pin may be shorted to GND if the application does not require use of the high-impedance state at any time. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 17 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 11 Layout 11.1 Layout Guidelines To ensure reliability of the device, TI recommends the following common printed-circuit board layout guidelines. • • • Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of signals depending on the system requirements. 11.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane (Inner Layer) VCCB VCCA Bypass Capacitor Bypass Capacitor VCCA 1 VCCA VCCB 16 2 DIR VCCB 15 From Controller 3 A1 OE 14 From Controller 4 A2 B1 13 To System From Controller 5 A3 B2 12 To System From Controller 6 A4 B3 11 To System From Controller 7 A5 B4 10 To System From Controller 8 A6 B5 12 To System From Controller 9 A7 B6 11 To System From Controller 10 A8 B7 10 To System 11 GND B8 10 To System 12 GND GND 13 Keep OE high until VCCA and VCCB are powered up SN74LVCH8T245 Figure 11-1. SN74LVCH8T245 Layout 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 SN74LVCH8T245 www.ti.com SCES637C – AUGUST 2005 – REVISED DECEMBER 2022 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • • • • Texas Instruments, Designing with SN74LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage Translators/Level-Shifters Texas Instruments, Bus-Hold Circuit Texas Instruments, AVC Logic Family Technology and Applications Texas Instruments, CMOS Power Consumption and Cpd Calculation 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LVCH8T245 19 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVCH8T245DBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 Samples SN74LVCH8T245DGVR ACTIVE TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 Samples SN74LVCH8T245PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 Samples SN74LVCH8T245PWE4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 Samples SN74LVCH8T245PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NJ245 Samples SN74LVCH8T245RHLR ACTIVE VQFN RHL 24 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 NJ245 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of