SN74LVCR16245ADLR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 SN74LVCR16245A 16-Bit Bus Transceiver with 3-State Outputs 1 Features 2 Applications • • • • • 1 • • • • • • • • • • Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) All Inputs and Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Servers PCs and Notebooks Network Switches Telecom Infrastructures 3 Description This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCR16245A device is designed for asynchronous communication between data buses. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Device Information(1) PART NUMBER PACKAGE SN74LVCR16245A BODY SIZE (NOM) TSSOP (48) 12.50 mm × 6.1 mm TVSOP (48) 9.70 mm × 4.40 mm SSOP (48) 15.88 mm × 7.49 mm BGA MICROSTAR 7.00 mm × 4.50 mm JUNIOR (56) (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 36 13 1B1 To Seven Other Channels 2OE 2B1 To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 5 5 6 6 7 7 7 8 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 10 Application and Implementation........................ 11 10.1 Application Information.......................................... 11 10.2 Typical Application ............................................... 11 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 Trademarks ........................................................... 13 13.2 Electrostatic Discharge Caution ............................ 13 13.3 Glossary ................................................................ 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 5 Revision History Changes from Revision A (November 2004) to Revision B Page • Updated document to new TI data sheet standards. ............................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Updated Ioff Feature bullet. ..................................................................................................................................................... 1 • Added Applications. ............................................................................................................................................................... 1 • Added Handling Ratings table. ............................................................................................................................................... 5 • Changed MAX ambient temperature to 125°C. ..................................................................................................................... 6 • Added Thermal Information table. .......................................................................................................................................... 6 • Added Typical Characteristics. ............................................................................................................................................... 8 2 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 6 Pin Configuration and Functions DGG, DGV, OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE Pin Functions PIN I/O DESCRIPTION 1DIR I Direction pin 1 1B1 I/O 1B1 input or output 3 1B2 I/O 1B2 input or output 4 GND — Ground pin 5 1B3 I/O 1B3 input or output 6 1B4 I/O 1B4 input or output 7 VCC — Power pin 8 1B5 I/O 1B5 input or output 9 1B6 I/O 1B6 input or output 10 GND — Ground pin 11 1B7 I/O 1B7 input or output 12 1B8 I/O 1B8 input or output 13 2B1 I/O 2B1 input or output 14 2B2 I/O 2B2 input or output 15 GND — Ground pin 16 2B3 I/O 2B3 input or output 17 2B4 I/O 2B4 input or output 18 VCC — Power pin 19 2B5 I/O 2B5 input or output 20 2B6 I/O 2B6 input or output 21 GND — Ground pin NO. NAME 1 2 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A 3 SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION 2B7 I/O 2B7 input or output 2B8 I/O 2B8 input or output 24 2DIR I Direction pin 2 25 2OE I Output Enable 2 26 2A8 I/O 2A8 input or output 27 2A7 I/O 2A7 input or output 28 GND — Ground pin 29 2A6 I/O 2A6 input or output 30 2A5 I/O 2A5 input or output 31 VCC — Power pin 32 2A4 I/O 2A4 input or output 33 2A3 I/O 2A3 input or output 34 GND — Ground pin 35 2A2 I/O 2A2 input or output 36 2A1 I/O 2A1 input or output 37 1A8 I/O 1A8 input or output 38 1A7 I/O 1A7 input or output 39 GND — Ground pin 40 1A6 I/O 1A6 input or output 41 1A5 I/O 1A5 input or output 42 VCC — Power pin 43 1A4 I/O 1A4 input or output 44 1A3 I/O 1A3 input or output 45 GND — Ground pin 46 1A2 I/O 1A2 input or output 47 1A1 I/O 1A1 input or output 48 1OE I NO. NAME 22 23 Output Enable 1 GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 1 2 3 4 5 6 A A 1DIR NC NC NC NC 1OE B B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 1A4 1B6 1B5 VCC GND 1A3 D VCC GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 2A5 J 2B7 2B8 VCC GND 2A6 H VCC GND 2A8 2A7 J K 2DIR NC NC NC NC 2OE C D E F G K 4 Pin Assignments 6 NC − No internal connection Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 7.2 Handling Ratings Tstg V(ESD) (1) (2) MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1500 Storage temperature range Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A 5 SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Operating VCC Supply voltage VIH High-level input voltage Data retention only MIN MAX 1.65 3.6 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V Low-level input voltage VI Input voltage V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V VO Output voltage IOH High-level output current Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –2 VCC = 2.3 V –4 VCC = 2.7 V –8 V V mA –12 VCC = 1.65 V 2 VCC = 2.3 V 4 VCC = 2.7 V 8 VCC = 3 V (1) V 0.8 0 VCC = 3 V IOL V 1.5 VCC = 1.65 V to 1.95 V VIL UNIT mA 12 –40 10 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7.4 Thermal Information THERMAL METRIC (1) DGG DGV DL 48 PINS 48 PINS 48 PINS RθJA Junction-to-ambient thermal resistance 64.3 78.4 68.4 RθJC(top) Junction-to-case (top) thermal resistance 17.6 30.7 34.7 RθJB Junction-to-board thermal resistance 31.5 41.8 41.0 ψJT Junction-to-top characterization parameter 1.1 3.8 12.3 ψJB Junction-to-board characterization parameter 31.2 41.3 40.4 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a (1) 6 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA 1.65 V to 3.6 V IOH = –2 mA II Control inputs MAX 1.2 1.7 2.7 V 2.2 IOH = –6 mA 3V 2.4 IOH = –8 mA 2.7 V 2 IOH = –12 mA 3V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.7 V IOL = 4 mA 2.7 V 0.4 IOL = 6 mA 3V 0.55 IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3V 0.8 VI = 0 to 5.5 V UNIT VCC – 0.2 2.3 V IOL = 2 mA VOL TYP (1) 1.65 V IOH = –4 mA VOH MIN V 3.6 V ±5 µA Ioff VI or VO = 5.5 V 0 ±10 µA IOZ (2) VO = 0 to 5.5 V 3.6 V ±5 µA VI = VCC or GND, ICC 20 3.6 V ≤ VI ≤ 5.5 V (3) IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND ∆ICC 3.6 V 20 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 3 pF Cio A or B ports VO = VCC or GND 3.3 V 12 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (See Figure 3) FROM (INPUT) TO (OUTPUT) tpd A or B ten tdis PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B or A 1 7.8 1 5.8 1.5 5.7 1.5 4.8 ns OE A or B 1.5 10 1 8 1.5 7.9 1.5 6.3 ns OE A or B 1.5 11.9 1 8.4 1.5 8.3 2.2 7.4 ns 7.7 Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS VCC = 1.8 V VCC = 2.7 V VCC = 3.3 V TYP TYP TYP f = 10 MHz 35 38 43 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A UNIT pF 7 SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com 7.8 Typical Characteristics 4.5 8 4 7 TPD in ns 3.5 6 TPD (ns) TPD (ns) 3 2.5 2 5 4 3 1.5 2 1 1 0.5 TPD in ns 0 -100 0 -50 0 50 Temperature (qC) 100 150 0 D001 Figure 1. TPD vs Temperature 8 Submit Documentation Feedback 1 2 VCC (V) 3 4 D002 Figure 2. TPD vs VCC Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 8 Parameter Measurement Information From Output Under Test VLOAD Open S1 RL GND CL (see Note A) RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V VCC VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu th VI VM Input VM VI VM Data Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPHL tPLH VOH VM Output VM VOL tPLH tPHL VOH Output VM VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VI Output Control Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) VM VM 0V tPLZ tPZL VLOAD/2 VM VOL + V∆ VOL tPHZ tPZH VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A 9 SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com 9 Detailed Description 9.1 Overview The SN74LVCR16245A device is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. All inputs and outputs have equivalent 26-Ω resistors that will slow the edges of the output and reduce switching noise caused by long capacitive etch runs or cables. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 9.2 Functional Block Diagram 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 To Seven Other Channels 2B1 To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages. Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description • • • Wide operating voltage range – Operates from 1.65 V to 3.6 V Allows down voltage translation – Inputs accept voltages to 5.5 V Ioff feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table (Each 8-Bit Section) INPUTS 10 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 10 Application and Implementation 10.1 Application Information The SN74LVCR16245A device is a 16-bit bidirectional transceiver. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The device has 5.5V tolerant inputs at any valid VCC which allows it to be used in multi-power systems and can be used for down translation. 10.2 Typical Application Regulated 3.6 V OE VCC DIR A1 B1 uC System Logic uC or System Logic A8 B8 LEDs GND Figure 5. Typical Application Diagram 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads; therefore, routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See (Δt/ΔV) in Recommended Operating Conditions – Specified high and low levels: See (VIH and VIL) in Recommended Operating Conditions – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend Output Conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part – Outputs should not be pulled above VCC Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A 11 SN74LVCR16245A SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves 300 ICC 1.8 V ICC 2.5 V ICC 3.3 V 250 ICC - mA 200 150 100 50 0 0 10 20 30 40 Frequency - MHz 50 60 D004 Figure 6. ICC vs Frequency 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 7. Layout Diagram 12 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A SN74LVCR16245A www.ti.com SCES427B – FEBRUARY 2003 – REVISED JUNE 2014 13 Device and Documentation Support 13.1 Trademarks Widebus is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR16245A 13 PACKAGE OPTION ADDENDUM www.ti.com 20-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74LVCR16245ADGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCR16245A SN74LVCR16245ADGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCR16245A SN74LVCR16245ADGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LDR245A SN74LVCR16245ADLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVCR16245A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of