SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
D
D
D
D
D
D
D
D
D
D
D
D
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
Members of the Texas Instruments
Widebus Family
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Support Live Insertion
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes
PCB Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVT16501 . . . WD PACKAGE
SN74LVT16501 . . . DGG OR DL PACKAGE
(TOP VIEW)
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
description
The ’LVT16501 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high,
the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
description (continued)
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. OE
should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the
current-sourcing capability of the driver.
The SN74LVT16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the input/output (I/O) pin count and functionality of standard small-outline packages in the
same printed circuit board area.
The SN54LVT16501 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16501 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
INPUTS
OEAB
LEAB
CLKAB
A
OUTPUT
B
Z
L
X
X
X
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
L
H
X
H
B0‡
B0§
† A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§ Output level before the indicated steady-state input
conditions were established
H
2
L
L
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SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
logic symbol†
OEAB
CLKAB
LEAB
1
55
2
27
OEBA
CLKBA
LEBA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
30
28
3
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
1
1
4
1
6D
54
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . –0.5 V to 7 V
Current into any output in the low state, IO: SN54LVT16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT16501 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVT16501 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book.
4
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SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
recommended operating conditions (see Note 4)
SN54LVT16501
SN74LVT16501
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
–24
–32
mA
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
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–55
2
125
–40
V
V
V
5
SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = –18 mA
IOH = –100 µA
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
VCC = 3 V
VCC = 2
2.7
7V
VOL
VCC = 3 V
Control pins
VCC = 3.6 V,
VCC = 0 or 3.6 V,
II
A or B ports‡
Ioff
II(hold)
I(h ld)
IOZH
IOZL
ICC
VCC = 3.6 V
VCC = 0,
A or B ports
SN54LVT16501
TYP†
MAX
TEST CONDITIONS
VCC = 3 V
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3
3.6
6V
V,
VI = VCC or GND
MIN
SN74LVT16501
TYP†
MAX
MIN
–1.2
VCC–0.2
2.4
–1.2
VCC–0.2
2.4
V
V
2
IOH = –32 mA
IOL = 100 µA
UNIT
2
0.2
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
V
0.55
IOL = 64 mA
VI = VCC or GND
0.55
±1
±1
VI = 5.5 V
VI = 5.5 V
10
10
120
20
VI = VCC
VI = 0
1
1
–5
–5
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
VO = 3 V
±100
75
75
–75
–75
VO = 0.5 V
Outputs high
IO = 0
0,
Outputs low
∆ICC§
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
1
µA
–1
µA
0.12
5
5
0.12
0.12
0.2
0.2
mA
mA
3.5
pF
Cio
12
12
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused pins at VCC or GND
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
6
3.5
µA
µA
0.12
Outputs disabled
µA
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SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT16501
VCC = 3.3 V
± 0.3 V
fclock
tw
Clock frequency
Pulse duration
tsu
Setup time
th
Hold time
MIN
MAX
0
150
SN74LVT16501
VCC = 2.7 V
MIN
MAX
0
125
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
150
VCC = 2.7 V
MIN
MAX
0
125
LE high
3.3
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
3.3
A before CLKAB↑
1.6
2.1
1.6
2.1
B before CLKBA↑
1.6
2.1
1.6
2.1
A or B before LE↓, CLK high
3.1
2.7
2.6
1.9
A or B before LE↓, CLK low
2.6
2.0
2
1.3
2
2.1
2
2.1
1.3
1.2
0.9
1.2
A or B after CLK↑
A or B after LE↓
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT16501
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
MAX
150
B or A
A or B
LEBA or LEAB
A or B
CLKBA or
CLKAB
A or B
OEBA or OEAB
A or B
OEBA or OEAB
A or B
tPLZ
† All typical values are at VCC = 3.3 V, TA = 25°C.
SN74LVT16501
VCC = 2.7 V
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN TYP†
MAX
150
VCC = 2.7 V
MIN
MAX
125
MHz
1.7
5.4
6.8
1.7
3
5.4
6.8
1.6
6
7.8
1.6
3.2
5.9
7.7
2.3
7.3
9
2.3
4
7
8.5
2.7
8.2
9.8
2.7
4.3
7.9
9.7
2.5
8.3
9.7
2.5
4.1
7.9
9.2
3.5
9.4
10.7
3.5
5.4
8.9
10.4
1.2
5.1
6.1
1.2
3
5
5.9
1.5
5.9
7
1.5
3
5.8
6.9
2.7
7.5
8.5
2.7
4.6
7.4
8.3
2.8
6.8
7.5
2.8
4.7
6.7
7.2
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UNIT
ns
ns
ns
ns
ns
7
SN54LVT16501, SN74LVT16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS147G – MAY 1992 – REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
0V
1.5 V
VOL
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
3V
VOL + 0.3 V
VOL
tPHZ
1.5 V
V
VOH – 0.3 V OH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVT16501DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVT16501
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of