SN74SSTU32866AZKER



     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 D Member of the Texas Instruments D D D D D D D D Checks Parity on DIMM-Independent Data Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the Control and RESET Inputs D D D D Inputs Able to Cascade with a Second SN74SSTU32866A RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except QERR Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only 1 device per DIMM is required to drive 9 SDRAM loads. In the 1:2 pinout configuration, 2 devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output. The SN74SSTU32866A buffer operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The SN74SSTU32866A buffer accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2−D3, D5−D6, D8−D25 when C0 = 0 and C1 = 0; D2−D3, D5−D6, D8−D14 when C0 = 0 and C1=1; or D1−D6, D8−D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state. When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C LFBGA − ZKE Tape and reel SN74SSTU32866AZKER SU866A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright  2005, Texas Instruments Incorporated   !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 description/ordering information (continued) When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers is tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTU32866A. The QERR output of the first SN74SSTU32866A is left floating, and the valid error information is latched on the QERR output of the second SN74SSTU32866A. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, then the QERR output is driven low and latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 must not be switched during normal operation. They must be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32866A ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, then the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle after DCS and CSR go high), then the device gates the QERR output from changing states. If LPS1 is low, then the QERR output functions normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input must be pulled up to VCC through a pullup resistor. The two VREF pins (A3 and T3) are connected together internally by approximately 150 Ω. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin must be terminated with a VREF coupling capacitor. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 ZKE PACKAGE (TOP VIEW) 1 A B C D 2 3 4 5 terminal assignments for 1:1 register (C0 = 0, C1 = 0) 6 1 2 3 4 5 6 A D1 (DCKE) PPO DNU D2 D15 VCC GND Q1 (QCKE) B VREF GND Q2 Q15 VCC GND VCC GND VCC GND C D3 D16 D D4 (DODT) QERR E D5 D17 E F D6 D18 F G PAR_IN RESET G H CLK D7 (DCS) H J CLK CSR Q3 Q16 Q4 (QODT) DNU VCC GND Q5 Q17 Q6 Q18 VCC GND VCC GND C1 C0 Q7 (QCS) DNU VCC GND VCC GND NC NC Q8 Q19 VCC GND VCC GND Q9 Q20 Q10 Q21 VCC GND VCC GND Q11 Q22 Q12 Q23 J K D8 D19 K L D9 D20 L M D10 D21 M N D11 D22 N P D12 D23 R D13 D24 Q24 D14 D25 Q25 P R T T VCC VCC Q13 VREF VCC Q14 Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU − Do not use NC − No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 logic diagram for 1:1 register configuration (positive logic); C0 = 0, C1 = 0 RESET CLK CLK VREF D1 (DCKE) G2 H1 J1 A3, T3 A1 D CLK Q CLK Q CLK Q CLK Q A5 Q1 (QCKE) R D4 (DODT) D1 D D5 Q4 (QODT) R D7 (DCS) H2 D H5 Q7 (QCS) R CSR J2 LPS0 (internal node) D R LPS1 (internal node) One of 22 Channels D2 B1 CE D CLK R To 21 Other Channels (D3, D5, D6, D8−D25) 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q B5 Q2 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 parity logic diagram for 1:1 register configuration (positive logic); C0 = 0, C1 = 0 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2−D3, 22 D5−D6, D8-D25 A3, T3 VREF D D2−D3, D5−D6, D8−D25 CE CLK Q 22 22 R 22 Q2−Q3, Q5−Q6, Q8−Q25 D2−D3, D5−D6, D8−D25 Parity Generator C1 G5 1 0 D Q PPO 1 D CLK D Q CLK R PAR_IN A2 R G1 0 Q CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments for 1:2 register-A (C0 = 0, C1 = 1) 1 2 3 4 5 6 A D1 (DCKE) PPO VREF VCC Q1A (QCKEA) Q1B (QCKEB) B D2 DNU GND GND Q2A Q2B C D3 DNU VCC VCC Q3A Q3B Q4A (QODTA) Q4B (QODTB) Q5A Q5B Q6A Q6B 6 A B C D D E F G H D4 (DODT) QERR GND GND E D5 DNU F D6 DNU VCC GND VCC GND G PAR_IN RESET VCC VCC C1 C0 Q7A (QCSA) Q7B (QCSB) H CLK D7 (DCS) GND GND J K CLK CSR VCC GND NC DNU VCC GND NC D8 Q8A Q8B VCC GND VCC GND Q9A Q9B Q10A Q10B VCC GND VCC GND Q11A Q11B Q12A Q12B VCC VREF VCC VCC Q13A Q13B Q14A Q14B J K L M N P L D9 DNU M D10 DNU N D11 DNU P D12 DNU R R D13 DNU T T D14 DNU Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU − Do not use NC − No internal connection 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 logic diagram for 1:2 register-A configuration (positive logic); C0 = 0, C1 = 1 RESET CLK CLK VREF D1 (DCKE) G2 H1 J1 A3, T3 A1 A5 D CLK Q A6 R D4 (DODT) D1 D5 D CLK D6 H2 H5 D CLK J2 Q4A (QODTA) Q4B (QODTB) Q7A (QCSA) Q R CSR Q1B (QCKEB) Q R D7 (DCS) Q1A (QCKEA) H6 Q7B (QCSB) LPS0 (internal node) D CLK Q R LPS1 (internal node) One of Eleven Channels D2 B1 B5 D CE CLK Q B6 R Q2A Q2B To 10 Other Channels (D3, D5, D6, D8−D14) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 parity logic diagram for 1:2 register-A configuration (positive logic); C0 = 0, C1 = 1 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2−D3, 11 D5−D6, D8-D14 A3, T3 VREF D2−D3, D5−D6, D8−D14 CE D CLK Q 11 11 R 11 11 D2−D3, D5−D6, D8−D14 Q2A−Q3A, Q5A−Q6A, Q8A−Q14A Q2B−Q3B, Q5B−Q6B, Q8B−Q14B Parity Generator C1 G5 1 0 D Q PPO 1 D CLK D Q CLK R PAR_IN A2 R G1 0 Q CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D R 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q CLK 1 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 ZKE PACKAGE (TOP VIEW) 1 A B C D 2 3 4 5 terminal assignments for 1:2 register-B (C0 = 1, C1 = 1) 6 1 2 3 4 5 6 A D1 PPO Q1B D2 DNU VCC GND Q1A B VREF GND Q2A Q2B C D3 DNU QERR VCC GND Q3B D4 VCC GND Q3A D Q4A Q4B E D5 DNU D6 DNU VCC GND Q5B F VCC GND Q5A E Q6A Q6B F G PAR_IN RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) VCC GND VCC GND VCC GND VCC GND G H J CLK CSR K D8 DNU L D9 DNU M D10 DNU N D11 (DODT) DNU VCC P P D12 DNU R R D13 DNU T D14 (DCKE) DNU J K L M N T NC NC Q8A Q8B Q9A Q9B Q10A Q10B VCC Q11A (QODTA) Q11B (QODTB) GND GND Q12A Q12B VCC VCC Q13A Q13B VREF VCC Q14A (QCKEA) Q14B (QCKEB) Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU − Do not use NC − No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 logic diagram for 1:2 register-B configuration (positive logic); C0 = 1, C1 = 1 RESET CLK CLK VREF D14 (DCKE) G2 H1 J1 A3, T3 T1 A5 D CLK Q A6 R D11 (DODT) N1 D5 D CLK D6 H2 H5 D CLK J2 Q11A (QODTA) Q11B (QODTB) Q7A (QCSA) Q R CSR Q14B (QCKEB) Q R D7 (DCS) Q14A (QCKEA) H6 Q7B (QCSB) LPS0 (internal node) D CLK Q LPS1 (internal node) R One of Eleven Channels D1 A1 D A5 CE CLK Q A6 R To 10 Other Channels (D2−D6, D8−D10, D12−D13) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q1A Q1B 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 parity logic diagram for 1:2 register-B configuration (positive logic); C0 = 1, C1 = 1 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D1−D6, D8-D13 VREF 11 A3, T3 D 11 D1−D6, D8−D13 CE Q1A−Q6A, Q8A−Q13A CLK Q 11 R 11 11 D1−D6, D8−D10, D12−D13 Q1B−Q6B, Q8B−Q13B Parity Generator C1 G5 1 0 D Q PPO 1 D CLK D Q CLK R PAR_IN A2 R G1 0 Q CLK R CE D2 QERR C0 G6 CLK 2−Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME ELECTRICAL CHARACTERISTICS DESCRIPTION GND Ground Ground input VCC Power-supply voltage 1.8 V nominal VREF Input reference voltage 0.9 V nominal CLK Positive master clock input Differential input CLK Negative master clock input Differential input C0, C1 Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select. LVCMOS input RESET Asynchronous reset input. Resets registers and disables VREF, data, and clock differential-input receivers. When RESET is low, all Q outputs are forced low and the QERR output is forced high. LVCMOS input D1−D25 Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. SSTL_18 inputs CSR, DCS Chip select inputs. Disables D1−D25† outputs switching when both inputs are high. SSTL_18 inputs DODT The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input DCKE The outputs of this register bit will not be suspended by the DCS and CSR control SSTL_18 input PAR_IN Parity input. Arrives one clock cycle after the corresponding data input. SSTL_18 input Q1−Q25‡ Data outputs that are suspended by the DCS and CSR control 1.8 V CMOS outputs PPO Partial parity out. Indicates odd parity of inputs D1−D25.† 1.8 V CMOS output QCS Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QODT Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QCKE Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QERR Output error bit. Timing is determined by the device mode. Open-drain output NC No internal connection DNU Do not use. Inputs are in standby-equivalent mode, and outputs are driven low. † Data inputs = D2, D3, D5, D6, D8−D25 when C0 = 0 and C1 = 0 Data inputs = D2, D3, D5, D6, D8−D14 when C0 = 0 and C1 = 1 Data inputs = D1−D6, D8−D10, D12, D13 when C0 = 1 and C1 = 1. ‡ Data outputs = Q2, Q3, Q5, Q6, Q8−Q25 when C0 = 0 and C1 = 0 Data outputs = Q2, Q3, Q5, Q6, Q8−Q14 when C0 = 0 and C1 = 1 Data outputs = Q1−Q6, Q8−Q10, Q12, Q13 when C0 = 1 and C1 = 1. FUNCTION TABLES INPUTS 12 OUTPUTS RESET DCS CSR CLK CLK Dn Qn H L X ↑ ↓ L L H L X ↑ ↓ H H H X L ↑ ↓ L L H X L ↑ ↓ H H H H H ↑ ↓ X Q0 H X X L or H L or H X Q0 L X or floating X or floating X or floating X or floating X or floating L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 Function Tables (Continued) INPUTS OUTPUTS RESET CLK CLK DCKE, DCS, DODT QCKE, QCS, QODT H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L PARITY AND STANDBY FUNCTION INPUTS OUTPUTS RESET CLK CLK DCS CSR Σ OF INPUTS = H D1−D25† H ↑ ↓ L X Even L L H H ↑ ↓ L X Odd L H L H ↑ ↓ L X Even H H L H ↑ ↓ L X Odd H L H H ↑ ↓ H L Even L L H H ↑ ↓ H L Odd L H L H ↑ ↓ H L Even H H L H ↑ ↓ H L Odd H L H PPO0 PPO0 QERR0 L H PAR_IN‡ PPO QERR§ H ↑ ↓ H H X X H L or H L or H X X X X L X or floating X or floating X or floating X or floating X X or floating QERR0 † Data inputs = D2−D3, D5−D6, D8−D25 when C0 = 0 and C1 = 0 Data inputs = D2−D3, D5−D6, D8−D14 when C0 = 0 and C1 = 1 Data inputs = D1−D6, D8−D13 when C0 = 1 and C1 = 1 ‡ PAR_IN arrives one clock cycle (C0 = 0) or two clock cycles (C0 = 1) after the data to which it applies. § This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If QERR goes low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, then the QERR output is driven low and latched low for a clock duration equal to the parity duration or until RESET is driven low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 PARITY ERROR DETECT IN LOW-POWER MODE¶ INPUT−DATA ERROR OCCURANCE# 1:1 MODE (C0 = 0, C1 = 0) 1:2 REGISTER-A MODE (C0 = 0, C1 = 1) 1:2 REGISTER-B MODE (C0 = 1, C1 = 1) CASCADED MODE (Registers A and B) PPO DURATION|| QERR DURATION|| PPO DURATION|| QERR DURATION|| PPO DURATION|| QERR DURATION|| PPO DURATION|| QERR DURATION|| n−4 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n−3 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n−2 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n−1 LPM + 2 Cycles LPM + 2 Cycles LPM + 1 Cycle LPM + 1 Cycle LPM + 2 Cycles LPM + 2 Cycles LPM + 2 Cycles LPM + 2 Cycles n Not detected Not detected Not detected Not detected Not detected Not detected Not detected Not detected ¶ If a parity error occurs before the device enters the low-power mode (LPM), then the behavior of PPO and QERR is dependent on the mode of the device and the position of the parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The low-power mode is activated on the n clock cycle when DCS and CSR go high. # The clock-edge position of a one cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inputs. || If an error occurs, then the QERR output may be driven low and the PPO output driven high. These columns show the clock duration for which the PPO signal will be high. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, qJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 2.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN NOM Supply voltage VTT VI Termination voltage VIH VIL AC high-level input voltage Data inputs, CSR, PAR_IN AC low-level input voltage Data inputs, CSR, PAR_IN VIH VIL DC high-level input voltage Data inputs, CSR, PAR_IN DC low-level input voltage Data inputs, CSR, PAR_IN VIH VIL High-level input voltage RESET, Cn Low-level input voltage RESET, Cn VICR VI(PP) Common-mode input voltage range CLK, CLK 0.675 Peak-to-peak input voltage CLK, CLK 600 IOH High-level output current Q outputs, PPO −8 Q outputs, PPO 8 QERR output 8 IOL 1.7 MAX VCC VREF 0.49 × VCC VREF−40 mV 0 Reference voltage Input voltage Low-level output current 1.9 0.5 × VCC VREF 0.51 × VCC VREF + 40 mV VCC VREF + 250 mV UNIT V V V V V VREF−250 mV VREF + 125 mV V V VREF−125 mV 0.65 × VCC V V 0.35 × VCC 1.125 V V mV mA mA TA Operating free-air temperature 0 70 _C NOTE 4: The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ICCD Q outputs, PPO IOH = −100 µA IOH = −6 mA Q outputs, PPO IOL = 100 µA IOL = 6 mA QERR output All inputs‡ QERR output 1.7 V MIN TYP† MAX VCC−0.2 1.3 UNIT V 0.2 1.7 V 0.4 IOL = 8 mA VI = VCC or GND 1.7 V 0.35 1.9 V ±5 µA VO = VCC or GND RESET = GND 1.9 V ±10 µA Static standby Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating − clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating − per each data input, 1:1 configuration Chip-select-enabled low-power active mode − clock only Chip-select-enabled low-power active mode − 1:1 configuration Chip-select-enabled low-power active mode − 1:2 configuration Data inputs, CSR, PAR_IN Ci VCC 1.7 V to 1.9 V 1.7 V to 1.9 V Dynamic operating − per each data input, 1:2 configuration ICCDLP TEST CONDITIONS CLK, CLK RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle IO = 0 1.9 V µA 50 mA µA/ MHz 25 1.8 V µA/ clock MHz/ D input 49 RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle 100 43 IO = 0 µA/ MHz 46 IO = 0 2 1.8 V 2.5 1.8 V VICR = 0.9 V, VI(PP) = 600 mV VI = VCC or GND µA/ clock MHz/ D input 2 VI = VREF ± 250 mV 2 3 V 3.5 3 pF RESET 2.5 † All typical values are at VCC = 1.8 V, TA = 25°C. ‡ Each VREF pin (A3 or T3) must be tested independently, with the other (untested) pin open. Since the two VREF pins are connected internally, the total maximum current on the VREF pin is doubled (±10 µA). 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Note 5) VCC = 1.8 V ± 0.1 V MIN fclock tw Clock frequency tact tinact Differential inputs active time (see Note 6) tsu th Pulse duration, CLK, CLK high or low Setup time MAX UNIT 500 MHz 1 Differential inputs inactive time (see Note 7) DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high 0.6 DCS before CLK↑, CLK↓, CSR low 0.5 DODT, DCKE, and Data before CLK↑, CLK↓ 0.5 PAR_IN before CLK↑, CLK↓ 0.5 DCS, DODT, DCKE, and Data after CLK↑, CLK↓ 0.5 PAR_IN after CLK↑, CLK↓ 0.5 UNIT ns 10 ns 15 ns ns Hold time ns NOTES: 5. All inputs slew rate is 1 V/ns ± 20%. 6. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) TO (OUTPUT) CLK and CLK Q 1.41 2.15 ns see Figure 4 CLK and CLK PPO 0.4 1.7 ns 0.7 2.5 see Figure 3 CLK and CLK QERR 0.7 2.1 CLK and CLK Q 2.35 Q 3 PPO 3 QERR 3 fmax (see Figure 1) tpdm† (see Figure 1) tpd tPLH VCC = 1.8 V ± 0.1 V FROM (INPUT) PARAMETER MIN 500 tPHL tpdmss† (see Figure 1) tRPHL† (see Figure 1) MHz ns RESET ns ns tRPHL (see Figure 4) tRPLH (see Figure 3) UNIT MAX RESET ns † Includes 350-ps test-load transmission-line delay. output slew rates over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM TO VCC = 1.8 V ± 0.1 V MIN MAX UNIT dV/dt_r 20% 80% 1 4 V/ns dV/dt_f 80% 20% 1 4 V/ns 20% or 80% 80% or 20% 1 V/ns dV/dt_∆‡ ‡ Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION VCC ZO = 50 Ω, tD = 350 ps Test Point DUT RL = 1 kΩ CLK RL = 100 Ω Clock Inputs CL = 30 pF (see Note A) ZO = 50 Ω, tD = 350 ps CLK ZO = 50 Ω, tD = 350 ps Output Test Point Out Test Point RL = 1 kΩ LOAD CIRCUIT tw VIH VREF Input VIL VCC LVCMOS RESET Input VCC/2 VCC/2 VOLTAGE WAVEFORMS PULSE DURATION 0V tinact ICC (see Note B) VREF VI(PP) tact 90% 10% ICC (operating) Timing Inputs ICC (standby) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES Output tsu tPHL VOH VCC/2 VOL VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES LVCMOS RESET Input VICR VICR tPLH VI(PP) Timing Inputs VICR VIH VCC/2 VIL tPHL th VOH VIH Input VREF Output VREF VCC/2 VOL VIL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time, with one transition per measurement. E. VREF = VTT = VCC/2 F. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. VIL = VREF − 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. VI(PP) = 600 mV I. tPLH and tPHL are the same as tpd. Figure 1. Data Output Load Circuit and Voltage Waveforms 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION VCC DUT RL = 50 Ω VOH Output Test Point Out 80% CL = 10 pF (see Note A) 20% VOL dV_f dt_f LOAD CIRCUIT HIGH-TO-LOW SLEW-RATE MEASUREMENT VOLTAGE WAVEFORMS HIGH-TO-LOW SLEW-RATE MEASUREMENT DUT dt_r dV_r Test Point Out CL = 10pF (see Note A) 80% RL = 50 Ω Output LOAD CIRCUIT LOW-TO-HIGH SLEW-RATE MEASUREMENT 20% VOH VOL VOLTAGE WAVEFORMS LOW-TO-HIGH SLEW-RATE MEASUREMENT NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified). Figure 2. Data Output Slew-Rate Measurement Information POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION VCC VI(PP) Timing Inputs DUT RL = 1 kΩ VICR tPHL Test Point Out VICR VCC Output Waveform 1 CL = 10 pF (see Note A) VCC/2 VOL VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (HIGH-TO-LOW) LOAD CIRCUIT VI(PP) LVCMOS RESET Input VCC VCC/2 0V Timing Inputs tPLH Output Waveform 2 VICR VICR tPHL VOH 0.15 V 0V VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (LOW-TO-HIGH) VOH Output Waveform 2 0.15 V VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUT TRANSITION TIME (LOW-TO-HIGH) NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). C. tPLH and tPHL are the same as tpd. Figure 3. Error Output Load Circuit and Voltage Waveforms 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0V 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION DUT Test Point Out CL = 5 pF (see Note A) RL = 1 kΩ LOAD CIRCUIT VI(PP) Timing Inputs VICR LVCMOS RESET Input VICR tPLH VIH VCC/2 VIL tPHL tPHL VOH Output VTT VTT VOH Output VTT VOL VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). C. VREF = VTT = VCC/2 D. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. E. VIL = VREF − 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. F. VI(PP) = 600 mV G. tPLH and tPHL are the same as tpd. Figure 4. Partial-Parity-Out Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 APPLICATION INFORMATION SN74SSTU32866A used as a single device in the 1:1 register configuration; C0 = 0, C1 = 0 Register 1 of 1 Dn 22 1D C1 Qn 22 22 22 QERR 1D C1 1D C1 1D C1 C0 = 0 PAR_IN Clock C1 = 0 † This function holds the error for two cycles. For details, see the parity logic diagram. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Latching and Reset Function† PPO 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0 (RESET switches from L to H) RESET ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ DCS CSR n n+1 n+3 n+2 n+4 CLK CLK tsu tact th D1−D25† tpdm, tpdmss CLK to Q Q1−Q25 ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th PAR_IN† tpd CLK to PPO PPO tPHL CLK to QERR QERR‡ tPHL, tPLH CLK to QERR Data to QERR Latency ÎÎÎÎÎ ÎÎÎÎÎ H, L, or X H or L † After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of tact max, to avoid false error. ‡ If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on the n + 3 clock pulse. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0 (RESET = H) RESET DCS CSR ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇ n CLK CLK n+1 tsu D1−D25 n+2 n+3 n+4 th tpdm, tpdmss CLK to Q Q1−Q25 tsu PAR_IN th tpd CLK to PPO PPO Data to PPO Latency QERR† tPHL or tPLH CLK to QERR Data to QERR Latency ÉÉÉ ÉÉÉ Unknown input event ÇÇÇÇ ÇÇÇÇ Output signal is dependent on the prior unknown input event H or L † If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on n + 3 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0 (RESET switches from H to L) RESET tinact DCS† CSR† CLK† CLK† D1−D25† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q25 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO QERR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tRPLH RESET to QERR H, L, or X H or L † After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of tinact max. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 SN74SSTU32866A used in pair in the 1:2 register configuration Register 1 of 2 (1:2 Register-A Configuration); C0 = 0, C1 = 1 Dn 22 11 1D C1 QnA 11 11 11 QnB 11 QERR 1D C1 1D C1 1D C1 C0 = 0 Latching and Reset Function† PPO PAR_IN Clock C1 = 0 Register 2 of 2 (1:2 Register-B Configuration); C0 = 1, C1 = 1 11 1D C1 QnA 11 11 11 QnB 11 QERR 1D C1 1D C1 1D C1 C0 = 1 PAR_IN Clock C1 = 0 † This function holds the error for two cycles. For details, see the parity logic diagram. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Latching and Reset Function† PPO 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair; C0 = 0, C1 = 1 (RESET switches from L to H) RESET ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tsu tact th D1−D14† tpdm, tpdmss CLK to Q Q1−Q14 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th PAR_IN† tpd CLK to PPO PPO tPHL CLK to QERR QERR‡ (not used) ÎÎÎÎÎ ÎÎÎÎÎ tPHL, tPLH CLK to QERR Data to QERR Latency H, L, or X H or L † After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of tact max, to avoid false error. ‡ If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 1 clock pulse, and it will be valid on the n + 2 clock pulse. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair; C0 = 0, C1 = 1 (RESET = H) RESET DCS CSR ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ n CLK CLK tsu D1−D14 n+1 n+2 n+3 n+4 th tpdm, tpdmss CLK to Q Q1−Q14 tsu PAR_IN PPO th tpd CLK to PPO Data to PPO Latency QERR† (not used) tPHL or tPLH CLK to QERR Data to QERR Latency ÇÇÇ ÇÇÇ Unknown input event ÉÉÉÉ ÉÉÉÉ Output signal is dependent on the prior unknown input event H or L † If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 1 clock pulse, and it will be valid on n + 2 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair; C0 = 0, C1 = 1 (RESET switches from H to L) RESET tinact DCS† CSR† CLK† CLK† D1−D14† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q14 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO QERR (not used) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tRPLH RESET to QERR H, L, or X H or L † After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of tinact max. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in pair; C0 = 1, C1 = 1 (RESET switches from L to H) RESET DCS CSR CLK CLK ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tact D1−D14† n n+1 tsu n+3 n+2 n+4 th tpdm, tpdmss CLK to Q Q1−Q14 PAR_IN†‡ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu th tpd CLK to PPO PPO (not used) tPHL CLK to QERR tPHL, tPLH CLK to QERR QERR§ Data to QERR Latency ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ H, L, or X H or L † After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of tact max, to avoid false error. ‡ PAR_IN is driven from PPO of the first SN74SSTU32866A device. § If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on the n + 3 clock pulse. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in pair; C0 = 1, C1 = 1 (RESET = H) RESET ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tsu th ÇÇÇÇÇ ÇÇÇÇÇ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÇÇÇÇ ÌÌÌÌ ÇÇÇÇ ÌÌÌÌ ÇÇÇÇ ÌÌÌÌ D1−D14 tpdm, tpdmss CLK to Q Q1−Q14 tsu th PAR_IN† tpd CLK to PPO PPO (not used) Data to PPO Latency tPHL or tPLH CLK to QERR QERR‡ Data to QERR Latency Unknown input event Output signal is dependent on the prior unknown input event H or L † PAR_IN is driven from PPO of the first SN74SSTU32866A device. ‡ If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on n + 3 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 


     
   

 
 SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007 timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in pair; C0 = 1, C1 = 1 (RESET switches from H to L) RESET tinact DCS† CSR† CLK† CLK† D1−D14† tRPHL RESET to Q ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Q1−Q14 PAR_IN† tRPHL RESET to PPO ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ PPO (not used) QERR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tRPLH RESET to QERR H, L, or X H or L † After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of tinact max. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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