SN74SSTV16857DGVR

Not Recommended for New Designs


    
   

 
 
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 D Member of the Texas Instruments D D D D D D D D DGG PACKAGE (TOP VIEW) Widebus Family Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II Specifications Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 description This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 D1 D2 GND VCC D3 D4 D5 D6 D7 CLK CLK VCC GND VREF RESET D8 D9 D10 D11 D12 VCC GND D13 D14 The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C TSSOP – DGG Tape and reel SN74SSTV16857DGGR SSTV16857 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2002, Texas Instruments Incorporated     !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '! !"# %! &*)' '$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 Not Recommended for New Designs


    
   

 
 
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 FUNCTION TABLE INPUTS RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X, or floating X, or floating X, or floating L logic diagram (positive logic) RESET CLK CLK VREF D1 34 38 39 35 One of 14 Channels 48 1D C1 1 Q1 R To 13 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Not Recommended for New Designs


    
   

 
 
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 4) MIN NOM MAX VCC VDDQ Supply voltage VDDQ 2.3 VREF VTT Reference voltage (VREF = VDDQ/2) VI VIH Input voltage AC high-level input voltage Data inputs VIL VIH AC low-level input voltage Data inputs DC high-level input voltage Data inputs VIL VIH DC low-level input voltage Data inputs High-level input voltage RESET VIL VICR Low-level input voltage RESET Common-mode input voltage range CLK, CLK 0.97 VI(PP) Peak-to-peak input voltage CLK, CLK 360 IOH IOL High-level output current –20 Low-level output current 20 Output supply voltage 1.15 Termination voltage VREF–40mV 0 2.7 V 2.7 V 1.35 V VREF+40mV VCC V 1.25 VREF UNIT VREF+310mV V V VREF–310mV VREF+150mV V V VREF–150mV 1.7 V V 0.7 V 1.53 V mV mA TA Operating free-air temperature 0 70 _C NOTE 4: The RESET input of the device must be held at a valid logic level (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VOH ICC All inputs IOL = 16 mA VI = VCC or GND Static standby RESET = GND MIN TYP† 2.3 V 2.3 V to 2.7 V IOH = –16 mA IOL = 100 µA VOL II VCC AND VDDQ TEST CONDITIONS 2.3 V MAX UNIT –1.2 V VDDQ–0.2 1.95 V 2.3 V to 2.7 V 0.2 2.3 V 0.35 2.7 V IO = 0 27V 2.7 ±5 µA 10 µA Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle rOH Output high IOH = –20 mA 2.3 V to 2.7 V 7 20 Ω rOL Output low IOL = 20 mA 2.3 V to 2.7 V 7 20 Ω rO(∆) rOH – rOL IO = 20 mA, TA = 25°C 6 Ω Data inputs VI = VREF ± 310 mV VICR = 1.25 V, VI(PP) = 360 mV ICCD Ci CLK, CLK IO = 0 56 28 9 µA/ clock MHz/ D input 2.5 V 2.5 V VI = VCC or GND † All typical values are at VCC = 2.5 V, TA = 25°C. • DALLAS, TEXAS 75265 mA µA/ MHz 2.5 V RESET POST OFFICE BOX 655303 8 V 2.5 3 3.5 2.5 3 3.5 2.5 3 3.5 pF F 3 Not Recommended for New Designs


    
   

 
 
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† MIN UNIT MAX fclock tw Clock frequency 200 tact tinact Differential inputs active time (see Note 5) 22 ns Differential inputs inactive time (see Note 6) 22 ns tsu Set p time Setup th Hold time Pulse duration CLK, CLK high or low D t b Data before f CLK↑ CLK↑, CLK↓ ns 0.9 0.75 Fast slew rate (see Notes 7 and 9) Slow slew rate (see Notes 8 and 9) ns 0.75 Fast slew rate (see Notes 7 and 9) Slow slew rate (see Notes 8 and 9) 2.5 MHz D t after Data ft CLK↑ CLK↑, CLK↓ ns 0.9 † For this test condition, VDDQ always is equal to VCC. NOTES: 5. Data inputs must be held low for a minimum time of tact min, after RESET is taken high. 6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low. 7. Data signal input slew rate ≥1 V/ns 8. Data signal input slew rate ≥0.5 V/ns and