Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
D
D
D
D
D
D
Member of the Texas Instruments
Widebus+ Family
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II
Specifications
Differential Clock Inputs (CLK and CLK)
Supports LVCMOS Switching Levels on the
RESET Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D
D
D
Flow-through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32877 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level. When OE and RESET are high, the outputs are in the high-impedance
state.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
D1
GND
Q2
B
D3
Q3
Q4
C
C
D5
D4
VREF
NC
VDDQ
GND
Q1
B
VCC
D2
GND
Q5
Q6
D
D
D7
D6
GND
Q7
Q8
E
E
D9
D8
Q9
F
F
D11
D10
VCC
GND
VDDQ
GND
Q10
VDDQ
GND
G
G
D13
D12
Q12
Q11
H
D15
D14
VCC
GND
VDDQ
VDDQ
GND
GND
Q13
J
CLK
NC
GND
GND
GND
Q14
K
CLK
RESET
D17
VDDQ
VDDQ
Q16
D16
VCC
GND
Q15
L
Q17
GND
M
D18
D19
GND
Q18
N
D20
D21
VCC
GND
Q20
P
D22
D23
NC
VDDQ
GND
VDDQ
Q19
Q22
Q21
R
D24
D25
OE
GND
Q24
Q23
T
D26
VCC
GND
VDDQ
Q26
Q25
H
J
K
L
M
N
P
R
T
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
0°C to 70°C
LFBGA – GKE
Tape and reel
SN74SSTV32877GKER
SV877
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
2
RESET
OE
CLK
CLK
D
OUTPUT
Q
H
L
↑
↓
H
H
H
L
↑
↓
L
L
H
L
L or H
L or H
X
Q0
H
H
X
X
X
Z
L
X or floating
X or floating
X or floating
X or floating
L
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
logic diagram (positive logic)
RESET
CLK
CLK
OE
VREF
D1
K2
J1
K1
R3
B3
A1
1D
C1
A5
Q1
R
To 25 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
recommended operating conditions (see Note 4)
MIN
NOM
VDDQ
2.3
MAX
VCC
VDDQ
Supply voltage
VREF
VTT
Reference voltage (VREF = VDDQ/2)
VI
VIH
Input voltage
AC high-level input voltage
OE, data inputs
VIL
VIH
AC low-level input voltage
OE, data inputs
DC high-level input voltage
OE, data inputs
VIL
VIH
DC low-level input voltage
OE, data inputs
High-level input voltage
RESET
VIL
VICR
Low-level input voltage
RESET
Common-mode input voltage range
CLK, CLK
0.97
VI(PP)
Peak-to-peak input voltage
CLK, CLK
360
IOH
IOL
High-level output current
-20
Low-level output current
20
Output supply voltage
1.15
Termination voltage
VREF–40mV
0
1.25
VREF
UNIT
2.7
V
2.7
V
1.35
V
VREF+40mV
VCC
V
VREF+310mV
V
V
VREF–310mV
VREF+150mV
V
V
VREF–150mV
1.7
V
V
0.7
1.53
V
V
mV
mA
TA
Operating free-air temperature
0
70
_C
NOTE 4: The RESET input of the device must be held at VCC or GND to ensure proper device operation. The differential inputs must not be floating
unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
II = – 18 mA
IOH = – 100 µA
VOH
IOH = – 16 mA
IOL = 100 µA
VOL
All inputs
Static standby
RESET = GND
Static operating
RESET = VCC, VI = VIH(AC) or
VIL(AC)
Dynamic operating –
clock only
RESET = VCC, VI = VIH(AC) or
VIL(AC),
CLK and CLK switching 50%
duty cycle
Dynamic operating –
per each data input
RESET = VCC, VI = VIH(AC) or
VIL(AC),
CLK and CLK switching 50%
duty cycle,
One data input switching at
one-half clock frequency, 50%
duty cycle
IOZ
Outputs
VO = VCC or GND,
rOH
Output high
IOH = –20 mA
rOL
Output low
IOL = 20 mA
rO(∆)
rOH – rOL
IO = 20 mA, TA = 25°C
Data inputs and OE
CLK, CLK
VI = VREF ± 310 mV
VICR = 1.25 V,
RESET
VI = VCC or GND
Outputs
VO = 1.7 V or 0.8 V
II
ICC
ICCD
Ci‡
Co‡
MIN
2.3 V to 2.7 V
VCC–0.2
1.95
2.3 V
IOL = 16 mA
VI = VCC or GND
TYP†
VCC
2.3 V
MAX
UNIT
– 1.2
V
V
2.3 V to 2.7 V
0.2
2.3 V
0.35
2.7 V
IO = 0
2.7 V
IO = 0
±5
µA
40
µA
95
mA
44
µA/
MHz
5
µA/
clock
MHz/
D input
2.5 V
VI (OE) = VCC
V
2.7 V
±10
µA
2.3 V to 2.7 V
7
20
Ω
2.3 V to 2.7 V
7
20
Ω
6
Ω
2.5 V
VI(PP) = 360 mV
2.5
3.3
4
2.5 V
3
3.5
4
3
4
4.5
2.5 V
6.5
7.6
9
pF
pF
† All typical values are at VCC = 2.5 V, TA = 25°C.
‡ Measured with 50-MHz input frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
Obsolete Device
SN74SSTV32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES378B – OCTOBER 2001 – REVISED MAY 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
200
tact
tinact
Differential inputs active time (see Note 5)
22
ns
Differential inputs inactive time (see Note 6)
22
ns
tsu
Setup time
th
Hold time
Pulse duration, CLK, CLK high or low
2.5
Slow slew rate (see Notes 8 and 9)
D t before
Data
b f
CLK↑,
CLK↑ CLK↓
ns
0.9
0.75
Fast slew rate (see Notes 7 and 9)
Data after CLK↑
CLK↑, CLK↓
Slow slew rate (see Notes 8 and 9)
NOTES: 5.
6.
7.
8.
9.
ns
0.75
Fast slew rate (see Notes 7 and 9)
MHz
ns
0.9
Data inputs must be low a minimum time of tact min, after RESET is taken high.
Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact min, after RESET is taken low.
Data signal input slew rate ≥1 V/ns
Data signal input slew rate ≥0.5 V/ns and
