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SN74TVC3306
SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
SN74TVC3306 Dual Voltage Clamp
1 Features
3 Description
•
The SN74TVC3306 device provides three parallel
NMOS pass transistors with a common unbuffered
gate. The low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
1
•
•
•
•
•
Designed to Be Used in Voltage-Limiting
Applications
3.5-Ω On-State Connection Between
Ports A and B
Flow-Through Pinout for Ease of Printed Circuit
Board Trace Routing
Direct Interface With GTL+ Levels
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
•
•
•
The device can be used as a dual switch, with the
gates cascaded together to a reference transistor.
The low-voltage side of each pass transistor is limited
to a voltage set by the reference transistor. This is
done to protect components with inputs that are
sensitive to high-state voltage-level overshoots.
Device Information(1)
PART NUMBER
PACKAGE
SN74TVC3306
BODY SIZE (NOM)
SM8 (8)
3.00 mm x 2.80 mm
US8 (8)
2.30 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Voltage Level Translation
Signal Switching
Bus Isolation
4 Simplified Schematic
GATE
8
1
GND
B1
7
B2
6
B3
5
2
3
4
A1
A2
A3
The SN74TVC3306 device has bidirectional capability across many voltage levels. The voltage levels documented in
this data sheet are examples.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74TVC3306
SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
Absolute Maximum Ratings ....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics (AC, VGATE = 3.3 V,
Translating Down)......................................................
7.7 Switching Characteristics (AC, VGATE = 2.5 V,
Translating Down)......................................................
7.8 Switching Characteristics (AC, VGATE = 3.3 V,
Translating Up) ..........................................................
7.9 Switching Characteristics (AC, VGATE = 2.5 V,
Translating Up) ..........................................................
5
7.10 Typical Characteristics ............................................ 6
8
9
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
7
10 Application and Implementation.......................... 8
10.1 Application Information............................................ 8
10.2 Typical Application ................................................. 8
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 10
5
5
5
13.1 Trademarks ........................................................... 10
13.2 Electrostatic Discharge Caution ............................ 10
13.3 Glossary ................................................................ 10
14 Mechanical, Packaging, and Orderable
Information ........................................................... 10
5 Revision History
Changes from Revision C (March 2002) to Revision D
Page
•
Added Applications, Device Information table, Pin Functions table, Handling Ratings table, Thermal Information
table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed the RON parameter in the Electrical Characersitics table. ....................................................................................... 5
2
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SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
6 Pin Configuration and Functions
Top View
DCT OR DCU PACKAGE
(TOP VIEW)
GND
A1
A2
A3
1
8
2
7
3
6
4
5
GATE
B1
B2
B3
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
A1
2
I/O
I/O of gate 1
A2
3
I/O
I/O of gate 1
A3
4
I/O
I/O of gate 1
B1
5
I/O
I/O of gate 2
B2
6
I/O
I/O of gate 2
B3
7
I/O
I/O of gate 2
GATE
8
I
GND
1
—
Gate pin. Set high to enable the switches. Connect to B1 (VBIAS) for translation application.
Ground
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SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
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7 Specifications
Absolute Maximum Ratings (1)
7.1
over operating free-air temperature range (unless otherwise noted)
Input voltage range (2)
VI
VI/O
Input/output voltage range
(2)
MIN
MAX
–0.5
7
–0.5
Input clamp current
Tstg
Storage temperature range
(1)
(2)
V
7
Continuous channel current
IIK
UNIT
VI < 0
–65
V
128
mA
–50
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2500
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
VI/O
Input/output voltage
0
5
V
VGATE
GATE voltage
0
5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
85
°C
–40
UNIT
7.4 Thermal Information
SN74TVC3306
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
DCT
DCU
8 PINS
8 PINS
220
227
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
MAX
UNIT
VIK
II = -18 mA,
VGATE = 0
–1.2
V
IIH
VI = 5 V,
VGATE = 0
5
μA
Ci(GATE)
VI = 3 V or 0
Cio(off)
VO = 3 V or 0,
VGATE = 0
Cio(on)
VO = 3 V or 0,
VGATE = 3 V
Ron
(1)
(2)
11
pF
4
6
pF
pF
10.5
12.5
VGATE = 4.5 V
3.5
5.5
VGATE = 3 V
4.7
7
VI = 0,
IO = 64 mA
VGATE = 2.3 V
6.3
9.5
VI = 2.4 V,
IO = 15 mA
VGATE = 4.5 V
4.8
7.5
VI = 1.8 V,
IO = 15 mA
VGATE = 4.5 V
4.5
5
(2)
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
7.6 Switching Characteristics (AC, VGATE = 3.3 V, Translating Down)
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V
(unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
0.8
0
0.6
0
0.3
0
1.2
0
1
0
0.5
UNIT
ns
7.7 Switching Characteristics (AC, VGATE = 2.5 V, Translating Down)
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V
(unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
1
0
0.7
0
0.4
0
1.3
0
1
0
0.6
UNIT
ns
7.8 Switching Characteristics (AC, VGATE = 3.3 V, Translating Up)
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V, and
RL = 300 Ω (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
0.9
0
0.6
0
0.4
0
1.4
0
1.1
0
0.7
UNIT
ns
7.9 Switching Characteristics (AC, VGATE = 2.5 V, Translating Up)
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V, and
RL = 300 Ω (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
1
0
0.6
0
0.4
0
1.3
0
1.3
0
0.8
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UNIT
ns
5
SN74TVC3306
SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
www.ti.com
On-resistance (
)
7.10 Typical Characteristics
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-40°C
25°C
85°C
0
±1
1
2
3
4
VIN (V)
C001
Figure 1. RON vs VIN at IIN = 15 mA.
8 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
VIH
Input
VM
VM
VIL
CL
(see Note A)
VOH
Output
VM
VM
LOAD CIRCUIT
VOL
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit for Outputs
6
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SCDS112D – MARCH 2001 – REVISED DECEMBER 2014
9 Detailed Description
9.1 Overview
The SN74TVC3306 device provides three parallel NMOS pass transistors with a common unbuffered gate. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The lowvoltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect
components with inputs that are sensitive to high-state voltage-level overshoots.
9.2 Functional Block Diagram
GATE
8
1
GND
B1
7
B2
6
B3
5
2
3
4
A1
A2
A3
The SN74TVC3306 device has bidirectional capability across many voltage levels. The voltage levels documented in
this data sheet are examples.
9.3 Feature Description
9.3.1 Voltage Clamping
The internal NMOS transistors allow the SN74TVC3306 device to act as a voltage clamp and be configured as a
voltage level translator. See Application and Implementation.
9.4 Device Functional Modes
9.4.1 Voltage Clamping
Whenever the signal on the inputs on the side with VREF goes higher than VREF, the voltage clamps on the
opposite side to the value of VDPU due to the pullup resistors. In this case, the voltage is translating up. See
Application and Implementation.
9.4.2 Voltage Passing
Whenever the signal on the inputs on the VREF side is lower than VREF, the signal will pass to the other side as
intended. In this case, the low pulse is staying low (no translation). See Application and Implementation.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Because of the voltage-clamping mechanism, the SN74TVC3306 device performs best as a level translator for
signals that have sharp edges (as opposed to analog audio signals).
10.2 Typical Application
VDDREF = 5 V
GATE(1)
8
VDPU = 2.5 V
200 kΩ
150 Ω
150 Ω
B1 (VBIAS)(1)
7
B2
6
B3
5
2
A1
3
A2
4
A3
TVC3306
1
VREF(1) = 1.5 V
Open-Drain
CPU Interface
VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS
Figure 3. Typical Application Circuit
8
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Typical Application (continued)
10.2.1 Design Requirements
10.2.1.1 Application Operating Conditions
Application Operating Conditions (See Figure 3)
MIN TYP (1)
VBIAS
BIAS voltage
VREF + 0.6
2.1
VGATE
GATE voltage
VREF + 0.6
VREF
Reference voltage
0
VDPU
Drain pullup voltage
2.36
IPASS
Pass-transistor current
IREF
Reference-transistor current
TA
Operating free-air temperature
(1)
MAX
V
2.1
5
V
1.5
4.4
V
2.5
2.64
V
14
mA
μA
5
–40
UNIT
5
85
°C
All typical values are at TA = 25°C.
10.2.2 Detailed Design Procedure
For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of
the pass transistors, making that the VBIAS connection of the reference transistor and the opposite side (Bn or
An) the VREF connection. When VBIAS is connected through a 200-kΩ resistor to a 3-V to 5.5-V VCC supply and
VREF is set to 0 V to VCC – 0.6 V, the output of each switch has a maximum clamp voltage equal to VREF. A filter
capacitor on VBIAS is recommended.
On-resistance (
)
10.2.3 Application Curves
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-40°C
25°C
85°C
±1
0
1
2
VIN (V)
3
4
C001
Figure 4. On-resistance vs VIN (A to B, 15 mA current)
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11 Power Supply Recommendations
A 200-kΩ resistor is recommended from the input to VCC when the device is being used as a voltage clamp. A
filter capacitor is recommended on B1 as well.
12 Layout
12.1 Layout Guidelines
If used, the filter capacitor should be placed as close to the input of the device as possible.
12.2 Layout Example
SN74TVC3306
GND
GATE
200 k
VREF
A1
B1
A2
B2
A3
B3
VCC
150
150
VDPU
Figure 5. Layout example for voltage-clamp configuration
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74TVC3306DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
FA6
(S, Y)
Samples
SN74TVC3306DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(29O4, FA6P, FA6S)
Samples
SN74TVC3306DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
FA6S
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of