SN75372PSR

  
   SLLS025A − JULY 1986 • • • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range up to 24 V Low Standby Power Dissipation D OR P PACKAGE (TOP VIEW) 1A E 2A GND description The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V. 1 8 2 7 3 6 4 5 VCC1 1Y 2Y VCC2 logic symbol† E 1A The SN75372 is characterized for operation from 0°C to 70°C. 2A 2 1 EN TTL/MOS 3 7 6 1Y 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. schematic (each driver) VCC1 VCC2 To Other Driver Input A Output Y Enable E GND To Other Driver Copyright  1986, Texas Instruments Incorporated Revision Information        !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 3−1 
  
   SLLS025A − JULY 1986 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Peak output current, VO (tw < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE 25°C TA = 25 C POWER RATING DERATING FACTOR ABOVE TA = 25°C 70°C TA = 70 C POWER RATING D 725 mW 5.8 mW/°C 464 mW P 1000 mW 8.0 mW/°C 640 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 4.75 5 5.25 V Supply voltage, VCC2 4.75 20 24 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V High-level output current, IOH −10 mA Low-level output current, IOL 40 mA 70 °C Operating free-air temperature, TA 3−2 0 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
  
   SLLS025A − JULY 1986 electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air temperature (unless otherwise noted) PARAMETER VIK Input clamp voltage VOH High-level output voltage TEST CONDITIONS II = − 12 mA VIL = 0.8 V, MIN IOH = − 50 µA IOH = − 10 mA VIL = 0.8 V, VIH = 2 V, VOL Low-level output voltage VCC2 = 15 V to 24 V, IOL = 40 mA VF Output clamp-diode forward voltage VI = 0, II Input current at maximum input voltage VI = 5.5 V IIH High-level input current IIL Low-level input current ICC1(H) Supply current from VCC1, both outputs high ICC2(H) Supply current from VCC2, both outputs high ICC1(L) Supply current from VCC1, both outputs low ICC2(L) Supply current from VCC2, both outputs low ICC2(S) Supply current from VCC2, standby condition VCC2 −1.3 VCC2 −2.5 TYP† IOL = 10 mA VIH = 2 V, V V 0.15 0.3 0.25 0.5 IF = 20 mA 1.5 1 40 VI = 2.4 V 80 Any A Any E UNIT −1.5 VCC2 −0.8 VCC2 −1.8 Any A Any E MAX VI = 0.4 V VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, No load VCC1 = 5.25 V, All inputs at 5 V, VCC2 = 24 V, No load VCC1 = 0, All inputs at 5 V, VCC2 = 24 V, No load V V mA µA A −1 −1.6 −2 −3.2 2 4 mA 0.5 mA 16 24 mA 7 13 mA 0.5 mA mA † All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDLH tDHL Delay time, low-to-high-level output 20 35 ns Delay time, high-to-low-level output 10 20 ns tTLH tTHL Transition time, low-to-high-level output 20 30 ns 20 30 ns tPLH tPHL Propagation delay time, low-to-high-level output 10 40 65 ns Propagation delay time, high-to-low-level output 10 30 50 ns Transition time, high-to-low-level output CL = 390 pF, • RD = 10 Ω, See Figure 1 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3−3 
  
   SLLS025A − JULY 1986 PARAMETER MEASUREMENT INFORMATION ≤ 10 ns ≤ 10 ns 5V 20 V VCC1 VCC2 3V Input 10% Input 90% 1.5 V 90% 1.5 V tPHL Pulse Generator (see Note A) RD 0V tPHL tDHL Output CL = 390 pF (see Note B) GND 10% 0.5 µs tTLH tTHL 2.4 V VOH VCC2 −3 V tDLH VCC2 −3 V Output 2V 2V VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms, Each Driver TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 0.5 VCC1 = 5 V VCC2 = 20 V VI = 0.8 V VCC2 −0.5 VCC2 −1 VOL VOL − Low-Level Output Voltage − V VV0H OH − High-Level Output Voltage − V VCC2 TA = 25°C TA = 70°C VCC2 −1.5 VCC2 −2 TA = 0°C VCC2 −2.5 VCC2 −3 − 0.01 VCC1 = 5 V VCC2 = 20 V VI = 2 V 0.4 TA = 70°C 0.3 TA = 0°C 0.2 0.1 0 − 0.1 −1 −10 −100 IOH − High-Level Output Current − mA 0 20 60 80 IOL − Low-Level Output Current − mA Figure 2 3−4 40 Figure 3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 100 
  
   SLLS025A − JULY 1986 TYPICAL CHARACTERISTICS POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY VOLTAGE TRANSFER CHARACTERISTICS 1200 24 VV) O − Output Voltage − V 20 P PT D − Power Dissipation − mW VCC1 = 5 V VCC2 = 20 V No Load TA = 25°C 16 12 8 VCC1 = 5 V VCC2 = 20 V Input: 3-V Square Wave 50% Duty Cycle TA = 25°C 1000 800 CL = 600 pF CL = 1000 pF 600 CL = 2000 pF 400 CL = 4000 pF 200 4 CL = 400 pF Allowable in P Package Only 0 0 0 0.5 1 2 1.5 10 2.5 20 40 VI − Input Voltage − V Figure 4 180 180 CL = 4000 pF t PHL − Propagation Delay Time, kSVR High-to-Low-Level Output − ns tkSVR PLH − Propagation Delay Time, Low-to-High-Level Output − ns 200 160 VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 CL = 2000 pF 100 80 CL = 1000 pF 60 CL = 200 pF 40 CL = 390 pF 20 VCC1 = 5 V VCC2 = 20 V RD = 10 Ω See Figure 1 160 1000 CL = 4000 pF 140 120 CL = 2000 pF 100 80 CL = 1000 pF 60 CL = 200 pF 40 CL = 390 pF 20 CL = 50 pF 0 400 PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 200 120 200 Figure 5 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 140 100 f − Frequency − kHz 0 10 20 30 40 50 60 TA − Free-Air Temperature − °C 70 0 80 CL = 50 pF 0 10 20 30 40 50 60 70 80 TA − Free-Air Temperature − °C Figure 6 Figure 7 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3−5 
  
   SLLS025A − JULY 1986 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs VCC2 SUPPLY VOLTAGE 200 200 VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 140 120 CL = 2000 pF 100 80 CL = 1000 pF 60 CL = 200 pF 40 CL = 390 pF High-to-Low-Level Output − ns 160 VCC1 = 5 V RD = 10 Ω TA = 25°C See Figure 1 180 CL = 4000 pF t PLH − Propagation Delay Time, Low-to-High-Level Output − ns t PLH − Propagation Delay Time, 180 20 160 CL = 4000 pF 140 120 CL = 2000 pF 100 80 CL = 1000 pF 60 40 CL = 200 pF 20 CL = 50 pF CL = 50 pF 0 0 0 5 10 15 20 VCC2 − Supply Voltage − V 25 0 5 10 15 20 VCC2 − Supply Voltage − V Figure 8 PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs LOAD CAPACITANCE 200 200 VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 160 140 RD = 24 Ω 120 RD = 10 Ω 100 80 RD = 0 60 VCC1 = 5 V VCC2 = 20 V TA = 25°C See Figure 1 180 t PLH − Propagation Delay Time, kSVR High-to-Low-Level Output − ns t PLH − Propagation Delay Time, kSVR Low-to-High-Level Output − ns 180 40 20 160 140 RD = 24 Ω 120 100 RD = 10 Ω 80 60 RD = 0 40 20 0 0 1000 2000 3000 CL − Load Capacitance − pF 4000 0 Figure 10 1000 2000 3000 CL − Load Capacitance − pF Figure 11 NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating. 3−6 25 Figure 9 PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs LOAD CAPACITANCE 0 CL = 390 pF • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 4000 
  
   SLLS025A − JULY 1986 THERMAL INFORMATION power dissipation precautions Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372 as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the equation PT(AV) = PDC(AV) + PC(AV) = PS(AV) where PDC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between the low and high levels. None of these include energy transferred to the load, and all are averaged over a full cycle. The power components per driver channel are tHL P t + PL t L PDC(AV) = H H T P C(AV) tLH [ C V2 f C PS(AV) = tH PLH t LH + PHL t HL T tL T = 1/f where the times are as defined in Figure 14. Figure 12. Output Voltage Waveform PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance. VC is the voltage across the load capacitance during the charge cycle shown by the equation VC = VOH − VOL PS(AV) may be ignored for power calculations at low frequencies. In the following power calculation, both channels are operating under identical conditions: VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2 is negligible and can be ignored. On a per-channel basis using data sheet values, P DC(AV) ƪ ǒ Ǔ ǒ Ǔƫ (0.6) ) ƪ(5 V) ǒ16 2mAǓ ) (20 V) ǒ7 mA Ǔƫ (0.4) 2 + (5 V) 2 mA ) (20 V) 0 mA 2 2 PDC(AV) = 47 mW per channel Power during the charging time of the load capacitance is PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel Total power for each driver is PT(AV) = 47 mW + 182 mW = 229 mW and total package power is PT(AV) = (229) (2) = 458 mW. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3−7 
  
   SLLS025A − JULY 1986 APPLICATION INFORMATION driving power MOSFETs The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the combination of Ciss and the pullup resistor is shown in Figure 12(b). M 5V 470 Ω 4 7 8 1/2 SN75447 IRF151 3 TLC555P 6 5 2 1 V0H V V OL − Gate Voltage − V OH − VOL 48 V 4 3 2 1 0 0 0.5 1 1.5 Figure 13. Power MOSFET Drive Using SN75447 3−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2.5 t − Time − µs (b) (a) 2 3 
  
   SLLS025A − JULY 1986 APPLICATION INFORMATION A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration, referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b). 48 V M 4 8 7 3 TLC555P IRF151 5 6 2 1/2 SN75372 1 V0H V V OL − Gate Voltage − V OH − VOL 5V 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 t − Time − µs (b) (a) Figure 14. Power MOSFET Drive Using SN75372 Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as shown by the equation I pk + VC tr where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged to. In the circuit shown in Figure 13(a), V is found by the equation V = VOH − VOL Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is I PK + (3 * 0)4(10 *9) 100(10 *9) + 120 mA Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151. With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V. For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad MOSFET driver should be used. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3−9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN75372D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75372 Samples SN75372DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75372 Samples SN75372P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75372P Samples SN75372PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75372P Samples SN75372PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A372 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of