SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
D
D
D
D
D
D
D
D
D
8-Channel Bidirectional Transceiver
High-Speed Advanced Low-Power Schottky
Circuitry
Low Power Dissipation . . . 46 mW Max per
Channel
Fast Propagation Times . . . 20 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis . . . 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (VCC = 0)
Power-Up/Power-Down Protection
(Glitch Free)
DW PACKAGE
(TOP VIEW)
GPIB
I/O
Ports
TE
B1
B2
B3
B4
B5
B6
B7
B8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
D1
D2
D3
D4
D5
D6
D7
D8
PE
Terminal
I/O Ports
NOT RECOMMENDED FOR NEW DESIGNS
description
The SN75ALS163 octal general-purpose interface bus transceiver is a monolithic, high-speed, advanced
low-power Schottky device. It is designed for two-way data communications over single-ended transmission
lines. The transceiver features driver outputs that can be operated in either the open-collector or 3-state mode.
If talk enable (TE) is high, these outputs have the characteristics of open-collector outputs when pullup enable
(PE) is low and of 3-state outputs when PE is high. Taking TE low places the outputs in the high-impedance state.
The driver outputs are designed to handle loads of up to 48 mA of sink current. Each receiver features pnp
transistor inputs for high input impedance and 400 mV minimum of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when VCC = 0.
The SN75ALS163 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
Function Tables
EACH DRIVER
INPUTS
D
TE
PE
OUTPUT
B
H
H
H
H
L
H
X
L
H
X
L
Z
X
L
X
Z
EACH RECEIVER
INPUTS
PE
OUTPUT
D
B
TE
L
L
X
L
H
L
X
H
X
H
X
Z
H = high level, L = low level,
X = irrelevant, Z = high-impedance state
logic symbol†
PE
TE
11
1
logic diagram (positive logic)
PE
M1 [3S]
TE
M2 [0C]
EN3 [XMT]
D1
11
1
19
EN4 [RCV]
D1
19
2
3 (1
4
D2
D3
D4
D5
D6
D7
D8
2
18
1
/2
)
B1
3
3
17
4
16
5
15
6
14
7
13
8
12
D2
9
B2
D3
4
B4
B5
B6
B7
B8
D4
Terminal
I/O
Ports
B6
B7
12
9
POST OFFICE BOX 655303
B5
13
8
D8
GPIB
I/O
Ports
14
7
D7
B4
15
6
D6
B3
16
5
D5
B2
17
B3
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Designates 3-state outputs
Designates open-collector outputs
2
B1
18
• DALLAS, TEXAS 75265
B8
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
VCC
9 kΩ NOM
VCC
10 kΩ
NOM
Req
Input
4 kΩ
NOM
GND
GND
Input/Output Port
Driver output Req = 30 Ω NOM
Receiver output Req = 110 Ω NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High level output current,
High-level
current IOH
Low level output current,
Low-level
current IOL
V
0.8
V
Bus ports with pullups active
– 5.2
mA
Terminal ports
– 800
µA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
mA
°C
3
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
electrical characteristics over recommended supply-voltage and operating free-air temperature
ranges (unless otherwise noted)
PARAMETER
VIK
Vhys
TEST CONDITIONS
Input clamp voltage
Hysteresis (VT+ – VT–)
MIN
II = –18 mA
Bus
TYP†
MAX
UNIT
– 0.8
–1.5
V
0.4
0.65
IOH = – 800 µA,
IOH = – 5.2 mA,
TE at 0.8 V
2.7
3.5
PE and TE at 2 V
2.5
3.3
IOL = 16 mA,
IOL = 48 mA,
TE at 0.8 V
Bus
VO = 5.5 V,
Terminal
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
IOH
High-level output current
(open-collector mode)
Bus
IOZ
Off-state output current
(3-state mode)
Bus
II
Input current at
maximum input voltage
Terminal
VI = 5.5 V
0.2
Terminal,,
PE, or TE
VI = 2.7 V
VI = 0.5 V
IIH
IIL
High-level input current
Low-level input current
IOS
Short-circuit output
current
ICC
Supply
y current
Bus
Terminal
TE at 2 V
0.3
0.5
0.5
100
VO = 2.7 V
VO = 0.5 V
TE at 0.8 V
V
0.35
PE at 0.8 V,
D and TE at 2 V
PE at 2 V,
V
20
–100
0.1
20
µA
–10
–100
µA
– 35
– 75
Bus
– 25
– 50
–125
Terminal outputs low
and enabled
42
65
Bus outputs low and enabled
52
80
VI/O = 0 to 2 V,
30
VCC = 0 to 5 V,
f = 1 MHz
µA
µA
– 15
CI/O(bus) Bus-port capacitance
† All typical values are at VCC = 5 V, TA = 25°C.
µA
100
Terminal
No load
V
mA
mA
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted), VCC = 5 V
PARAMETER
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
Terminal
Bus
CL = 30 pF,
See Figure 1
Bus
Terminal
CL = 30 pF,,
See Figure 2
MIN
TYP†
MAX
7
20
8
20
7
14
9
14
19
30
ns
ns
tPZH
tPHZ
Output enable time to high level
tPZL
tPLZ
Output enable time to low level
tPZH
tPHZ
Output enable time to high level
Output disable time from high level
12
20
tPZL
tPLZ
Output enable time to low level
12
20
11
20
11
22
6
12
Output disable time from high level
Bus
CL = 15 pF,,
See Figure 3
Output disable time from low level
TE
Terminal
CL = 15 pF,,
See Figure 4
Output disable time from low level
ten
Output pull-up enable time
tdis
Output pull-up disable time
† All typical values are at VCC = 5 V, TA = 25°C.
4
TE
PE
POST OFFICE BOX 655303
Bus
CL = 15 pF,
See Figure 5
• DALLAS, TEXAS 75265
UNIT
5
12
16
35
9
20
13
30
ns
ns
ns
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
5V
3V
PE
3V
200 Ω
Output
Generator
(see Note A)
D
B
D Input
1.5 V
1.5 V
50 Ω
480 Ω
CL = 30 pF
(see Note B)
B Output
0V
tPHL
tPLH
VOH
2.2 V
1V
VOL
TE
3V
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
4.3 V
TE
3V
B Input
1.5 V
1.5 V
Output
240 Ω
Generator
(see Note A)
B
D
0V
tPLH
VOH
D Output
50 Ω
tPHL
CL = 30 pF
(see Note B)
3Ω
TEST CIRCUIT
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
5V
3V
200 Ω
PE
Output
3V
TE Input
S2
1.5 V
0V
S1 D
B
CL = 15 pF 480 Ω
(see Note B)
Generator
(see Note A)
1.5 V
tPZH
B Output
S1 to 3 V
S2 Open
90%
VOH
2V
t PZL
B Output
S1 to GND
S2 Closed
TE
tPHZ
0.8 V
tPLZ
1V
3.5 V
0.5 V
VOL
50 Ω
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
4.3 V
TE
Generator
(see Note A)
S2
50 Ω
D
3V
CL = 15 pF
(see Note B)
B
TE Input
1.5 V
3 kΩ
D Output
S1 to 3 V
S2 Open
tPHZ
90%
VOH
1.5 V
tPZL
D Output
S1 to GND
S2 Closed
1.5 V
0V
tPZH
Output
240 Ω
S1
3V
≈0V
tPLZ
4V
1V
0.7 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note A)
50 Ω
PE
3V
PE Input
D
B
1.5 V
0V
Output
tdis
ten
CL = 15 pF
(see Note B)
RL = 480 Ω
1.5 V
90%
B Output
VOH
2V
VOL≈ 0.8 V
3V
TE
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. PE-to-Bus Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
3.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
4
3
2.5
2
1.5
1
0.5
0
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
– 5 – 10 – 15 – 20 – 25 – 30 – 35
IOH – High-Level Output Current – mA
– 40
0
10
20
30
40
50
IOL – Low-Level Output Current – mA
Figure 6
Figure 7
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
VCC = 5 V
No Load
TA = 25°C
VO – Output Voltage – V
3.5
3
2.5
2
VT +
VT –
1.5
1
0.5
0
0
0.2
0.4 0.6 0.8 1 1.2 1.4
VI – Input Voltage – V
1.6
Figure 8
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.8
2
60
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021E – JUNE 1986 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
0.6
4
VOL– Low-Level Output Voltage – V
3
2
1
VCC = 5 V
TA = 25°C
0.5
0.4
0.3
0.2
0.1
0
0
0
– 10
– 20
– 30
– 40
– 50
0
– 60
10
20
30
40
50
60
70
80
90 100
IOL – Low-Level Output Current – mA
IOH – High-Level Output Current – mA
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
4
VCC = 5 V
No Load
TA = 25°C
VO – Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 5 V
TA = 25°C
3
2
1
0
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VI – Input Voltage – V
Figure 11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75ALS163DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS163DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS163DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75ALS163N
OBSOLETE
PDIP
N
20
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75ALS163DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.1
2.65
12.0
24.0
Q1
SN75ALS163DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75ALS163DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN75ALS163DWR
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
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