0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
SN75ALS193NE4

SN75ALS193NE4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    PDIP

  • 描述:

    SN75ALS193 QUADRUPLE DIFFERENTIA

  • 数据手册
  • 价格&库存
SN75ALS193NE4 数据手册
SN75ALS193 SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 SN75ALS193 Quadruple Differential Line Receiver 1 Features • • • • • • • • • • Meets or exceeds ANSI standard EIA/TIA-422B and EIA/TIA-423-A and ITU recommendations V.10 and V.11 Designed for multipoint bus transmission on long bus lines in noisy environments 3-state outputs Common-mode input voltage range: –7 V to 7 V Input sensitivity: ±200 mV Input hysteresis: 120-mV typical High input impedance: 12-kΩ minimum Operates from single 5-V supply Low supply current requirement 35-mA maximum Improved speed and power version of the AM26LS32A 2 Applications • • Motor drives Factory automation and control 3 Description The device is optimized for balanced multipoint bus transmission at rates up to 20 megabits per second. The input features high input impedance, input hysteresis for increased noise immunity, and an input sensitivity of ± 200 mV over a common-mode input voltage range of –7 to 7 V. It also features active-high and active-low enable functions that are common to the four channels. The SN75ALS193 is designed for optimum performance when used with the ’ALS192 quadruple differential line driver. The SN75ALS193 is characterized for operation from 0°C to 70°C. Package Information The SN75ALS193 is a monolithic quadruple line receiver with 3-state outputs designed using advanced low-power Schottky technology. This technology provides combined improvements in bar design, tooling production, and wafer fabrication. This, in turn, provides significantly lower power requirements and permits much higher data Logic Symbol† † throughput than other designs. This device meets the specifications of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-A and ITU Recommendations V.10 and V.11. It features 3-state outputs that permit direct connection to a bus-organized system with a fail-safe design that ensures the outputs will always be high if the inputs are open. PART NUMBER SN75ALS193 (1) (2) PACKAGE(1) PACKAGE SIZE(2) N (PDIP, 16) 19.3 mm × 9.4 mm D (SOIC, 16) 9.9 mm × 6 mm For more information, see Section 10. The package size (length × width) is a nominal value and includes pins, where applicable. Logic Diagram (Positive Logic) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Dissipation Rating....................................................... 4 5.3 Recommended Operating Conditions.........................4 5.4 Thermal Information....................................................4 5.5 Electrical Characteristics.............................................5 5.6 Switching Characteristics............................................5 5.7 Typical Characteristics................................................ 6 2 6 Parameter Measurement Information.......................... 10 7 Detailed Description......................................................12 7.1 Device Functional Modes..........................................12 8 Device and Documentation Support............................13 8.1 Receiving Notification of Documentation Updates....13 8.2 Support Resources................................................... 13 8.3 Trademarks............................................................... 13 8.4 Electrostatic Discharge Caution................................13 8.5 Glossary....................................................................13 9 Revision History............................................................ 13 10 Mechanical, Packaging, and Orderable Information.................................................................... 13 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 4 Pin Configuration and Functions Figure 4-1. D or N Package (Top View) Table 4-1. Pin Functions PIN NAME NO. 1B 1 1A 1Y G 2Y TYPE(1) DESCRIPTION I Channel 1 Differential Receiver Inverting Input 2 I Channel 1 Differential Receiver Non-Inverting Input 3 O Channel 1 Single Ended Output 4 I Active High Enable 5 O Channel 2 Single Ended Output 2A 6 I Channel 2 Differential Receiver Non-Inverting Input 2B 7 I Channel 2 Differential Receiver Inverting Input GND 8 GND 3B 9 I Channel 3 Differential Receiver Inverting Input 3A 10 I Channel 3 Differential Receiver Non-Inverting Input 3Y 11 O Channel 3 Single Ended Output G 12 I Active Low Enable 4Y 13 O Channel 4 Single Ended Output 4A 14 I Channel 4 Differential Receiver Non-Inverting Input 4B 15 I Channel 4 Differential Receiver Inverting Input VCC 16 PWR (1) Device GND Device VCC (4.75V to 5.25V) Signal Types: I = Input, O = Output, I/O = Input or Output. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 3 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN VCC Supply voltage, see (2) VI VID VI Enable input voltage IOL Low-level output current V Input voltage, A or B ±15 V Differential input voltage, see (3) ±15 V 0 Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds (1) (2) (3) 7 V 50 mA 70 °C 300 °C 150 °C See Dissipation Rating table Operating free-air temperature range Tstg UNIT 7 Continuous total dissipation TA MAX Storage temperature range –65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential input voltage, are with respect to network ground terminal. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input. 5.2 Dissipation Rating PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING N 1150 mW 9.2 mW/°C 736 mW 5.3 Recommended Operating Conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V ±7 V ±12 V Common-mode input voltage, VIC Differential input voltage, VID High-level input voltage, VIH 2 V Low-level input voltage, VIL High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 0 0.8 V –400 µA 16 mA 70 °C 5.4 Thermal Information SN75ALS193 THERMAL METRIC(1) D (SOIC) UNIT 16 Pins 16 Pins R θJA Junction-to-ambient thermal resistance 60.6 84.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.1 43.5 °C/W R θJB Junction-to-board thermal resistance 40.6 43.2 °C/W ψ JT Junction-to-top characterization parameter 27.5 10.4 °C/W ψ JB Junction-to-board characterization parameter 40.3 42.8 °C/W (1) 4 N (PDIP) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5.5 Electrical Characteristics over recommended range of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) TEST CONDITIONS(1) PARAMETER VIT+ MIN TYP(2) Positive-going input threshold voltage MAX UNIT 200 mV –200(3) VIT- Negative-going input threshold voltage Vhys Hysteresis voltage (VIT+ -VIT-) VIK Enable-input clamp voltage VCC = MIN, II = –18 mA VOH High-level output voltage VCC = MIN, IOH = – 400 μA, VID = 200 mV, See Figure 1 Low-level output voltage VCC = MIN, VID = – 200 mV, See Figure 1 IOL = 8 mA 0.45 VOL IOL = 16 mA 0.5 IOZ High-impedance-state output current VCC = MAX VO = 2.4 V 20 VO = 0.4 V –20 II Line input current (4) IIH High-level enable-input current VCC = MAX IIL Low-level enable-input current 2.5 V 1.6 V 0.7 1.2 –1.0 –1.7 V μA mA VIH = 2.7 V 20 VIH = MAX 100 VCC = MAX, VIL = 0.4 V –100 μA Input resistance Short-circuit output current VCC = MAX, VO = 0, VID = 3 V, See (5) ICC Supply current VCC = MAX, Outputs disabled (4) (5) mV –1.5 Other input at 0, See VCC = MIN, VI = 15 V VCC = MIN, VI = –15 V IOS (1) (2) (3) mV 120 μA 12 18 –15 –78 –130 mA kΩ 22 35 mA For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25°C. The algebraic convention, in which the less positive limit is designated minimum, is used in this data sheet for threshold voltage levels only. Refer to ANSI Standard EIA/TIA-422-B and EIA/TIA-423-A for exact conditions. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. 5.6 Switching Characteristics VCC = 5 V, TA = 25°C TYP MAX tPLH Propagation delay time, low-to-high-level output VID = –2.5 V to 2.5 V PARAMETER TEST CONDITIONS 15 22 tPHL Propagation delay time, high-to-low-level output CL = 15 pF See Figure 6-1 15 22 13 25 11 25 13 25 15 22 tPZH Output enable time to high level CL =15 pF See Figure 6-2 tPHZ Output disable time from high level CL = 5 pF See Figure 6-2 MIN UNIT ns Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 5 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5.7 Typical Characteristics 6 Figure 5-1. Output Voltage vs Enable Voltage Figure 5-2. Output Voltage vs Enable Voltage Figure 5-3. Output Voltage vs Enable Voltage Figure 5-4. Output Voltage vs Enable Voltage Figure 5-5. Output Voltage vs Differential Input Voltage Figure 5-6. High-level Output Voltage vs Free-air Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5.7 Typical Characteristics (continued) Figure 5-7. High-level Output Voltage vs High-level Output Current Figure 5-8. High-level Output Voltage vs High-level Output Current Figure 5-9. Low-level Output Voltage vs Free-air Temperature Figure 5-10. Low-level Output Voltage vs Low-level Output Current Figure 5-11. Low-level Output Voltage vs Low-level Output Current Figure 5-12. Supply Current vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 7 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5.7 Typical Characteristics (continued) Figure 5-13. Supply Current vs Free-air Temperature Figure 5-15. Supply Current vs Frequency Figure 5-17. Input Current vs Input Voltage to GND 8 Figure 5-14. Supply Current vs Differential Input Voltage Figure 5-16. Input Resistance vs Free-air Temperature Figure 5-18. Switching Time vs Free-air Temperature Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 5.7 Typical Characteristics (continued) Figure 5-19. Propagation Delay Time vs Supply Voltage Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 9 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 6 Parameter Measurement Information Figure 6-1. VOH, VOL A. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. CL includes probe and jig capacitance. Figure 6-2. Test Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com A. B. C. SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 CL includes probe and jig capacitance. All diodes are 1N3064 or equivalent. Enable G is tested with G high; G is tested with G low. Figure 6-3. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 11 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 7 Detailed Description 7.1 Device Functional Modes Table 7-1. Function Table (Each Receiver) DIFFERENTIAL INPUTS A – B(1) VID ≥ 0.2 V –0.2 VID < VID < 0.2 V VID ≤ –0.2 V X Open (1) ENABLES OUTPUT Y G G H X H X L H H X ? X L ? H X L X L L L H Z H X H X L H H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impedance (off) Figure 7-1. Schematics of Inputs and Outputs 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 SN75ALS193 www.ti.com SLLS008E – JUNE 1986 – REVISED OCTOBER 2023 8 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 8.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 9 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (May 1995) to Revision E (October 2023) Page • Changed the numbering format for tables, figures, and cross-references throughout the document................ 1 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN75ALS193 13 PACKAGE OPTION ADDENDUM www.ti.com 12-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN75ALS193D LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS193 SN75ALS193DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75ALS193 Samples SN75ALS193N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75ALS193N Samples SN75ALS193NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75ALS193N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN75ALS193NE4 价格&库存

很抱歉,暂时无法提供与“SN75ALS193NE4”相匹配的价格&库存,您可以联系我们找货

免费人工找货