SN75C1154DWG4

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 D D D D D D D SN65C1154 . . . N PACKAGE SN75C1154 . . . DW, N, OR NS PACKAGE (TOP VIEW) Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption . . . 5 mW Typ Wide Driver Supply Voltage . . . ±4.5 V to ±15 V Driver Output Slew Rate Limited to 30 V/µs Max Receiver Input Hysteresis . . . 1000 mV Typ Push-Pull Receiver Outputs On-Chip Receiver 1-µs Noise Filter VDD 1RA 1DY 2RA 2DY 3RA 3DY 4RA 4DY VSS 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1RY 1DA 2RY 2DA 3RY 3DA 4RY 4DA GND description/ordering information The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154 and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need for external components. The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. ORDERING INFORMATION –40°C to 85°C 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING PDIP (N) Tube of 20 SN65C1154N SN65C1154N PDIP (N) Tube of 20 SN75C1154N SN75C1154N Tube of 25 SN75C1154DW Reel of 2500 SN75C1154DWR SOIC (DW) SN75C1154 SOP (NS) Reel of 2000 SN75C1154NSR SN75C1154 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 logic diagram (positive logic) Typical of Each Receiver RA 2, 4, 6, 8 19, 17, 15, 13 RY Typical of Each Driver DY 2 3, 5, 7, 9 POST OFFICE BOX 655303 18, 16, 14, 12 • DALLAS, TEXAS 75265 DA SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 schematics of inputs and outputs EQUIVALENT DRIVER INPUT VDD EQUIVALENT DRIVER OUTPUT VDD Internal 1.4-V Reference Input DA 160 Ω VSS Output DY 74 Ω GND 72 Ω VSS Input RA EQUIVALENT RECEIVER INPUT 3.4 kΩ EQUIVALENT RECEIVER OUTPUT VCC 1.5 kΩ ESD Protection ESD Protection Output RY 530 Ω GND GND Resistor values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage: VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V Output voltage range, VO:Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSS – 6 V) to (VDD + 6 V) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V) Package thermal impedance, θJA (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage s are with respect to the network GND terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions 4 MIN NOM MAX VDD VSS Supply voltage 4.5 12 15 V Supply voltage –4.5 –12 –15 V VCC Supply voltage 4.5 5 6 V VDD ±25 V Driver VSS + 2 UNIT VI Input voltage VIH VIL High-level input voltage Driver Low-level input voltage Driver 0.8 V IOH IOL High-level output current Receiver –1 mA High-level output current Receiver 3.2 mA TA Operating O erating free-air tem temperature erature Receiver POST OFFICE BOX 655303 2 V SN65C1154 –40 85 SN75C1154 0 70 • DALLAS, TEXAS 75265 °C SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 DRIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10% (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5 V, VDD = 12 V, VSS = –5 V VSS = –12 V VDD = 5 V, VDD = 12 V, VSS = –5 V VSS = –12 V TYP† 4 4.5 10 10.8 MAX UNIT VOH High level output voltage High-level VIL = 0.8 V,, See Figure 1 VOL Low-level output voltage g (see Note 4) VIH = 2 V,, See Figure 1 RL = 3 kΩ,, High-level input current See Figure 2 1 µA Low-level input current VI = 5 V, VI = 0, See Figure 2 –1 µA IOS(H) High-level g short-circuit output current‡ VI = 0 0.8 8V V, VO = 0 or VSS, See Figure 1 –7.5 75 –12 12 –19.5 19 5 mA IOS(L) Low-level short-circuit output current‡ VI = 2 V V, VO = 0 or VDD, See Figure 1 75 7.5 12 19 5 19.5 mA IDD Supply current from VDD No load, All inputs at 2 V or 0.8 V VDD = 5 V, VDD = 12 V, VSS = –5 V VSS = –12 V 115 250 115 250 ISS Supply current from VSS No load, All inputs at 2 V or 0.8 V VDD = 5 V, VDD = 12 V, VSS = –5 V VSS = –12 V –115 –250 –115 –250 IIH IIL RL = 3 kΩ,, MIN V –4.4 –4 –10.7 –10 V µA µA ro Output resistance VDD = VSS = VCC = 0, VO = –2 V to 2 V, See Note 5 300 400 Ω † All typical values are at TA = 25°C. ‡ Not more than one output should be shorted at one time. NOTES: 4. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 5. Test conditions are those specified by TIA/EIA-232-F. switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10%, TA = 25°C (see Figure 3) TYP MAX tPLH tPHL Propagation delay time, low- to high-level output§ Propagation delay time, high- to low-level output§ PARAMETER RL = 3 to 7 kΩ, TEST CONDITIONS CL = 15 pF MIN 1.2 3 µs RL = 3 to 7 kΩ, CL = 15 pF 2.5 3.5 µs tTLH tTHL Transition time, low- to high-level output¶ Transition time, high- to low-level output¶ RL = 3 to 7 kΩ, CL = 15 pF 0.53 2 3.2 µs RL = 3 to 7 kΩ, CL = 15 pF 0.53 2 3.2 µs tTLH tTHL Transition time, low- to high-level output# Transition time, high- to low-level output# RL = 3 to 7 kΩ, CL = 2500 pF 1 2 µs RL = 3 to 7 kΩ, CL = 2500 pF 1 2 µs SR Output slew rate RL = 3 to 7 kΩ, CL = 15 pF 10 30 V/µs 4 UNIT § tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points. ¶ Measured between 10% and 90% points of output waveform # Measured between 3 V and –3 V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 RECEIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT VIT IT+ Positive-going g g input threshold voltage See Figure 5 17 1.7 21 2.1 2 55 2.55 V VIT IT– Negative-going g g g input threshold voltage See Figure 5 0 65 0.65 1 1 25 1.25 V Vhys Input hysteresis voltage (VIT+ – VIT–) 600 1000 VI = 0.75 V, VOH High level output voltage High-level VI = 0 0.75 75 V V, See Figure 5 VOL Low-level output voltage VI = 3 V, VI = 25 V IOH = –20 µA, IOH = –1 1 mA, A IOL = 3.2 mA, See Figure 5 and Note 6 3.5 VCC = 4.5 V VCC = 5 V 2.8 4.4 3.8 4.9 VCC = 5.5 V See Figure 5 4.3 mV V 5.4 0.17 0.4 3.6 4.6 8.3 VI = 3 V VI = –25 V 0.43 0.55 1 –3.6 –5 –8.3 VI = –3 V –0.43 –0.55 –1 V IIH High level input current High-level IIL Low level input current Low-level IOS(H) Short-circuit output at high level 75 V VI = 0 0.75 V, VO = 0 0, See Figure 4 8 –8 15 –15 mA IOS(L) Short-circuit output at low level VI = VCC, VO = VCC, See Figure 4 13 25 mA ICC Supply current from VCC No load, All inputs at 0 or 5 V 400 600 400 600 VDD = 5 V, VDD = 12 V, VSS = –5 V VSS = –12 V mA mA µA † All typical values are at TA = 25°C. NOTE 6: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state. switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C PARAMETER TEST CONDITIONS TYP MAX See Figure 6 3 4 µs RL = 5 kΩ, See Figure 6 3 4 µs CL = 50 pF, RL = 5 kΩ, See Figure 6 300 450 ns Transition time, high- to low-level output CL = 50 pF, RL = 5 kΩ, See Figure 6 100 300 ns Duration of longest pulse rejected as noise‡ CL = 50 pF, RL = 5 kΩ 4 µs tPLH Propagation delay time, low- to high-level output CL = 50 pF, RL = 5 kΩ, tPHL Propagation delay time, high- to low-level output CL = 50 pF, Transition time, low- to high-level output tTLH tTHL tw(N) MIN 1 UNIT ‡ The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION IOSL VDD VCC VDD VCC VDD or GND –IOSH IIH VSS or GND VI VI –IIL RL = 3 kΩ VO VI VSS VSS Figure 1. Driver Test Circuit (VOH, VOL, IOSL, IOSH) Figure 2. Driver Test Circuit (IIL, IIH) 3V VDD Input VCC Input 1.5 1.5 0V Pulse Generator (see Note A) tPHL CL (see Note B) RL tPLH 50% 10% 50% 10% Output tTHL VSS VOH 90% 90% tTLH VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms VDD VCC VI –IOS(H) VDD VCC IOS(L) VIT, VI VCC VOH VOL VSS –IOH IOL VSS Figure 4. Receiver Test Circuit (IOSH, IOSL) POST OFFICE BOX 655303 Figure 5. Receiver Test Circuit (VIT, VOL, VOH) • DALLAS, TEXAS 75265 7 SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151D – DECEMBER 1988 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION 4V VDD Input Input VCC 50% 50% 0V Pulse Generator (see Note A) tPHL RL CL (see Note B) tPLH 90% 90% 50% 10% Output 50% 10% tTHL VSS tTLH VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VOH VOL PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65C1154N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 85 SN65C1154N Samples SN75C1154DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1154 Samples SN75C1154DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1154 Samples SN75C1154N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN75C1154N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of