SN75C1406DWRE4

SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 D D D D D D D D D Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption . . . 5 mW Typ Wide Driver Supply Voltage Range . . . ±4.5 V to ±15 V Driver Output Slew Rate Limited to 30 V/µs Max Receiver Input Hysteresis . . . 1000 mV Typ Push-Pull Receiver Outputs On-Chip Receiver 1-µs Noise Filter Functionally Interchangeable With Motorola MC145406 and Texas Instruments TL145406 Package Options Include Plastic Small-Outline (D, DW, NS) Packages and DIPs (N) SN65C1406 . . . D PACKAGE SN75C1406 . . . D, DW, N, OR NS PACKAGE (TOP VIEW) VDD 1RA 1DY 2RA 2DY 3RA 3DY VSS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1RY 1DA 2RY 2DA 3RY 3DA GND description The SN65C1406 and SN75C1406 are low-power BiMOS devices containing three independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1406 and SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the receivers have filters that reject input noise pulses shorter than 1 µs. Both these features eliminate the need for external components. The SN65C1406 and SN75C1406 are designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1406 and SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. The SN65C1406 is characterized for operation from –40°C to 85°C. The SN75C1406 is characterized for operation from 0°C to 70°C. AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (D) SMALL OUTLINE (DW) PLASTIC DIP (N) PLASTIC SMALL OUTLINE (NS) –40°C to 85°C SN65C1406D — — — 0°C to 70°C SN75C1406D SN75C1406DW SN75C1406N SN75C1406NS The D, DW, and PW packages are available taped and reeled. Add the suffix R to device type (e.g., SN75C1406DR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 logic diagram (positive logic) Typical of Each Receiver RA 2, 4, 6 15, 13, 11 RY Typical of Each Driver DY 2 3, 5, 7 POST OFFICE BOX 655303 14, 12, 10 DA • DALLAS, TEXAS 75265 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 schematics of inputs and outputs EQUIVALENT DRIVER INPUT EQUIVALENT DRIVER OUTPUT VDD VDD Internal 1.4-V Reference Input DA 160 Ω Output DY 74 Ω VSS GND 72 Ω VSS EQUIVALENT RECEIVER INPUT EQUIVALENT RECEIVER OUTPUT VCC 3.4 kΩ Input RA Output RY 1.5 kΩ ESD Protection ESD Protection 530 Ω GND GND All resistor values shown are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage: VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V Output voltage range, VO: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSS – 6 V) to (VDD + 6 V) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V) Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to the network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN NOM MAX VDD VSS Supply voltage 4.5 12 15 V Supply voltage –4.5 –12 –15 V VCC Supply voltage 4.5 5 6 V VDD ± 25 V VI Input voltage VIH VIL High-level input voltage IOH IOL TA 4 Driver VSS+ 2 Receiver 2 Low-level input voltage UNIT V 0.8 V High-level output current –1 mA Low-level output curren 3.2 mA Operating free free-air air temperature POST OFFICE BOX 655303 SN65C1406 –40 85 SN75C1406 0 70 • DALLAS, TEXAS 75265 °C SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 DRIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High level output voltage High-level VIH = 0.8 V,, See Figure 1 RL = 3 kΩ, VOL Low-level output voltage g (see Note 3) VIH = 2 V,, See Figure 1 RL = 3 kΩ, High-level input current See Figure 2 1 µA Low-level input current VI = 5 V, VI = 0, See Figure 2 –1 µA IOS(H) High-level short-circuit output current‡ VI = 0.8 V, VO = 0 or VSS, See Figure 1 –7.5 –12 –19.5 mA IOS(L) Low-level short-circuit output current‡ VI = 2 V, VO = 0 or VDD, See Figure 1 7.5 12 19.5 mA IDD Supply current from VDD No load,, All inputs at 2 V or 0.8 V VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V 115 250 115 250 ISS Supply current from VSS No load,, All inputs at 2 V or 0.8 V VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V –115 –250 –115 –250 rO Output resistance VDD = VSS = VCC = 0, See Note 4 VO = – 2 V to 2 V, IIH IIL VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V 4 4.5 10 10.8 V –4.4 –4 –10.7 –10 300 V µA µA Ω 400 † All typical values are at TA = 25°C. ‡ Not more than one output should be shorted at a time. NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 4. Test conditions are those specified by TIA/EIA-232-F. switching characteristics at TA = 25°C, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10% PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 3 µs 2.5 3.5 µs tPLH Propagation delay time, low- to high-level output§ RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 tPHL Propagation delay time, high- to low-level output§ RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 tTLH Transition time, low- to high-level output¶ RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 0.53 2 3.2 µs tTHL Transition time, high- to low-level output¶ RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 0.53 2 3.2 µs tTLH Transition time, low- to high-level output# RL = 3 kΩ to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs tTHL Transition time, high- to low-level output# RL = 3 kΩ to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs SR Output slew rate RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 10 30 V/µs 4 § tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points. ¶ Measured between 10% and 90% points of output waveform # Measured between 3-V and – 3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 RECEIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT + Positive-going input threshold voltage See Figure 5 1.7 2 2.55 V VIT – Negative-going input threshold voltage See Figure 5 0.65 1 1.25 V Vhys Input hysteresis voltage (VIT +–VIT –) 600 1000 VI = 0.75 V, VOH VOL High level output voltage High-level Low-level output voltage VI = 0 0.75 75 V V, See Figure 5 VI = 3 V, VI = 2.5 V IOH = – 20 µA, See Figure 5 and Note 5 3.5 2.8 4.4 IOH = – 1 mA, A VCC = 4.5 V VCC = 5 V 3.8 4.9 VCC = 5.5 V See Figure 5 4.3 5.4 IOL = 3.2 mA, mV V 0.17 0.4 3.6 4.6 8.3 0.43 0.55 1 –3.6 –5 –8.3 –0.43 –0.55 –1 V IIH High level input current High-level IIL Low level input current Low-level IOS(H) High-level short-circuit g output current 75 V VI = 0 0.75 V, VO = 0 0, See Figure 4 8 –8 15 –15 mA IOS(L) Low-level short-circuit output current VI = VCC, VO = VCC, See Figure 4 13 25 mA ICC Supply current from VCC No load, All inputs at 0 or 5 V 320 450 320 450 VI = 3 V VI = – 2.5 V VI = – 3 V VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V mA mA µA † All typical values are at TA = 25°C. NOTE 5: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs remain in the high state. switching characteristics at TA = 25°C, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX RL = 5 kΩ, MIN UNIT 3 4 µs tPLH Propagation delay time, low- to high-level output CL = 50 pF, See Figure 6 tPHL Propagation delay time, high- to low-level output CL = 50 pF, See Figure 6 RL = 5 kΩ, 3 4 µs tTLH Transition time, low- to high-level output‡ CL = 50 pF, See Figure 6 RL = 5 kΩ, 300 450 ns tTHL Transition time, high- to low-level output‡ CL = 50 pF, See Figure 6 RL = 5 kΩ, 100 300 ns tw(N) Duration of longest pulse rejected as noise§ CL = 50 pF, RL = 5 kΩ 1 4 µs ‡ Measured between 10% and 90% points of output waveform § The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION IOS(L) VDD VCC VDD or GND VDD – IOS(H) VSS or GND VI VCC IIH VI – IIL VO RL = 3 kΩ VI VSS VSS Figure 1. Driver Test Circuit VOH, VOL, IOS(L), IOS(H) Figure 2. Driver Test Circuit, IIL, IIH VDD 3V Input VCC Input 1.5 1.5 0V Pulse Generator (See Note B) tPHL RL CL (see Note A) tPLH 50% 10% Output VSS VOH 90% 90% 50% 10% tTHL tTLH VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. Figure 3. Driver Test Circuit and Voltage Waveforms VDD VDD VCC VCC – IOS(H) VIT, VI VI IOS(L) VOH VOL VCC – IOH IOL VSS VSS Figure 4. Receiver Test Circuit, IOS(H), IOS(L) POST OFFICE BOX 655303 Figure 5. Receiver Test Circuit, VIT, VOL, VOH • DALLAS, TEXAS 75265 7 SN65C1406, SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148E – MAY 1990 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 4V VDD Input VCC Input 50% 50% 0V Pulse Generator (See Note B) tPHL RL CL (see Note A) tPLH 90% 90% 50% 10% Output VSS VOH 50% 10% tTLH tTHL VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: C. CL includes probe and jig capacitance. D. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. Figure 6. Receiver Test Circuit and Voltage Waveforms APPLICATION INFORMATION The TIA/EIA-232-F specification is for data interchange between a host computer and a peripheral at signaling rates up to 20 kbit/s. Many TIA/EIA-232-F devices will operate at higher data rates with lower capacitive loads (short cables). For reliable operation at greater than 20 kbit/s, the designer needs to have control of both ends of the cable. By mixing different types of TIA/EIA-232-F devices and cable lengths, errors can occur at higher frequencies (above 20 kbit/s). When operating within the TIA/EIA-232-F requirements of less than 20 kbit/s and with compliant line circuits, interoperability is assured. For applications operating above 20 kbit/s, the design engineer should consider devices and system designs that meet the TIA/EIA-232-F requirements. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65C1406D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C1406 Samples SN65C1406DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C1406 Samples SN75C1406D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 Samples SN75C1406DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 Samples SN75C1406DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 Samples SN75C1406DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 Samples SN75C1406N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75C1406N Samples SN75C1406NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN75C1406 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of