SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
D
D
D
D
D
D
D
D
D
D
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Single Chip With Easy Interface Between
UART and Serial-Port Connector
Less Than 9-mW Power Consumption
Wide Driver Supply Voltage . . . 4.5 V to
13.2 V
Driver Output Slew Rate Limited to
30 V/µs Max
Receiver Input Hysteresis . . . 1100 mV Typ
Push-Pull Receiver Outputs
On-Chip Receiver 1-µs Noise Filter
Functionally Interchangeable With Texas
Instruments SN75185
Operates Up to 120 kbit/s Over a 3-Meter
Cable (See Application Information for
Conditions)
DW OR N PACKAGE
(TOP VIEW)
VDD
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
VSS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
GND
description
The SN75C185 is a low-power BiMOS device containing three independent drivers and five receivers that are
used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). Typically, the
SN75C185 replaces one SN75188 and two SN75189 devices. This device conforms to TIA/EIA-232-F. The
drivers and receivers of the SN75C185 are similar to those of the SN75C188 and SN75C189A, respectively.
The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the receivers have
filters that reject input noise pulses that are shorter than 1 µs. Both these features eliminate the need for external
components.
The SN75C185 uses the low-power BiMOS technology. In most applications, the receivers contained in this
device interface to single inputs of peripheral devices such as ACEs, UARTS, or microprocessors. By using
sampling, such peripheral devices usually are insensitive to the transition times of the input signals. If this is not
the case, or for other uses, it is recommended that the SN75C185 receiver outputs be buffered by single Schmitt
input gates or single gates of the HCMOS, ALS, or 74F logic families.
The SN75C185 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
logic symbol†
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
logic diagram (positive logic)
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
RY1
RY1
RA2
RY2
RA3
RY3
DY1
DA1
DY2
DA2
RA4
RY4
DY3
DA3
RA5
RY5
RY2
RY3
DA1
DA2
RY4
DA3
RY5
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
RA1
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SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
equivalent schematics of inputs and outputs
EQUIVALENT DRIVER INPUT
EQUIVALENT DRIVER OUTPUT
VDD
VDD
Input
DA
Internal
1.4-V Ref
to GND
160 Ω
74 Ω
Output
DY
GND
GND
VSS
72 Ω
VSS
EQUIVALENT RECEIVER INPUT
EQUIVALENT RECEIVER OUTPUT
VCC
Input
RA
3.4 kΩ
ESD
Protection
ESD
Protection
1.5 kΩ
Output
RY
530 kΩ
GND
GND
All resistor values are nominal.
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3
SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 V
Supply voltage, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 13.5 V
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 V to 30 V
Output voltage range, VO: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 6 V to VDD + 6 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
VDD
VSS
VCC
Supply voltage
VI
Input voltage (see Note 3)
VIH
VIL
High-level input voltage
IOH
IOL
High-level output current
Drivers
Receivers
Drivers
Low-level input voltage
NOM
UNIT
4.5
12
13.2
V
– 4.5
– 12
– 13.2
V
4.5
5
6
V
VDD
25
V
VSS + 2
– 25
2
V
Receivers
High-level output current
MAX
0.8
V
–1
mA
3.2
mA
TA
Operating free-air temperature
0
70
°C
NOTE 3: The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only, e.g., if – 10 V is a maximum, the typical value is a more negative voltage.
supply currents
PARAMETER
TEST CONDITIONS
TYP
MAX
VSS = – 5 V
VSS = – 12 V
MIN
115
200
115
200
– 115
– 200
– 115
– 200
IDD
Supply current from VDD
No load,,
All inputs at 2 V or 0.8 V
VDD = 5 V,
VDD = 12 V,
ISS
Supply current from VSS
No load,,
All inputs at 2 V or 0.8 V
VDD = 5 V,
VDD = 12 V,
VSS = – 5 V
VSS = – 12 V
ICC
Supply current from VCC
No load
All inputs at 0 or 5 V
VDD = 5 V,
VDD = 12 V,
VSS = – 5 V
VSS = – 12 V
4
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750
750
UNIT
µA
µA
µA
SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
DRIVER SECTION
electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V,
VCC = 5 V ± 10% (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDD = 5 V,
VDD = 12 V
VSS = – 5 V
VSS = – 12 V
VDD = 5 V,
VDD = 12 V
VSS = – 5 V
VSS = – 12 V
TYP†
4
4.5
10
10.8
MAX
UNIT
VOH
High level output voltage
High-level
VIL = 0.8 V,,
See Figure 1
RL = 3 kΩ,,
VOL
Low-level output voltage
g
(see Note 3)
VIH = 0.8 V,,
See Figure 1
RL = 3 kΩ,,
High-level input current
See Figure 2
1
µA
Low-level input current
VI = 5 V,
VI = 0,
See Figure 2
–1
µA
IOS(H)
High-level
short-circuit
g
output current (see Note 4)
VO = 0 or VO = VSS,
VI = 0.8 V,,
See FIgure 1
IOS(L)
Low-level short-circuit
output current (see Note 4)
VI = 2 V,,
See Figure 1
ro
Output resistance
VDD = VSS = VCC = 0,
See Note 5
IIH
IIL
VO = 0 or VO = VDD,
VO = – 2 V to 2 V,
V
– 4.4
–4
– 10.7
– 10
V
45
– 4.5
– 12
19 5
– 19.5
mA
45
4.5
12
19 5
19.5
mA
300
400
Ω
† All typical values are at TA = 25 °C.
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only, e.g., if – 10 V is a maximum, the typical value is a more negative voltage.
4. Not more than one output should be shorted at one time.
5. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C (unless otherwise
noted) (see Figure 3)
PARAMETER
tPLH
Propagation delay time,
low- to high-level output (see Note 6)
tPHL
Propagation delay time,
high- to low-level output (see Note 6)
TEST CONDITIONS
RL = 3 kΩ to 7 kΩ,
MIN
CL = 15 pF
TYP
MAX
UNIT
1.2
3
µs
2.5
3.5
µs
tTLH
tTHL
Transition time, low- to high-level output
0.53
2
3.2
µs
Transition time, high- to low-level output
0.53
2
3.2
µs
tTLH
tTHL
Transition time, low- to high-level output (see Note 7)
Transition time, high- to low-level output (see Note 7)
RL = 3 kΩ to 7 kΩ
kΩ,
CL = 2500 pF
1
µs
1
µs
SR
Output slew rate (see Note 7)
RL = 3 kΩ to 7 kΩ,
CL = 15 pF
4
10
30
V/µs
NOTES: 6. tPHL and tPLH include the additional time due to on-chip slew rate and are measured at the 50% points.
7. Measured between 3-V and – 3-V points of output waveform TIA/EIA-232-F conditions), and all unused inputs are tied either high
or low.
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SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
RECEIVER SECTION
electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V,
VCC = 5 V ± 10% (unless otherwise noted)
MIN
TYP†
MAX
UNIT
See Figure 5
1.6
2.1
2.55
V
See Figure 5
0.65
1
1.25
V
600
1100
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshhold
voltage
VIT–
Negative-going input threshhold
voltage
Vhys
Input hysteresis voltage
(VIT + – VIT–)
VI = 0.75 V,
VOH
High level output voltage
High-level
VI = 0.75 V,
IOH = – 1 mA,
See Figure 5
VOL
Low-level output voltage
VI = 3 V,
VI = 3 V
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IOH = – 20 µA,
VCC = 4.5 V
See Figure 5 and Note 8
VCC = 5 V
VCC = 5.5 V
IOL = 3.2 mA,
3.5
2.8
4.4
3.8
4.9
4.3
See Figure 5
VI = 25 V
VI = – 3 V
VI = – 25 V
VI = 0.75 V,
mV
V
5.4
0.17
0.4
0.43
0.55
1
3.6
4.6
8.3
– 0.43
– 0.55
–1
– 3.6
– 5.0
– 8.3
V
mA
mA
IOS(H) Short-circuit output at high level
VO = 0,
See Figure 4
–8
– 15
mA
IOS(L) Short-circuit output at low level
VI = VCC,
VO = VCC,
See Figure 4
13
25
mA
† All typical values are at TA = 25 °C.
NOTE 8: If the inputs are left unconnected, the receiver interprets this as an input low, and the receiver outputs remain in the high state.
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C (unless otherwise
noted) (see Figure 6)
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low- to high-level output
tTLH
tTHL
Transition time, low- to high-level output
tw(N)
Propagation delay time, high- to low-level output
RL = 5 kΩ
kΩ,
MIN
CL = 50 pF
Transition time, high- to low-level output
Duration of longest pulse rejected as noise
(see Note 9)
RL = 5 kΩ,
CL = 50 pF
1
TYP
MAX
3
4
UNIT
µs
3
4
µs
300
450
ns
100
300
ns
4
µs
NOTE 9: The receiver ignores any postive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or
negative-going pulse greater than the maximum of tw(N).
6
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SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
IOS(L)
VDD or GND
– IOS(H)
VSS or GND
VI
VO
RL = 3 kΩ
(for VOH and VOL tests only)
Figure 1. Driver Test Circuit
for VOH, VOL, IOS(H), and IOS(L)
IIH
VI
– IIL
VI
Figure 2. Driver Test Circuit for IIH and IIL
3V
Input
1.5 V
1.5 V
Input
Pulse
Generator
(See Note B)
0V
t PHL
Output
CL
(see Note A)
RL
90%
Output
50%
10%
t PLH
50%
10%
t THL
TEST CIRCUIT
90%
VOH
VOL
t TLH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
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SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
– IOS(H)
IOS(L)
VI
Figure 4. Receiver Test Circuit for IOS(H) and IOS(L)
– IOH
VIT, VI
VOH
VOL
IOL
Figure 5. Receiver Test Circuit for VIT, VOH, and VOL
4V
Input
50%
50%
Input
Pulse
Generator
(See Note B)
0V
t PHL
Output
RL
CL
(see Note A)
90%
Output
50%
10%
t PLH
50%
10%
t THL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 6. Receiver Propagation and Transition Times
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VOH
VOL
t TLH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
8
90%
SN75C185
LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
SLLS065F – AUGUST 1989 – REVISED JANUARY 2000
APPLICATION INFORMATION
– 12 V
TL16C450
ACE
11
RI
43
12
DTR
37
13
CTS
40
14
SO
13
15
RTS
36
16
SI
11
17
DSR
41
18
DCD
42
19
20
GND
VSS
RY5
RA5
DA3
DY3
RY4
RA4
DA2
DY2
SN75C185
DA1
DY1
RY3
RA3
RY2
RA2
RY1
RA1
VCC
VDD
10
5
9
9
R1
8
DTR
7
CTS
6
TX
5
RTS
4
RX
3
DSR
2
DCD
1
TIA/EIA-232-F
DB9S
Connector
6
1
12 V
5V
Figure 7. Typical Connection
The SN75C185 supports data rates up to 120 kbit/s over a 3-meter cable. Laboratory experiments show that,
with CL= 500 pF and RL = 3 kΩ (minimum RS-232 input resistance load), the device can support this data rate.
The 500-pF load approximates a typical 3-meter cable because the maximum RS-232 specification is 2500 pF
(or about 15 meters). Figure 8 shows the test circuit used. Temperature was varied from 0°C to 70°C for the
experiment.
VDD
Input VCC
Pulse
Generator
(See Note A)
Output
RL
CL
VSS
NOTES: A. The pulse generator has the following characteristics: PRR = 60 kHz (120 kbit/s), ZO = 50 Ω.
B. VCC = 5 V, VDD = 12 V, VSS = –12 V.
Figure 8. Data-Rate Test Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN75C185DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
SN75C185
Samples
SN75C185DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
SN75C185
Samples
SN75C185N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN75C185N
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of