SN65C3222E, SN75C3222E
SLLS725B – JUNE 2006 – REVISED AUGUST 2021
3-V to 5.5-V Multichannel RS-232 Line Drivers and Receivers
with ±15-kV ESD Protection
1 Features
•
•
•
•
•
•
•
•
ESD Protection for RS-232 bus pins
– ±15-kV Human-body model (HBM)
– ±8-kV IEC 61000-4-2, Contact discharge
– ±15-kV IEC 61000-4-2, Air-gap discharge
Meet or exceed the requirements of TIA/EIA-232-F
and ITU v.28 standards
Operate with 3-V to 5.5-V VCC supply
Operate up to 1000 kbit/s
Two drivers and two receivers
Low standby current . . . 1 μA Typ
External capacitors . . . 4 × 0.1 μF
Accepts 5-V Logic Input with 3.3-V supply
2 Applications
•
•
•
•
•
Industrial PCs
Wired Networking
Data center and networking equipment
Notebooks
Hand-held equipment
an asynchronous communication controller and the
serial-port connector. The charge pump and four small
external capacitors allow operation from a single 3-V
to 5.5-V supply. The devices operate at typical data
signaling rates up to 1000 kbit/s and are improved
drop-in replacements for industry-popular '3222 twodriver, two-receiver functions.
The SN65C3222E and SN75C3222E can be placed
in the power-down mode by setting the power-down
( PWRDOWN) input low, which draws only 1 μA from
the power supply. When the devices are powered
down, the receivers remain active while the drivers
are placed in the high-impedance state. Also, during
power down, the onboard charge pump is disabled;
V+ is lowered to VCC, and V– is raised toward GND.
Receiver outputs also can be placed in the highimpedance state by setting enable ( EN) high.
Device Information
PART NUMBER
SN65C3222E
SN75C3222E
3 Description
The SN65C3222E and SN75C3222E consist of two
line drivers, two line receivers, and a dual chargepump circuit with ±15-kV ESD protection pin to pin
(serial-port connection pins, including GND).
(1)
PACKAGE(1)
BODY SIZE (NOM)
DB (SSOP) (20)
10.2 mm x 5.30 mm
DW (SOIC) (20)
15.4 mm x 7.50 mm
PW (TSSOP) (20)
7.80 mm v 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
The devices meet the requirements of TIA/EIA-232F and provide the electrical interface between
DIN1
DIN2
PWRDOWN
EN
ROUT1
13
17
DOUT1
12
8
DOUT2
20
Powerdown
1
15
16
RIN1
5 kW
ROUT2
10
9
RIN2
5 kW
Pin numbers are for the DB, DW, and PW packages.
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65C3222E, SN75C3222E
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SLLS725B – JUNE 2006 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 ESD Ratings - IEC Specifications............................... 4
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information: SN65C3222E............................5
6.6 Thermal Information: SN75C3222E............................5
6.7 Electrical Characteristics.............................................5
6.8 Electrical Characteristics: Driver................................. 6
6.9 Switching Characteristics: Driver................................ 6
6.10 Electrical Characteristics: Receiver.......................... 7
6.11 Switching Characteristics: Receiver..........................7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Functional Block Diagram......................................... 10
8.2 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2006) to Revision B (August 2021)
Page
• Updated the list of Applications.......................................................................................................................... 1
• Deleted the Ordering Information table. Removed the RHL package from the Device Information table.......... 1
• Added the Device Information table, the Pin Configuration and Functions, the Detailed Description section,
the Application and Implementation section....................................................................................................... 1
• Deleted the Package thermal impedance from the Absolute Maximum Ratings ...............................................4
• Added the ESD Ratings table............................................................................................................................. 4
• Added the Thermal Information: SN65C3222E table......................................................................................... 5
• Changed the value of RθJA for PW package (previously in the Absolute Maximum Ratings table), and added
additional thermal parameters for all packages in the Thermal Information: SN65C3222E table...................... 5
• Added separate Thermal Information table for SN75C3222E............................................................................ 5
2
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5 Pin Configuration and Functions
DB, DW, OR PW PACKAGE
(TOP VIEW)
EN
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
ROUT2
1
20
2
19
3
18
4
17
5
16
6
7
15
14
8
13
9
12
10
11
PWRDOWN
VCC
GND
DOUT1
RIN1
ROUT1
NC
DIN1
DIN2
NC
NC − No internal connection
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
C1+
2
—
Charge pump capacitor pin
C1-
4
—
Charge pump capacitor pin
C2+
5
—
Charge pump capacitor pin
C2-
6
—
Charge pump capacitor pin
DIN1
13
I
Driver logic input
DIN2
12
I
Driver logic input
DOUT1
17
O
RS-232 driver output
DOUT2
8
O
RS-232 driver output
EN
1
I
Receiver enable, active low
GND
18
—
Ground
11,14
—
No internal connection
PWRDOWN
20
I
Driver disable, active low
RIN1
16
I
RS-232 receiver input
NC
RIN2
9
I
RS-232 receiver input
ROUT1
15
O
Receiver logic output
ROUT2
10
O
Receiver logic output
VCC
19
—
Power Supply
V+
3
—
Charge pump capacitor pin
V-
7
—
Charge pump capacitor pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range(2)
VCC
range(2)
V+
Positive-output supply voltage
V–
Negative-output supply voltage range(2)
V+ – V–
Supply voltage
Input voltage range
VO
Output voltage range
TJ
Operating virtual junction temperature
Tstg
Storage temperature range
(2)
MAX
6
V
–0.3
7
V
0.3
–7
V
13
V
difference(2)
VI
(1)
MIN
–0.3
Driver ( EN, PWRDOWN)
–0.3
6
Receiver
–25
25
–13.2
13.2
–0.3
VCC + 0.3
Driver
Receiver
–65
UNIT
V
V
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
6.2 ESD Ratings
VALUE
V (ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/
ESDA/JEDEC JS-002(2)
(1)
(2)
All pins except RIN1, RIN2, DOUT1 and
DOUT2 pins
±3,000
RIN1, RIN2, DOUT1 and DOUT2 pins to
GND
±15,000
All pins
±1,500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
V (ESD)
(1)
4
Electrostatic
discharge
IEC 61000-4-2, Contact Discharge
IEC 61000-4-2, Air Discharge (1)
(1)
RIN1, RIN2, DOUT1, and DOUT2 pins
only
±8,000
±15,000
UNIT
V
For the PW Package of SN65C3222E only, a minimum of 1-µF capacitor is required between VCC and GND to meet the specified IEC
61000-4-2 rating
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6.4 Recommended Operating Conditions
See Figure 9-1 and (1)
Supply voltage
VCC = 5 V
VIH
Driver and control high-level input voltage
DIN, EN, PWRDOWN
VIL
Driver and control low-level input voltage
DIN, EN, PWRDOWN
VI
Driver and control input voltage
DIN, EN, PWRDOWN
VI
Receiver input voltage
TA
(1)
MIN
NOM
MAX
3
3.3
3.6
4.5
5
5.5
VCC = 3.3 V
VCC = 3.3 V
V
2
VCC = 5 V
Operating free-air temperature
UNIT
V
2.4
0.8
V
0
5.5
V
–25
25
V
SN75C3222E
0
70
SN65C3222E
–40
85
°C
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
6.5 Thermal Information: SN65C3222E
SN65C3222E
THERMAL METRIC(1)
DB (SSOP)
DW (SOIC)
PW (TSSOP)
20 Pins
20 Pins
20 Pins
UNIT
70
58
94.1
°C/W
R θJA
Junction-to-ambient thermal resistance
R θJC(top)
Junction-to-case (bottom) thermal
resistance
33.6
30.0
35.2
°C/W
R θJB
Junction-to-board thermal resistance
36.4
29.6
45.5
°C/W
ψ JT
Junction-to-top characterization parameter
4.8
7.7
3.1
°C/W
ψ JB
Junction-to-board characterization
parameter
35.9
29.3
45.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.6 Thermal Information: SN75C3222E
SN75C3222E
THERMAL
METRIC1
DB (SSOP)
DW (SOIC)
PW (TSSOP)
20
20
20
UNIT
70
58
83
°C/W
R θJA
Junction-to-ambient thermal resistance
R θJC(top)
Junction-to-case (top) thermal
resistance
33.6
30.0
24.8
°C/W
R θJB
Junction-to-board thermal resistance
36.4
29.6
39.5
°C/W
ψ JT
Junction-to-top characterization
parameter
4.8
7.7
1.1
°C/W
ψ JB
Junction-to-board characterization
parameter
35.9
29.3
39.0
°C/W
6.7 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1)
TEST CONDITIONS(2)
PARAMETER
II
ICC
(1)
(2)
Input leakage current ( EN, PWRDOWN)
Supply current
No load, PWRDOWN at VCC
Supply current (powered off)
No load, PWRDOWN at GND
MIN
TYP(1)
MAX
±0.01
±1
μA
0.3
1
mA
1
10
μA
UNIT
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.8 Electrical Characteristics: Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
(3)
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = GND
5
5.4
V
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = VCC
–5
–5.4
V
IIH
High-level input current
VI = VCC
±0.01
±1
μA
IIL
Low-level input current
VI at GND
±0.01
±1
μA
IOS
Short-circuit output current(2)
±35
±60
mA
ro
Output resistance
IOZ
(1)
(2)
(3)
VCC = 3.6 V
VO = 0 V
VCC = 5.5 V
VCC, V+, and V– = 0 V,
Output leakage current
PWRDOWN = GND
VO = ±2 V
300
10M
Ω
VCC = 3 V to 3.6 V,
VO = ±12 V
±25
VCC = 4.5 V to 5.5 V,
VO = ±10 V
±25
μA
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
6.9 Switching Characteristics: Driver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1)
TEST CONDITIONS(3)
PARAMETER
CL = 1000 pF
RL = 3 kΩ,
One DOUT switching
CL = 250 pF,
VCC = 3 V to 4.5 V
1000
CL = 1000 pF,
VCC = 4.5 V to 5.5 V
1000
tsk(p)
Pulse skew(2)
CL = 150 pF to 2500 pF,
RL = 3 kΩ to 7 kΩ,
See Figure 7-2
Slew rate,
transition region
(see Figure 7-1)
RL = 7 kΩ,
CL = 150 pF to 1000 pF
SR(tr)
RL = 3 kΩ
MAX
UNIT
250
Maximum data rate
(See Figure 7-1)
(1)
(2)
(3)
6
MIN TYP(1)
kbit/s
300
8
ns
90
CL = 1000 pF
12
60
CL = 150 pF to 250 pF
24
150
V/μs
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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6.10 Electrical Characteristics: Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1)
TEST CONDITIONS(2)
PARAMETER
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis (VIT+ – VIT–)
IOZ
Output leakage current
EN = 1
ri
Input resistance
VI = ±3 V to ±25 V
(1)
(2)
MIN
TYP(1)
VCC – 0.6
VCC – 0.1
MAX
V
0.4
VCC = 3.3 V
1.5
2.4
VCC = 5 V
1.8
2.4
VCC = 3.3 V
0.6
1.2
VCC = 5 V
0.8
1.5
UNIT
V
V
V
0.3
V
±0.05
±10
μA
5
7
kΩ
3
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
6.11 Switching Characteristics: Receiver
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS(3)
PARAMETER
TYP(1)
UNIT
tPLH
Propagation delay time, low- to high-level output
CL = 150 pF, See Figure 7-3
300
ns
tPHL
Propagation delay time, high- to low-level output
CL = 150 pF, See Figure 7-3
300
ns
ten
Output enable time
CL = 150 pF, RL = 3 kΩ, See Figure 7-4
200
ns
tdis
Output disable time
CL = 150 pF, RL = 3 kΩ, See Figure 7-4
200
ns
See Figure 7-3
300
ns
tsk(p)
(1)
(2)
(3)
Pulse
skew(2)
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
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7 Parameter Measurement Information
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
CL
(see Note A)
tTHL
3V
PWRDOWN
tTLH
VOH
3V
3V
Output
−3 V
−3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) +
A.
B.
t
THL
6V
or t
TLH
CL includes probe and jig capacitance.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-1. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
0V
CL
(see Note A)
tPLH
tPHL
VOH
3V
PWRDOWN
50%
50%
Output
VOL
TEST CIRCUIT
A.
B.
1.5 V
1.5 V
VOLTAGE WAVEFORMS
CL includes probe and jig capacitance.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-2. Driver Pulse Skew
EN
0V
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
A.
B.
VOLTAGE WAVEFORMS
CL includes probe and jig capacitance.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-3. Receiver Propagation Delay Times
8
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VCC
GND
S1
3V
Input
RL
3 V or 0 V
0V
tPZH
(S1 at GND)
CL
(see Note A)
S1 at GND)
VOH
Output
50%
0.3 V
Generator
(see Note B)
1.5 V
tPHZ
Output
EN
1.5 V
50 Ω
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
B.
CL includes probe and jig capacitance.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 7-4. Receiver Enable and Disable Times
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8 Detailed Description
8.1 Functional Block Diagram
13
DIN1
17
DOUT1
12
DIN2
8
DOUT2
20
PWRDOWN
Powerdown
1
EN
15
ROUT1
16
RIN1
5 kW
10
ROUT2
9
RIN2
5 kW
Pin numbers are for the DB, DW, and PW packages.
Figure 8-1. Logic Diagram (Positive Logic)
8.2 Device Functional Modes
Table 8-1. Function Tables: Each Driver
INPUTS(1)
DIN
(1)
OUTPUT
DOUT
PWRDOWN
X
L
Z
L
H
H
H
H
L
H = high level, L = low level, X = irrelevant, Z = high impedance
Table 8-2. Function Table: Each Receiver
INPUTS(1)
RIN
(1)
10
OUTPUT
ROUT
EN
L
L
H
L
H
L
X
H
Z
Open
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off),
Open = input disconnected or connected driver off
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
1
EN
2
+
C1
−
3
C3†
+
20
Powerdown
VCC
C1+
V+
GND
PWRDOWN
19
18
+ C
BYPASS
− = 0.1 µF
−
4
17
C1−
DOUT1
16
5
C2+
+
C2
−
6
7
C4
DOUT2
RIN2
−
RIN1
5 kW
15
C2−
14
V−
ROUT1
NC
+
13
8
9
DIN1
12
5 kW
ROUT2
11
10
DIN2
NC
† C3 can be connected to V
CC or GND.
NOTES: A. Resistor values shown are nominal.
B. NC − No internal connection
C. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
VCC vs CAPACITOR VALUES
VCC
3.3 V " 0.3 V
C1
0.1 µF
C2, C3, and C4
0.1 µF
5 V " 0.5 V
0.047 µF
0.33 µF
3 V to 5.5 V
0.1 µF
0.47 µF
Figure 9-1. Typical Operating Circuit and Capacitor Values
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SLLS725B – JUNE 2006 – REVISED AUGUST 2021
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN65C3222E SN75C3222E
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65C3222EDB
ACTIVE
SSOP
DB
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MU222E
Samples
SN65C3222EDBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MU222E
Samples
SN65C3222EDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C3222E
Samples
SN65C3222EDWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C3222E
Samples
SN65C3222EPWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
MU222E
Samples
SN75C3222EPW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
MY222E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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