SN75C3232D

SN65C3232, SN75C3232 SLLS540C – JULY 2002 – REVISED JUNE 2021 3-V to 5.5-V Multichannel RS-232 Compatible Line Driver and Receiver 1 Features 3 Description • • • • • • The SN65C3232 and SN75C3232 consist of two line drivers, two line receivers, and a dual chargepump circuit with ±15-kV ESD protection pin-to-pin (serial-port connection pins, including GND). These devices provide the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The devices operate at typical data signaling rates up to 1 Mbit/s and a driver output slew rate of 24 V/μs to 150 V/μs. Operate with 3-V to 5.5-V VCC supply Operate up to 1 Mbit/s Low supply current: 300 μA typical External capacitors: 4 × 0.1 μF Accept 5-V logic input with 3.3-V supply RS-232 bus-pin ESD protection exceeds ±15 kV using human-body model (HBM) 2 Applications • • • • • • • • Industrial PCs Wired networking Data center and enterprise computing Battery-powered systems Notebooks Laptops Palmtop PCs Hand-held equipment Device Information PART NUMBER SN65C3232 SN75C3232 (1) PACKAGE(1) BODY SIZE (NOM) D (SOIC) (16) 9.90 mm x 3.91 mm DB (SSOP) (16) 6.20 mm x 5.30 mm DW (SOIC) (16) 10.3 mm x 7.50 mm PW (TSSOP) (16) 5.00 mm v 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. spacer spacer 3.3 V, 5 V POWER 2 DIN 2 TX RS232 2 ROUT DOUT RX 2 RIN RS232 Simplified Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Driver Section - Electrical Characteristics...................6 6.7 Switching Characteristics............................................6 6.8 Receiver Section - Electrical Characteristics.............. 7 6.9 Switching Characteristics............................................7 6.10 Typical Characteristics.............................................. 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 10 Layout...........................................................................14 10.1 Layout Guidelines................................................... 14 10.2 Layout Example...................................................... 14 11 Device and Documentation Support..........................15 11.1 Documentation Support.......................................... 15 11.2 Receiving Notification of Documentation Updates.. 15 11.3 Support Resources................................................. 15 11.4 Trademarks............................................................. 15 11.5 Electrostatic Discharge Caution.............................. 15 11.6 Glossary.................................................................. 15 12 Mechanical, Packaging, and Orderable Information.................................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November 2004) to Revision C (June 2021) Page • Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................................................................................1 • Added Applications: Industrial PCs, Wired networking, and Data center and enterprise computing..................1 • Added thermal parameter values for all packages and changed the thermal parameters for D package in the Thermal Information table...................................................................................................................................5 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 5 Pin Configuration and Functions C1+ V+ C1− C2+ C2− V− DOUT2 RIN2 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC GND DOUT1 RIN1 ROUT1 DIN1 DIN2 ROUT2 Figure 5-1. D, DW, DB and PW Package, 16-Pin SOIC, SSOP and TSSOP, Top View PIN NAME NO. I/O DESCRIPTION C1+ 1 — Positive lead of C1 capacitor V+ 2 O Positive charge pump output for storage capacitor only C1– 3 — Negative lead of C1 capacitor C2+ 4 — Positive lead of C2 capacitor C2– 5 — Negative lead of C2 capacitor V– 6 O Negative charge pump output for storage capacitor only DOUT2 7 O RS232 line data output (to remote RS232 system) RIN2 8 I RS232 line data input (from remote RS232 system) ROUT2 9 O Logic data output (to UART) DIN2 10 I Logic data input (from UART) DIN1 11 I Logic data input (from UART) ROUT1 12 O Logic data output (to UART) RIN1 13 I RS232 line data input (from remote RS232 system) DOUT1 14 O RS232 line data output (to remote RS232 system) GND 15 — Ground VCC 16 — Supply Voltage, Connect to external 3-V to 5.5-V power supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 3 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range(2) VCC range(2) V+ Positive-output supply voltage V– Negative-output supply voltage range(2) V+ – V– Supply voltage Input voltage range VO Output voltage range TJ Operating virtual junction temperature Tstg Storage temperature range (2) MAX 6 V –0.3 7 V 0.3 –7 V 13 V difference(2) VI (1) MIN –0.3 Drivers –0.3 6 Receivers –25 25 –13.2 13.2 –0.3 VCC + 0.3 Drivers Receivers –65 UNIT V V 150 °C 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute MaximumRatings do not imply functional operation of the device at these or any other conditions beyond those listed underRecommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability,functionality, performance, and shorten the device lifetime. All voltages are with respect to network GND. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge All pins except RIN and DOUT Human body model (HBM), per ANSI/ ESDA/JEDEC JS-001(1) RIN and DOUT Pins Charged-device model (CDM), per JEDEC specification JESD22-C101(2) UNIT ±3000 ±15,000 All pins V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See Typical Operating Circuit and Capacitor Values, See (1) VCC = 3.3 V Supply voltage VIH Driver high-level input voltage DIN VIL Driver low-level input voltage DIN Driver input voltage DIN VI TA (1) 4 VCC = 5 V VCC = 3.3 V VCC = 5 V NOM MAX 3 3.3 3.6 4.5 5 5.5 2 UNIT V V 2.4 0.8 0 5.5 –25 25 SN75C3232 0 70 SN65C3232 –40 85 Receiver input voltage Operating free-air temperature MIN V V °C Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 6.4 Thermal Information SN65C3232, SN75C3232 THERMAL METRIC(1) PW (TSSOP) D (SOIC) DW (SOIC) DB (SSOP) 16 PINS 16 PINS 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 108.0 85.9 57.0 46.0 °C/W RθJCtop Junction-to-case (top) thermal resistance 20.8 43.1 33.5 36.2 °C/W RθJB Junction-to-board thermal resistance 45.1 44.5 37.1 43.8 °C/W ψJT Junction-to-top characterization parameter 0.6 10.1 7.5 4.2 °C/W ψJB Junction-to-board characterization parameter 45.1 44.1 37.1 42.9 °C/W RθJCbot Junction-to-case (bottom) thermal resistance – – – – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values) PARAMETER(2) ICC (1) (2) Supply current TEST CONDITIONS No load, VCC = 3.3 V or 5 V MIN TYP(1) MAX 0.3 1 UNIT mA All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 5 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 6.6 Driver Section - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values) TEST CONDITIONS(3) PARAMETER MIN TYP(1) 5.4 VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 IIH High-level input current VI = VCC IIL Low-level input current VI at GND Short-circuit output current(2) VO = 0 V ro Output resistance VCC, V+, and V– = 0 V, (1) (2) (3) V ±1 μA μA ±0.01 ±1 VCC = 3.6 V ±35 ±60 VCC = 5.5 V ±35 ±90 VO = ±2 V 300 UNIT V –5.4 ±0.01 IOS MAX 10M mA Ω All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one output should be shorted at a time. Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. 6.7 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values ) TEST CONDITIONS(3) PARAMETER Maximum data rate RL = 3 kΩ, (see Figure 7-1) One DOUT switching CL = 1000 pF MAX UNIT 250 CL = 250 pF, VCC = 3 V to 4.5 V 1000 1000 CL = 1000 pF, VCC = 4.5 V to 5.5 V tsk(p) Pulse skew(2) CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ, See Figure 7-2 SR(tr) Slew rate, transition region (see Figure 7-1 ) RL = 3 kΩ to 7 kΩ, CL = 150 pF to 1000 pF, VCC = 3.3 V (1) (2) (3) 6 MIN TYP(1) kbit/s 300 18 ns 150 V/μs All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 6.8 Receiver Section - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values) TEST CONDITIONS(2) PARAMETER VOH High-level output voltage IOH = –1 mA VOL Low-level output voltage IOL = 1.6 mA VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input hysteresis (VIT+ – VIT–) ri Input resistance (1) (2) MIN TYP(1) VCC – 0.6 VCC – 0.1 MAX V 0.4 VCC = 3.3 V 1.5 2.4 VCC = 5 V 1.8 2.4 VCC = 3.3 V 0.6 1.2 VCC = 5 V 0.8 1.5 3 5 V V V 0.3 VI = ±3 V to ±25 V UNIT V 7 kΩ All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. 6.9 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values) TEST CONDITIONS(3) PARAMETER TYP(1) UNIT tPLH Propagation delay time, low- to high-level output CL = 150 pF 300 ns tPHL Propagation delay time, high- to low-level output CL = 150 pF 300 ns tsk(p) Pulse skew(2) 300 ns (1) (2) (3) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 7 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 6 0 5 ±1 DOUT Voltage (V) DOUT Voltage (V) 6.10 Typical Characteristics 4 3 2 1 ±2 ±3 ±4 ±5 VOH VOL 0 ±6 0 5 10 15 20 DOUT Current (mA) 25 VCC = 3.3 V 5 10 15 DOUT Current (mA) 20 25 C001 VCC = 3.3 V Figure 6-1. DOUT VOH vs Load Current, Both Drivers Loaded 8 0 C001 Figure 6-2. DOUT VOL vs Load Current, Both Drivers Loaded Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 7 Parameter Measurement Information 3V Input Generator (see Note B) 1.5 V RS-232 Output 50 Ω RL 1.5 V 0V CL (see Note A) tTHL tTLH 3V 3V Output -3 V -3 V VOH VOL TEST CIRCUIT VOLTAGE WAVEFORMS SR(tr) = A. B. t THL 6V or t TLH CL includes probe and jig capacitance. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 7-1. Driver Slew Rate 3V Input Generator (see Note B) 1.5 V RS-232 Output 50 Ω RL 1.5 V 0V CL (see Note A) tPHL tPLH VOH 50% Output 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS A. B. CL includes probe and jig capacitance. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 7-2. Driver Pulse Skew 3V Input 1.5 V 1.5 V −3 V Output Generator (see Note B) 50 Ω tPHL CL (see Note A) tPLH VOH 50% Output 50% VOL TEST CIRCUIT A. B. VOLTAGE WAVEFORMS CL includes probe and jig capacitance. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns. Figure 7-3. Receiver Propagation Delay Times Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 9 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 8 Detailed Description 8.1 Overview The devices consists of two line drivers, two-line receivers, and a dual charge-pump circuit with IEC61000-4-2 ESD protection terminal to terminal (serial-port connection terminals, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s and a maximum of 30-V/μs driver output slew rate. Outputs are protected against shorts to ground. 8.2 Functional Block Diagram 3.3 V, 5 V POWER 2 DIN 2 TX RS232 2 ROUT DOUT RX 2 RIN RS232 8.3 Feature Description 8.3.1 Power The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires four external capacitors. 8.3.2 RS232 Driver Two drivers interface standard logic level to RS232 levels. Both DIN inputs must be valid high or low. 8.3.3 RS232 Receiver Two receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT. Each RIN input includes an internal standard RS232 load. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 8.4 Device Functional Modes Table 8-1 and Table 8-2 list the functional modes of the drivers and receivers of MAX3232E. Table 8-1. Each Driver(1) INPUT DIN (1) OUTPUT DOUT L H H L H = high level, L = low level Table 8-2. Each Receiver(1) INPUT RIN (1) OUTPUT ROUT L H H L Open H H = high level, L = low level, Open = input disconnected or connected driver off 11 14 DIN1 DOUT1 10 7 DIN2 DOUT2 12 13 ROUT1 RIN1 9 8 ROUT2 RIN2 Figure 8-1. Logic Diagram 8.4.1 VCC Powered by 3 V to 5.5 V The device is in normal operation. 8.4.2 VCC Unpowered, VCC = 0 V When the device is unpowered, it can be safely connected to an active remote RS232 device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 11 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information For proper operation, add capacitors as shown in Table 9-1. 9.1.1 Typical Application ROUT and DIN connect to UART or general-purpose logic lines. RIN and DOUT lines connect to a RS232 connector or cable. 1 16 + CBYPASS − = 0.1µF + C1 VCC C1+ 2 (1) + − C3 V+ GND 15 − 3 4 14 DOUT1 C1− 13 + C2 RIN1 C2+ 5 kΩ − 5 C2− 12 6 C4 − V− ROUT1 11 DIN1 + DOUT2 RIN2 7 10 8 9 DIN2 ROUT2 5 kΩ A. C3 can be connected to VCC or GND A. Resistor values shown are nominal. B. Nonpolorized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. Figure 9-1. Typical Operating Circuit and Capacitor Values Table 9-1. VCC vs Capacitor Values VCC 12 C1 C2, C3, C4 3.3 V ± 0.3 V 0.1 µF 0.1 µF 5 V ± 0.5 V 0.047 µF 0.33 µF 3 V to 5.5 V 0.1 µF 0.47 µF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 9.1.1.1 Design Requirements The recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible The maximum recommended bit rate is 250 kbit/s. 9.1.1.2 Detailed Design Procedure All DIN inputs must be connected to valid low or high logic levels. Select capacitor values based on VCC level for best performance. 9.1.1.3 Application Performance Plots Voltage (V) Figure 9-2 curves are for 3.3-V VCC and 250-kbit/s alternative bit data stream. 6 5 4 3 2 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 DIN DOUT to RIN ROUT 0 1 2 3 4 5 6 7 8 Time ( s) 9 10 C001 Figure 9-2. 250 kbit/s Driver to Receiver Loopback Timing Waveform, VCC = 3.3 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 13 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 10 Layout 10.1 Layout Guidelines Keep the external capacitor traces short, specifically on the C1 and C2 nodes that have the fastest rise and fall times. 10.2 Layout Example Ground C3 C1 1 C1+ VCC 16 2 V+ GND 15 3 C1– DOUT1 14 4 C2+ RIN1 13 5 C2– ROUT1 12 VCC 0.1µF Ground C2 Ground 6 V– DIN1 11 7 DOUT2 DIN2 10 C4 8 RIN2 ROUT2 9 Figure 10-1. Layout Diagram 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 SN65C3232, SN75C3232 www.ti.com SLLS540C – JULY 2002 – REVISED JUNE 2021 11 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 11.1 Documentation Support 11.1.1 Related Documentation 11.1.1.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN65C3232 SN75C3232 15 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65C3232DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 Samples SN65C3232DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 Samples SN65C3232DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 Samples SN65C3232DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C3232 Samples SN65C3232PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3232 Samples SN75C3232DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA3232 Samples SN75C3232DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 Samples SN75C3232DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 Samples SN75C3232DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C3232 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of