SN75DP122
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DisplayPort 1:2 Switch With Integrated TMDS Translator
FEATURES
1
•
•
•
•
•
•
•
•
One Input Port to One of Two Output Ports
Integrated TMDS Level Translator with
Receiver Equalization
DP Port Supports Data Rates up to 2.7 Gbps
DP Port Supports Dual-Mode DisplayPort
DP Port Output Waveform Mimics Input
Waveform Characteristics
TMDS Port Supports Data Rates up to 2.5
Gbps
Integrated I2C Logic Block for DVI/HDMI
Connector Recognition
Enhanced ESD:
•
•
– 12 kV on all High Speed Pins
– 8 kV on all Auxiliary and I2C Pins
Enhanced Commercial Temperature Range:
0°C to 85°C
56 Pin 8 × 8 QFN Package
APPLICATIONS
•
Personal Computer Market
– Desktop PC
– Notebook PC
– Docking Station
– Standalone Video Card
DESCRIPTION
The SN75DP122 is a one Dual-Mode DisplayPort input to one Dual-Mode DisplayPort output or one TMDS
output. The TMDS output has a built in level translator compliant with Digital Video Interface (DVI) 1.0 and High
Definition Multimedia Interface (HDMI) 1.3b. The DisplayPort output follows the input signal in a manner that
provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking.
Through the SN75DP122 data rates of up to 2.7 Gbps through each link for a total throughput of up to 10.8 Gbps
can be realized.
In addition to the switching of the DisplayPort high speed signal lines, the SN75DP122 also supports the
switching of the bidirectional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels.
The Auxiliary differential pair supports Dual-Mode DisplayPort operation through the DisplayPort port. Through
the TMDS port the auxiliary port is configured as an I2C port with an integrated I2C repeater.
The SN75DP122 is characterized for operation over ambient air temperature of 0°C to 85°C.
TYPICAL APPLICATION
DisplayPort
Enabled
Monitor or HDTV
DP++
GPU
DP++
SN75DP122
TMDS
HDMI / DVI
Monitor or HDTV
Computer/Notebook/Docking Station
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN75DP122
SLLS892A – FEBRUARY 2008 – REVISED NOVEMBER 2008......................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DATA FLOW BLOCK DIAGRAM
DPVadj
DP_SINK 0(p)
Driver
DP_SINK 0(n)
VBIAS
50 W
50 W
Driver
ML_IN 0(p)
Receiver
ML_IN 0(n)
Driver
2-to-1
MUX
VBIAS
DP_SINK 3(p)
50 W
50 W
Driver
ML_IN 1(p)
DP_SINK 3(n)
Receiver
ML_IN 1(n)
TMDS_SINK 2(p)
Driver
VBIAS
TMDS_SINK 2(n)
50 W
50 W
ML_IN 2(p)
Driver
Receiver
ML_IN 2(n)
Driver
VBIAS
50 W
50 W
TMDS_SINK_CLK (p)
ML_IN 3(p)
Driver
TMDS_SINK_CLK (n)
Receiver
ML_IN 3(n)
VSadj
HPD
DP_HPD_SINK
Switching
Logic
Priority
CAD_SINK
CAD
__
LP
TMDS_HPD_SINK
AUX_SINK (p)
I2C Logic
AUX_SINK (n)
AUX(p)_I2C (SCL)
I2C_SCL
AUX(n)_I2C (SDA)
I2C_SDA
2
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I2C_SCL
I2C_SDA
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SN75DP122
LP
I2C_SCL
Priority
TMDS_HPD_SINK
I2C_EN
VDD
AUX(p)_I2C (SCL)
AUX(n)_I2C (SDA)
*1
VDD
HPD
CAD
DP_HPD_SINK
GND
AUX_SINK(n)
CAD_SINK
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42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
43
I2C_SDA
GND
GND
44
27
AUX_SINK(p)
45
26
VSadj
DP_SINK 3(n)
46
25
TMDS_SINK 2(p)
DP_SINK 3(p)
47
24
TMDS_SINK 2(n)
VDD
48
23
VCC
DP_SINK 2(n)
49
22
TMDS_SINK 1(p)
DP_SINK 2(p)
50
21
TMDS_SINK 1(n)
GND
51
20
DP_SINK 1(n)
52
19
GND
TMDS_SINK 0(p)
DP_SINK 1(p)
53
18
TMDS_SINK 0(n)
VDD
DP_SINK 0(n)
54
17
VCC
16
TMDS_SINK CLK(p)
DP_SINK 0(p)
56
1
TMDS_SINK CLK(n)
SN75DP122
5
6
7
8
9
15
10 11 12 13 14
ML_IN 0(p)
ML_IN 0(n)
GND
ML_IN 1(p)
ML_IN 1(n)
VDD
ML_IN 2(p)
ML_IN 2(n)
VCC
4
ML_IN 3(n)
3
GND
ML_IN 3(p)
2
VDD
DPVadj
55
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SN75DP122
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TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
MAIN LINK INPUT PINS
ML_IN 0
3, 4
I
DisplayPort main link channel 0 differential input
ML_IN 1
6, 7
I
DisplayPort main link channel 1 differential input
ML_IN 2
9, 10
I
DisplayPort main link channel 2 differential input
ML_IN 3
12, 13
I
DisplayPort main link channel 3 differential input
MAIN LINK PORT A OUTPUT PINS
DP_SINK 0
56, 55
O
DisplayPort main link port a channel 0 differential output
DP_SINK 1
53, 52
O
DisplayPort main link port a channel 1 differential output
DP_SINK 2
50, 49
O
DisplayPort main link port a channel 2 differential output
DP_SINK 3
47, 46
O
DisplayPort main link port a channel 3 differential output
MAIN LINK PORT B OUTPUT PINS
TMDS_SINK 2
25, 24
O
TMDS data 2 differential output
TMDS_SINK 1
22, 21
O
TMDS data 1 differential output
TMDS_SINK 0
19, 18
O
TMDS data 0 differential output
TMDS_SINK CLK
16, 15
O
TMDS data clock differential output
HPD
37
O
Hot plug detect output to the displayport source
DP_HPD_SINK
40
I
DisplayPort port hot plug detect input
TMDS_HPD_SINK
32
I
TMDS port hot plug detect input
AUX_I2C
36, 35
I/O
Source side bidirectional displayport auxiliary data line
AUX_SINK
45, 43
I/O
DisplayPort port bidirectional displayport auxiliary data line
29,
28
I/O
TMDS port bidirectional ddc data lines
HOT PLUG DETECT PINS
AUXILIARY DATA PINS
I2C_SCL
I2C_SDA
CABLE ADAPTER DETECT PINS
CAD
39
O
Cable adapter detect output to the displayport source
CAD_SINK
41
I
DisplayPort cable adapter detect input
LP
30
I
Low power select bar
Priority
33
I
Output port priority selection
DPVadj
1
I
DisplayPort main link output gain adjustment
VSadj
26
I
TMDS compliant voltage swing control
31
I
Internal I2C register enable, used for HDMI / DVI connector differentiation
CONTROL PINS
2
I C_EN
SUPPLY and GROUND PINS
VDD
*1
2, 8, 34, 48, 54
VDD
38
VCC
14, 17, 23
GND
5, 11, 20, 27, 42, 44, 51
4
5-V supply
HPD/CAD supply
3.3-V supply
Ground
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Table 1. Control Pin Lookup Table
SIGNAL
LEVEL
LP
(1)
STATE
H
Normal Mode
L
Low Power Mode
H
TMDS Port has
Priority
L
DP Port has Priority
If both DP_HPD_SINK and TMDS_HPD_SINK are high, the DP port is selected
H
HDMI
The Internal I2C register is active and readable when the TMDS port is selected
indicating that the connector being used is HDMI
L
DVI
4.53 kΩ
Increased Gain
Priority
I2C_EN
DPVadj
VSadj
(1)
DESCRIPTION
6.49 kΩ
Nominal Gain
10 kΩ
Decreased Gain
5.11 kΩ
Compliant Voltage
Swing
Normal operational mode for device
Device is forced into a low power state causing the outputs to go to a high impedance
state. All other inputs are ignored
If both DP_HPD_SINK and TMDS_HPD_SINK are high, the TMDS port is selected
The Internal I2C register is disabled and not readable when the TMDS port is selected
indicating that the connector being used is DVI
Main link displayport output has an increased voltage swing
Main link displayport output has a nominal voltage swing
Main link displayport output has a decreased voltage swing
Driver output voltage swing precision control to aid with system compliance
(H) Logic High; (L) Logic Low
Explanation of the internal switching logic of the SN75DP122 is located in the application section at the end of
this data sheet.
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
SN75DP122RTQR
75DP122
56-pin QFN Reel (large)
SN75DP122RTQT
75DP122
56-pin QFN Reel (small)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
Supply voltage range (2)
VDD, VDD*1
–0.3 to 5.25
V
Supply voltage range
VCC
–0.3 to 3.6
V
1.5
V
–0.3 to 4
V
HPD and CAD I/O
–0.3 to 5.25
V
Auxiliary I/O
–0.3 to 5.25
V
Control I/O
–0.3 to 5.25
V
Main Link I/O (ML_IN x, DP_SINK x) Differential Voltage
TMDS I/O
Voltage range
Human body model (3)
Electrostatic discharge
Auxiliary and I2C I/O
±8000
All other pins
±12000
Charged-device model (3)
±1000
V
Machine model (4)
±200
V
Continuous power dissipation
(1)
(2)
(3)
(4)
V
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method A115-A
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SN75DP122
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DISSIPATION RATINGS
PACKAGE
PCB JEDEC
STANDARD
TA < 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
Low-K
3623 mW
36.23 mW/°C
1449 mW
High-K
1109 mW
11.03 mW/°C
443.9 mW
56-Pin QFN (RTQ)
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
RθJB
Junction-to-board thermal
resistance
RθJC
Junction-to-case thermal
resistance
PD(1)
Device power dissipation
DisplayPort selected
LP = 5 V, ML: VID = 600 mV, 2.7 Gbps PRBS;
AUX: VID = 500 mV, 1 Mbps PRBS;
HPD/CAD = 5 V; VDD*1 = VDD
250
305
mW
PD(2)
Device power dissipation TMDS
selected
LP = 5 V, ML: VID = 500 mV, 2.5 Gbps PRBS;
I2C: VID = 3.3 V, 100 Kbps PRBS; HPD/CAD = 5
V; VDD*1 = VDD
270
420
mW
PSD
Device power dissipation under
low power
LP = 0 V, ML: VID = 600 mV, 2.7 Gbps PRBS;
AUX: VID = 500 mV, 1 Mbps PRBS; HPD/CAD =
5 V; VDD*1 = VDD
75
85
µW
(1)
4x4 Thermal vias under powerpad
11.03
°C/W
20.4
C/W
The maximum rating is simulated under 5.25 V VDD.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
4.5
5
5.25
V
5.25
V
VDD
Supply voltage
VDD*1
HPD and CAD output reference voltage
VCC
Supply voltage
3
TA
Operating free-air temperature
1.62
3.3
3.6
V
0
85
°C
0.15
1.40
V
2.7
Gbps
55
Ω
2
V
MAIN LINK DIFFERENTIAL PINS
VID
Peak-to-peak input differential voltage
dR
Data rate
Rt
Termination resistance
VOterm
Output termination voltage
45
50
0
TMDS DIFFERENTIAL OUTPUT PINS
AVCC
TMDS output termination voltage
dR
Data rate
Rt
Termination resistance
3
45
3.3
50
3.6
V
2.5
Gbps
55
Ω
AUXILIARY AND I2C PINS
VI
Input voltage
dR(AUX)
Auxiliary data rate
dR(I2C)
I2C data rate
0
5.25
V
1
MHz
100
kHz
HPD, CAD, AND CONTROL PINS
VIH
High-level input voltage
2
5.25
V
VIL
Low-level input voltage
0
0.8
V
6
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DEVICE POWER
The SN75DP122 is designed to operate off of two supply voltages. The DisplayPort port and the digital logic run
off of the 5V supply voltage. The TMDS level translator is powered off of the 3.3V supply.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply current
LP = 5 V, VDD*1 = VDD, Priority = 0 V
ML: VID = 600 mV, 2.7 Gbps PRBS
AUX: VID = 500 mV, 1 Mbps PRBS
DP/TMDS_HPD_SINK and CAD_SINK = 5 V
Supply current
LP = 5 V, VDD*1 = VDD, Priority = 1 V
ML: VID = 500 mV, 2.5 Gbps PRBS
AUX: VI = 2 V, 100 kHz
DP/TMDS_HPD_SINK and CAD_SINK = 5 V
IDD*1
Supply current
VDD*1 = 5.25 V
ISD
Shutdown current
LP = 0 V
IDD
ICC
IDD(2)
ICC(2)
MIN
TYP
MAX
60
65
0.1
0.25
2
4
80
110
UNIT
mA
mA
0.1
4
mA
1
16
µA
HOT PLUG AND CABLE ADAPTER DETECT
The SN75DP122 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals.
The SN75DP122 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD
and CAD pins is defined by the voltage level of the VDD*1 pin.
When the DisplayPort port is selected, the state of CAD_SINK is propagated to the CAD output pin. If the TMDS
port is selected, the CAD output pin stays HIGH as long as that port is selected.
Explanation of HPD and the internal logic of the SN75DP122 is located in the application section at the end of
the data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
High-level output voltage
IOH = –100 µA,
VOH3.3
High-level output voltage
IOH = –100 µA,
VOH2.5
High-level output voltage
IOH = –100 µA,
VOH1.8
High-level output voltage
IOH = –100 µA,
VOL
Low-level output voltage
IOH = 100 µA,
IH
High-level input current
VIH = 2.0 V,
IL
Low-level input current
VIL = 0.8 V,
VOH5
VDD*1 = 5 V
MIN
TYP
MAX
UNIT
4.5
5
V
VDD = 3.3 V
3
3.3
V
VDD*1 = 2.5 V
2.25
2.5
V
VDD*1 = 1.8 V
1.62
1.8
V
0
0.4
V
VDD = 5.25 V
–10
10
µA
VDD = 5.25 V
–10
10
µA
*1
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPD(CAD)
TEST CONDITIONS
VDD*1 = 5 V
Propagation delay
*1
MIN
TYP
MAX
5
30
UNIT
ns
tPD(HPD)
Propagation delay
VDD = 5 V
30
110
ns
tT1(HPD)
HPD logic switch pause time
VDD*1 = 5 V
2
4.7
ms
tT2(HPD)
HPD logic switch time
VDD*1 = 5 V
170
400
ms
tM(HPD)
Minimum output pulse duration
VDD*1 = 5 V
100
tZ(HPD)
Low power to high-level propagation delay
*1
VDD = 5 V
30
ns
50
110
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SN75DP122
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HPD Input
HPD Output
DP122
100 kW
100 kW
Figure 1. HPD Test Circuit
HPD_B
0V
HPD_A
VDD
Sink Hot Plug Detect
Pulse Duration
50%
0V
tPD(HPD)
VDD*1
HPD
Minimum
Hot Plug Detect
Output Pulse Duration
tm(HPD)
50%
0V
Figure 2. HPD Timing Diagram #1
8
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HPD_A & HPD_B
VDD
VDD
Priority
50%
0V
Sink Hot Plug Detect
Timeout
t2(HPD)
t1(HPD)
VDD*1
HPD
50%
0V
Port B
Selected
Port A
Selected
Figure 3. HPD Timing Diagram #2
HPD_B
0V
VDD
HPD_A
50%
0V
tZ(HPD)
VDD*1
HPD
50%
0V
Figure 4. HPD Timing Diagram #3
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SN75DP122
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DisplayPort Auxiliary Pins
The SN75DP122 is designed to support the bidirectional auxiliary signals through the DisplayPort port in both a
differential (DisplayPort) mode and an I2C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimized
based on the status of the CAD_SINK pin.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VPass1
Maximum passthrough voltage (CAD=1)
VDD = 4.5 V, VI = 5 V, IO = 100 µA
2.4
3.6
V
IOZ
Output current from unselected output
VDD = 5.25 V, VO = 0 V to 3.6 V, VI = 0 V
–5
5
µA
CIO(off)
I/O capacitance when in low power
DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz,
CAD = High
9
12
pF
CIO(on)
I/O capacitance when in normal operation
DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz,
CAD = Low
18
25
pF
rON(C0)
On resistance
VDD = 4.5 V, VI = 0 V or 3.6 V, IO = 5 mA, CAD = Low
5
10
Ω
ΔrON
On resistance
VDD = 4.5 V, VI = 0 V or 2 V, IO = 5 mA, CAD = Low
1
5
Ω
rON(C1)
On resistance
VDD = 4.5 V, VI = 0.4 V , IO = 3 mA , CAD = High
10
18
Ω
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tsk(AUX)
Intra-pair skew
VID = 400 mV, VIC = 2 V
IL(AUX)
Single Line Insertion Loss
VID = 500 mV, VIC = 2 V, F = 1 MHz, CAD = Low
tPLH(AUXC0)
Propagation delay time, low to high
tPHL(AUXC0)
tPLH(AUXC1)
tPHL(AUXC1)
TYP MAX
40
UNIT
80
ps
0.4
dB
CAD = Low, F = 1 MHz
3
ns
Propagation delay time, high to low
CAD = Low, F = 1 MHz
3
ns
Propagation delay time, low to high
CAD = High, F = 100 kHz
3
ns
Propagation delay time, high to low
CAD = High, F = 100 kHz
3
ns
3.3V
50 W
50 W
AUX+
10 pF
AUX-
0.5 pF
100 W
SN75DP122
CAD = 0
Figure 5. Auxiliary Channel Test Circuit (CAD = LOW)
3.3 V
2 kW
3.3 V
100 kW
SN75DP122
10 pF
AUX
+ or -
50 pF
CAD = 1
Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH)
10
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2.2 V
50%
1.8 V
Tsk(AUX)
Figure 7. Auxiliary Channel Skew Measurement
2.2 V
AUX Input
1.8 V
Differential
0V
AUX Input
tPHL(AUXCO)
Differential
AUX Output
tPLH(AUXCO)
0V
Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW)
3.6 V
AUX
Input
+ or -
1.8 V
0V
tPHL(AUXC1)
tPLH(AUXC1)
3.6 V
AUX
Output 1.8 V
+ or 0V
Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH)
DisplayPort Link Pins
The SN75DP122 is designed to support DisplayPort’s high speed differential main link through the DisplayPort
port. The main link I/O of the SN75DP122 are designed to track the magnitude and frequency characteristics of
the input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP122 to
increase the either increase of decrease the output amplitude via the resistor connected between the DPVADJ
pin and ground.
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
ΔVI/O(2)
PARAMETER
VID = 200 mV, DPVadj = 6.5 kΩ
0
30
60
mV
ΔVI/O(3)
VID = 300 mV, DPVadj = 6.5 kΩ
–24
11
36
mV
VID = 400 mV, DPVadj = 6.5 kΩ
–45
–15
15
mV
VID = 600 mV, DPVadj = 6.5 kΩ
–87
–47
–22
mV
45
50
55
Ω
2
V
ΔVI/O(4)
TEST CONDITIONS
Difference between input and output) voltages
(VOD – VID)
ΔVI/O(6)
RINT
Input termination impedance
VIterm
Input termination voltage
0
UNIT
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TYP
MAX
UNIT
tR/F(DP)
Output edge rate (20%–80%)
PARAMETER
Input edge rate = 80 ps (20%–80%)
TEST CONDITIONS
MIN
115
160
ps
tPD
Propagation delay time
F= 1 MHz, VID = 400 mV
227
tSK(1)
Intra-pair skew
F= 1 MHz, VID = 400 mV
tSK(2)
Inter-pair skew
F= 1 MHz, VID = 400 mV
tDPJIT(PP)
Peak-to-peak output residual jitter
dR = 2.7 Gbps, VID = 400 mV, PRBS 27-1
VIterm
ps
40
ps
35
ps
0 V to 2 V
50 W
50 W
50 W
Receiver
VID
50 W
0.5 pF
D+
VD+
25
ps
20
Driver
D-
Y
100 pF
VY
Z
VD-
100 pF
VZ
VID = VD+ - VD-
VOD = VY - VZ
VICM = (VD+ + VD-)
2
VOC = (VY + VZ)
2
Figure 10. Main Link Test Circuit
tR/FDP
Input
DVI/O
Output
Input Edge Rate
20% to 80%
80 ps
DVI/O
Figure 11. Main Link ΔVI/O and Edge Rate Measurements
12
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ML_IN x+
ML_IN x-
Main Link 0 V
Input
tPD(ML)
tPD(ML)
Main Link
Output
0V
Figure 12. Main Link Delay Measurements
2.2 V
ML x+
50%
1.8 V
ML xTsk1
Tsk2
2.2 V
ML y+
50%
1.8 V
ML yTsk1
Figure 13. Main Link Skew Measurements
TMDS I2C Pins
When the TMDS port is selected the SN75DP122 utilizes an I2C repeater. The repeater is designed to isolate the
parasitic effects of the system in order to aid with system level compliance.
In addition to the I2C repeater, the SN75DP122 also supports the connector detection I2C register. This register
is enabled via the I2C_EN pin. When active an internal memory register is readable via the AUX_I2C I/O. The
functionality of this register block is described in the application section
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
IL
Low input current
Ilkg(AUX)
Input leakage
TEST CONDITIONS
MIN
VCC = 3.6 V, VI = 0 V
AUX_I2C pins
VCC = 3.6 V, VI = 3.6 V
–10
TYP MAX
10
µA
10
µA
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Input/output capacitance
AUX_I2C pins
VIH(AUX)
High-level input voltage
AUX_I2C pins
1.6
VIL(AUX)
Low-level input voltage
AUX_I2C pins
–0.2
0.4
CIO(AUX)
2
DC bias = 1 V, AC = 1.4 Vp-p,
f = 100 kHz
15
UNIT
pF
V
V
VOL(AUX)
Low-level output voltage
AUX_I C pins
IO = 4 mA
0.5
0.6
V
Ilkg(I2C)
Input leakage current
I2C SDA/SCL pins
VCC = 3.6 V, VI = 4.95 V
–10
10
µA
CIO(I2C)
Input/output capacitance
I2C SDA/SCL pins
DC bias = 2.5 V,
AC = 3.5 Vp-p, f = 100 kHz
15
pF
VIH(I2C)
High-level input voltage
I2C SDA/SCL pins
2.1
VIL(I2C)
Low-level input voltage
I2C SDA/SCL pins
-0.2
VOL(I2C)
2
Low-level output voltage
I C SDA/SCL pins
V
IO = 4 mA
1.5
V
0.2
V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
MIN
TYP MAX
tPLH1
Propagation delay time, low to high
PARAMETER
Source to sink
TEST CONDITIONS
204
459
UNIT
ns
tPHL1
Propagation delay time, high to low
Source to sink
35
140
ns
tPLH2
Propagation delay time, low to high
Sink to source
80
251
ns
tPHL2
Propagation delay time, high to low
Sink to source
35
200
ns
tf1
Output signal fall time
Sink side
20
72
ns
tf2
Output signal fall time
Source side
20
72
ns
fSCL
SCL clock frequency for internal register
Source side
100
kHz
tW(L)
Clock LOW period for I2C register
Source side
4.7
µs
tW(H)
Clock HIGH period for internal register
Source side
4.0
µs
tSU1
Internal register setup time, SDA to SCL
Source side
250
ns
th(1)
Internal register hold time, SCL to SDA
Source side
0
µs
T(buf)
Internal register bus free time between STOP and START
Source side
4.7
µs
tsu(2)
Internal register setup time, SCL to START
Source side
4.7
µs
th(2)
Internal register hold time, START to SCL
Source side
4.0
µs
tsu(3)
Internal register hold time, SCL to STOP
Source side
4.0
µs
3.3 V
VCC
RL = 2 kW
PULSE
GENERATOR
D.U.T.
CL = 100 pF
RT
VIN
VOUT
Figure 14. Source Side Test Circuit (AUX_I2C)
14
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5V
VCC
RL = 2 kW
PULS
GENERATOR
D.U.T.
CL = 400 pF
RT
VIN
VOUT
Figure 15. Sink Side Test Circuit (SCL, SDA)
5V
I2C_SCL/
I2C_SDA
Input
1.6 V
0.1 V
tPHL2
tPLH2
3.3 V
80%
AUX_I2C (p)/
AUX_I2C (n)
Output
1.6 V
20%
VOL
tf1
Figure 16. Source Side Output AC Measurements
3.3 V
AUX_I2C (p)/
AUX_I2C (n)
Input
1.6 V
0.1 V
tPHL1
5V
80%
I2C_SCL/
I2C_SDA
Output
1.6 V
20%
VOL
tf1
Figure 17. Sink Side Output AC Measurements
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3.3 V
AUX_I2C (p)/
AUX_I2C (n)
Input
0.5 V
tPHL1
5V
I2C_SCL/
I2C_SDA
Output
1.6 V
Figure 18. Sink Side Output AC Measurements Continued
TMDS MAIN LINK PINS
The TMDS port of the SN75DP122 is designed to be compliant with the Digital Video Interface (DVI) 1.0 and
High Definition Multimedia Interface (HDMI) 1.3 specifications. The differential output voltage swing can be fine
tuned with the VSadj resistor.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Single-ended HIGH level output voltage
AVCC –10
AVCC+10
mV
VOL
Single-ended LOW level output voltage
AVCC –600
AVCC –400
mV
VSWING
Single-ended output voltage swing
400
600
mV
VOC(SS)
Change in steady-state common-mode output
voltage between logic states
–5
5
mV
VOD(PP)
Peak-to-Peak output differential voltage
AVCC = 3.3 V, RT = 50 Ω
800
1200
mV
AVCC –10
AVCC+10
mV
V(O)SBY
Single-ended standby output voltage
AVCC = 3.3 V, RT = 50 Ω,
DP Port Selected
I(O)OFF
Single-ended power down output current
0 V ≤ VCC ≤ 1.5 V ,
AVCC = 3.3 V, RT = 50 Ω
–10
10
µA
IOS
Short circuit output current
VID = 500 mV
–15
15
mA
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time
250
480
600
ps
tPHL
Propagation delay time
250
400
800
ps
tR
Rise time
60
90
140
ps
tF
Fall time
60
90
140
ps
tSK(P)
Pulse skew
8
15
ps
tSK(D)
Intra-pair skew
20
40
ps
tSK(O)
Inter-pair skew
20
65
ps
tJITD(PP)
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50 Ω, dR = 2.5 Gbps
20
50
ps
tJITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, RT = 50 Ω, f = 250 MHz
10
30
ps
16
AVCC = 3.3 V, RT = 50 Ω, f = 1 MHz
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VTERM
3.3 V
50 W
50 W
50 W
50 W
0.5 pF
D+
100 pF
VD+
Receiver
VID
Y
Driver
VY
D-
100 pF
VD-
Z
VID = VD+ - VD-
VOD = VY - VZ
VICM = (VD+ + VD-)
2
VOC = (VY + VZ)
2
VZ
Figure 19. TMDS Main Link Test Circuit
2.2 V
VTERM
VID
1.8 V
VID+
VID(pp)
0V
VID
tPHL
80%
tPLH
80%
VOD(pp)
VOD
0V
20%
tf
20%
tr
Figure 20. TMDS Main Link Timing Measurements
VOC
DVOC(SS)
Figure 21. TMDS Main Link Common Mode Measurements
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AVCC (4)
RT
Data +
Video Data Patterm
Generator
Coax
Coax
SMA
SMA
RX
+EQ
SMA
FR4 PCB trace (1) &
AC coupling Caps
1000 mVpp
Differential
Clk +
Clk -
Coax
Coax
OUT
SN75DP122
SMA
Coax
Jitter Test
Instrument (2,3)
AVcc
RT RT
SMA
SMA
Coax
FR4 PCB trace
SMA
RX
+EQ
RT (5)
OUT
SMA
Coax
Coax
Jitter Test
Instrument (2,3)
TTP 1
TTP 2
TTP 4
TTP 3
(1)
The FR4 trace between TTP1 and TTP2 is designed to emulate 8" of FR4, a connector, and another 8" of FR4.
(2)
All Jitter is measured at a BER of 10–12
(3)
Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1
(4)
AVCC = 3.3 V
(5)
RT = 50 Ω
Figure 22. TMDS Jitter Measurements
50 W
IOS
Driver
50 W
+ 0 V or 3.6 V
-
Figure 23. TMDS Main Link Short Circuit Output Circuit
18
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TYPICAL CHARACTERISTICS
INPUT/OUTPUT VOLTAGE
vs
DPVadj RESISTANCE
INPUT/OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
40
150
DVI\O − Input/Output Voltage − mV
DVI\O − Input/Output Voltage − mV
30
VID = 200 mV
100
VID = 300 mV
50
0
VID = 400 mV
−50
VID = 600 mV
−100
VID = 300 mV
10
0
VID = 400 mV
−10
−20
−30
VID = 600 mV
−40
Temp = 25oC
−60
4.4
−150
2k
20
−50
Temp = 25oC
0
VID = 200 mV
4k
6k
8k
10k
12k
14k
4.5
4.7
4.8
4.9
5
5.1 5.2 5.3 5.4
VDD − Differential Voltage − V
DPVadj − Resistance − W
Figure 24.
Figure 25.
OUTPUT RISE TIME
vs
INPUT RISE TIME
POWER DISSIPATION
vs
DATA RATE
500
200
VDD = 5.25 V
180
450
160
Power Dissipation − mW
Output Rise Time 20% - 80% (ps)
4.6
140
120
VDD = 5 V
100
VDD = 4.5 V
80
60
40
TMDS
400
350
300
Display Port
250
20
200
0
0
20
40
60
80
100
120 140 160
0
180
Figure 26.
500M
1G
1.5G
2G
2.5G
3G
Data Rate − Bps
Input Rise Time 20% - 80% (ps)
(1)
TMDS power dissipation in this graph includes
132 mW of power supplied by the AVCC
termination.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
TMDS PORT SUPPLY VOLTAGE
vs
RESIDUAL DATA JITTER
TMDS PORT JITTER
vs
DATA RATE
25
15
13
Peak-Peak Residual Data Jitter (ps)
Peak-Peak Residual Data Jitter (ps)
14
25oC
12
0oC
11
10
85oC
9
8
7
VID = 600 mV
20
VID = 400 mV
15
10
VID = 500 mV
5
6
5
2.7
3
3.3
3.6
0
500M
3.9
1G
1.5G
2G
2.5G
3G
Data Rate − Bps
VCC − Supply Voltage − V
Figure 28.
Figure 29.
TMDS OUTPUT DIFFERENTIAL VOLTAGE
vs
VSadj RESISTANCE
VOD − Differential Output Voltage − mV
1400
3.6 V, VCC
1200
3.3 V, VCC
1000
3 V, VCC
800
600
400
200
0
3k
3.5k
4k
4.5k
5k
5.5k
6k
6.5k
7k
VSadj − Resistance − W
Figure 30.
20
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APPLICATION INFORMATION
SWITCHING LOGIC
The Switching logic of the SN75DP122 is tied to the state of the HPD pins as well as the LP and priority pins.
When both HPD_A and HPD_B input pins are LOW, the SN75DP122 enters the low power state. In this state the
outputs are high impedance. When either HPD_A or HPD_B goes high, the device enters the normal operational
state and the port associated with the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH,
the port selection is determined by the state of the priority pin.
In order to ease the transitioning from one output port to the other output port the SN75DP122 forces the HPD
output pin LOW for an extended duration. This forced Low is designed to mimic an unplug event for the
transmitting device. This should allow for a smooth transition from one port to another. This forced LOW timer
can be bypassed by pulsing the LP pin LOW for a short duration and then returning to HIGH. When the LP pin if
driven LOW the device enters a low power state and the internal logic block is reset.
I2C INTERFACE NOTES
The I2C interface can be used to access the internal memory of the SN75DP122. I2C is a two-wire serial
interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The SN75DP122 works as a slave and supports the standard mode
transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I2C-Bus Specification.
The basic I2C start and stop access cycles are shown in Figure 31.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SDA
SCL
SCL
Start
Condition
Stop
Condition
Figure 31. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 31. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 32). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 33) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
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•
•
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 34).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 32. I2C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
Clock Pulse for
Acknowledgement
START
Condition
Figure 33. I2C Acknowledge
SCL
SDA
Stop
MSB
Acknowledge
Acknowledge
Data
Slave Address
2
Figure 34. I C Address and Data Cycles
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
22
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address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 35 and Figure 36.
See Example – Reading from the SN75DP122 section for more information.
Figure 35. I2C Read Cycle
Start
Condition
Acknowledge
(From
Receiver)
Not
Acknowledge
(Transmitter)
Acknowledge
(From
Transmitter)
SDA
I2C Device Address and
Read/Write Bit
First Data
Byte
Other
Data Bytes
Stop
Condition
Last Data Byte
Figure 36. Multiple Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 1000000. Table 2 lists the calls that the SN75DP122 responds to.
Table 2. SN75DP122 Slave Address
FIXED ADDRESS
READ/WRITE BIT
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(R/W)
1
0
0
0
0
0
0
1
Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)
The SN75DP122 operates using a multiple byte transfer protocol similar to Figure 36. The internal memory of the
SN75DP122 contains the phrase DP-HDMI ADAPTOR converted to ASCII characters. The internal
memory address registers and the value of each can be found in Table 3.
During a read cycle, the SN75DP122 sends the data in its selected sub-address in a single transfer to the master
device requesting the information. See the Example – Reading from the SN75DP122 section of this document
for the proper procedure on reading from the SN75DP122.
Table 3. SN75DP122 Sink Port and Source Plug-In Status Registers Selection
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Data
44
50
2D
48
44
4D
49
20
41
44
41
50
54
4F
52
04
FF
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EXAMPLE – READING FROM THE SN75DP122
The read operation consists of several steps. The I2C master begins the communication with the transmission of
the start sequence followed by the slave address of the SN75DP122. The SN75DP122 acknowledges its
presence to the master and begin to transmit the contents of the memory registers. After each byte is transferred
the SN75DP122 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master. If an
ACK is received, the next byte of data is transmitted. If a NACK is received the data transmission sequence is
expected to end and the master should send the stop command.
The SN75DP122 continues to send data as long as the master continues to acknowledge each byte
transmission. If an ACK is received after the transmission of byte 0x0F, the SN75DP122 transmits byte 0x10 and
continue to transmit byte 0x10 for all further ACK’s until a NACK is received.
SN75DP122 Read Phase:
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
1
0
0
0
0
0
0
1
Step 3
9
I2C Acknowledge (Slave)
A
Step 10
I2C Read Data (Slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the logic values contained in the Sink port register
Step 11
9
2
I C Not-Acknowledge (Master)
X
Where X is either an A (Acknowledge) or A (Not-Acknowledge)
An A causes the pointer to increment and step 10 is repeated
An A causes the slave to stop transmitting and proceed to step 12
Step 12
0
I2C Stop (Master)
P
SWITCHING LOGIC
The switching logic of the SN75DP122 is tied to the state of the HPD input pins as well as the priority pin and low
power pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP122 enters the low power state. In
this state the outputs are high impedance, and the device is shutdown to optimize power conservation. When
either HPD_A or HPD_B goes high, the device enters the normal operational state, and the port associated with
the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection is determined by
the state of the priority pin.
Several key factors were taken into consideration with this digital logic implementation of channel selection as
well as HPD repeating. This logic has been divided into the following four scenarios.
1. Low power state to active state. There are two possible cases for this scenario depending on the state of the
low power pin:
– Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initial
state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device
remains in the low power mode with both the main link and auxiliary I/O in a high impedance state.
However, the port associated with the HPD input that went HIGH is still selected and the HPD output to
the source is enabled and follows the logic state of the input HPD (see Figure 37). The state of the
Priority pin has no effect in this scenario as only one HPD input port is active.
24
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SN75DP122
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
HI-Z
Channel A
0
1
HI-Z
Channel B
0
Figure 37.
– Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initial
state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device
comes out of the low power mode and enters active mode enabling the main link and auxiliary I/O. The
port associated with the HPD input that went HIGH is selected and the HPD output to the source is
enabled and follows the logic state of the input HPD (see Figure 38). This is specified as tZ(HPD). Again,
the state of the Priority pin has no effect in this scenario as only one HPD input port is active.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
HI-Z
Channel A
DATA
0
1
HI-Z
Channel B
0
Figure 38.
2. HPD Changes on the selected port. There are also two possible starting cases for this scenario:
– Case one: In this case only one HPD input is initially HIGH. The HPD output logic state follows the state
of the HPD input. If the HPD input pulses LOW, as may be the case if the Sink device is requesting an
interrupt, the HPD output to the source also pulses LOW for the same duration of time with a slight delay
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25
SN75DP122
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(see Figure 39). The delay of this signal through the SN75DP122 is specified as tPD(HPD). If the duration of
the LOW pulse is less then tM(HPD), it may not be accurately repeated to the source. If the duration of the
LOW pulse exceeds tT2(HPD), the device assumes that an unplug event has occurred and enters the low
power state (see Figure 40). Once the HPD input goes high again, the device returns to the active state
as indicated in scenario 1. The state of the Priority pin has no effect in this scenario as only one HPD
input port is active.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 39.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
HI-Z
0
1
HI-Z
Channel B
0
Figure 40.
– Case two: In this case both HPD inputs are initially HIGH and the selected port has been determined by
the state of the priority pin. The HPD output logic state follows the state of the selected HPD input. If the
HPD input pulses LOW, the HPD output to the source also pulses LOW for the same duration of time,
again with a slight delay (see Figure 41). If the duration of the LOW pulse exceeds tT2(HPD), the device
assumes that an unplug event has occurred and the other port is selected (see Figure 42). The case in
26
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which the previously selected port with priority goes high again is covered in scenario 3.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 41.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 42.
3. One channel becomes active while other channel is already selected. There are also two possible starting
cases for this scenario:
– Case one: In this case the HPD input that is initially HIGH is from the port that has priority. Since the port
with priority is already selected, any activity on the HPD input from the other port does not have any
effect on the switch whatsoever (see Figure 43).
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SN75DP122
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1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 43.
– Case two: In this case the HPD input that is initially HIGH is not the port with priority. When the HPD input
of the port that has priority goes high, the HPD output is forced LOW for some time in order to simulate
an unplug event to the source device. The duration of this LOW output is defined as tT2(HPD). If the HPD
input of the port with priority pulses LOW for a short duration while the tT2(HPD) timer is counting down, the
timer is reset. Once this time has passed the switch switches to the port with priority and the output HPD
once again follows the state of the newly selected channel’s HPD input (see Figure 44).
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 44.
4. 4. Priority pin is toggled. There are also two possible starting cases for this scenario:
– Case one: In this case only one HPD input is HIGH. A port whose HPD input is LOW cannot be selected.
In this case, the state of the priority pin has no effect on the switch (see Figure 45).
28
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Product Folder Link(s): SN75DP122
SN75DP122
www.ti.com......................................................................................................................................... SLLS892A – FEBRUARY 2008 – REVISED NOVEMBER 2008
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
DATA
Channel A
0
1
HI-Z
Channel B
0
Figure 45.
– Case two: In this case both HPD inputs are HIGH. Changing the state of the priority pin when both HPD
inputs are high forces the device to switch which channel is selected. When a state change is detected on
the priority pin, the device waits for a short period of time tT1(HPD) before responding (see Figure 46). The
purpose for this pause is to allow for the priority signal to settle and also to allow the device to ignore
potential glitches on the priority pin. Once tT1(HPD) has expired, the HPD output is forced LOW for tT2(HPD)
and the device follows the chain of events outlined in scenario 3 case 2.
1
LP
0
1
Priority
0
1
HPD_A
0
1
HPD_B
0
HPD_OUT
1
Z
0
1
Channel A
DATA
HI-Z
HI-Z
DATA
0
1
Channel B
0
Figure 46.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN75DP122RTQT
NRND
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
75DP122
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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