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SN65DPHY440SS, SN75DPHY440SS
SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
SNx5DPHY440SS CSI-2/DSI DPHY Re-timer
1 Features
3 Description
•
•
•
The DPHY440 is a one to four lane and clock MIPI
DPHY re-timer that regenerates the DPHY signaling.
The device complies with MIPI DPHY 1.1 standard
and can be used in either a MIPI CSI-2 or MIPI DSI
application at datarates of up to 1.5 Gbps.
1
•
•
•
•
•
•
•
•
•
•
•
•
MIPI DPHY 1.1 Specification compliant
Enables low-cost cable solutions
Supports up to 4 lanes at 1.5 Gbps
– CSI-2/DSI Clock rates
from 100 MHz To 750 MHz
Sub mW Power in shutdown state
MIPI DSI Bi-directional LP mode supported
Supports for both ULPS and LP power states
Adjustable output voltage swing
Selectable TX Pre-emphasis levels
Adjustable Rx EQ to compensate for ISI loss
Configurable edge rate control
Dynamic data and clock skew compensation
3-kV ESD HBM protection
Industrial temperature range: –40°C to 85°C
(SN65DPHY440SS)
Commercial temperature range: 0°C to 70°C
(SN75DPHY440SS)
Available in single 1.8-Vlpply
2 Applications
•
•
•
•
The device compensates for PCB, connector, and
cable related frequency loss and switching related
loss to provide the optimum electrical performance
from a CSI2/DSI source to sink. The DPHY440’s
DPHY inputs feature configurable equalizers.
The output pins automatically compensate for uneven
skew between clock and data lanes received on its
inputs ports. The DPHY440 output voltage swing and
edge rate can be adjusted by changing the state of
the VSADJ_CFG0 pin and ERC pin respectively.
The DPHY440 is optimized for mobile applications,
and contains activity detection circuitry on the DPHY
Link interface that can transition into a lower power
mode when in ULPS and LP states.
The SN65DPHY440SS is characterized for an
industrial temperature range from -40ºC to 85ºC while
SN75DPHY440SS is characterized for commercial
temperature range from 0ºC to 70ºC.
(1)
Device Information
Notebook PC
Clam lhell
Tablets
Camera
PART NUMBER
SN65DPHY440SS
SN75DPHY440SS
PACKAGE
WQFN (28)
BODY SIZE (NOM)
3.50 mm x 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Camera
(CSI-2 Source)
Typical Application
APU
(CSI-2 Sink)
DPHY440
CSI TX
SDA
EQ
Vio
ERC
PRE_CFG1
CSI Slave
SCL
CSI RX
CSI0P/N
CSI1P/N
CSICP/N
CSI2P/N
CSI3P/N
DB0P/N
DB1P/N
DBCP/N
DB2P/N
DB3P/N
DA0P/N
DA1P/N
DACP/N
DA2P/N
DA3P/N
VSADJ_CFG0
CSI0P/N
CSI1P/N
CSICP/N
CSI2P/N
CSI3P/N
CSI Master
SCL
SDA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65DPHY440SS, SN75DPHY440SS
SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics, Power Supply ................. 7
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
7.5 Register Maps ......................................................... 15
8
Application and Implementation ........................ 21
8.1 Application Information, ......................................... 21
8.2 Typical Application, CSI-2 Implementations ........... 21
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision B (August 2017) to Revision C
•
Page
Changed F(BR) MAX value From: 1 Gbps To: 1.5 Gbps in the Switching Characteristics table ............................................. 9
Changes from Revision A (April 2016) to Revision B
Page
•
Changed Feature From: CSI-2/DSI Clock Rates From 100 MHz to 500 MHz To: CSI-2/DSI Clock Rates From 100
MHz to 750 MHz .................................................................................................................................................................... 1
•
Changed text in the Description From: MIPI DSI application at datarates of up to 1 Gbps. To: MIPI DSI application
at datarates of up to 1.5 Gbps................................................................................................................................................ 1
•
Changed VIH = 4 dB To: VIH = 5 dB in the Pin Functions table .............................................................................................. 4
•
Added a Test Condition of EQ is at 750 MHz to V(RXEQ1) n the Electrical Characteristics table ............................................ 7
•
Changed V(RXEQ2) TYP value From: 4 dB To: 5 dB in the Electrical Characteristics table .................................................... 7
•
Changed the MIPI DPHY HS Interface section in the Timing Requirements table................................................................ 8
•
Changed F(HSCLK) From 500 µsMHz To: 750 MHz in the Switching Characteristics table ..................................................... 9
•
Changed F(DESKEW) from 500 MHz To: 750 MHz. .................................................................................................................. 9
•
Changed tR and tF Datarate Test Conditions and values ...................................................................................................... 9
•
Changed text From: application at datarates of up to 1 Gbps To: application at datarates of up to 1.5 Gbps in the
Overview section .................................................................................................................................................................. 11
•
Changed Table 1 ................................................................................................................................................................. 12
•
Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_CLK in Table 8 ............................................................................................ 17
•
Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_DATA in Table 8 ......................................................................................... 17
•
Changed From: Data Rate To: Data Rate (200 Mbps to 1.5 Gbps) in Table 15.................................................................. 22
2
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Product Folder Links: SN65DPHY440SS SN75DPHY440SS
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SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
Changes from Original (March 2016) to Revision A
Page
•
Changed Features From: 3-kV ESD HBM Protection To: 2-kV ESD HBM Protection........................................................... 1
•
Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 13 and 14.................................................... 4
•
Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 26, 27, and 28............................................. 5
•
Changed ESD Ratings values. HBM From: ±2000 To: ±3000, and CDM Form: ±500 To: ±1000 ........................................ 6
•
Changed V(RXEQ2) TYP value From: 5 dB To: 4 dB in the Electrical Characteristics table .................................................... 7
•
Added MIN and MAX values to |VOD(VD0)|, |VOD(VD1)|, and |VOD(VD2)| in the Electrical Characteristics table ............................ 7
•
Deleted rows ZOS and ΔZOS from the Electrical Characteristics table .................................................................................... 8
•
Updated the MIPI DPHY LP Transmitter Interface section of the Switching Characteristics table ........................................ 9
•
Changed 5 dB to 4 dB in HS Receive Equalization and Table 1 ........................................................................................ 12
•
Changed 11 – 4 dB To: 11 – 5 dB in Table 8 ..................................................................................................................... 17
Copyright © 2016–2019, Texas Instruments Incorporated
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3
SN65DPHY440SS, SN75DPHY440SS
SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
www.ti.com
5 Pin Configuration and Functions
RSTN
VSADJ_CFG0
PRE_CFG1
VDD
28
27
26
25
RHR Package
28 Pin (WQFN)
Top View
DA0P
1
24
DB0P
DA0N
2
23
DB0N
DA1P
3
22
DB1P
DA1N
4
21
DB1N
DACP
5
20
DBCP
DACN
6
19
DBCN
DA2P
7
18
DB2P
DA2N
8
17
DB2N
DA3P
9
16
DB3P
DA3N
10
15
DB3N
Thermal
11
12
13
14
VCC
VREG_OUT
EQ/SCL
ERC/SDA
Pad
Pin Functions
PIN
NAME
NO.
DA0P
1
DA0N
2
DA1P
3
DA1N
4
DACP
5
DACN
6
DA2P
7
DA2N
8
DA3P
9
DA3N
I/O
INTERNAL
PULLUP/PULLDOWN
DESCRIPTION
CSI-2/DSI Lane 0 Differential positive Input. Supports DSI LP Backchannel.
If unused, this pin should be tied to GND.
100-Ω
Differential
Input
CSI-2/DSI Lane 0 Differential negative Input. Supports DSI LP Backchannel.
If unused, this pin should be tied to GND.
100-Ω
Differential
Input
(Failsafe)
CSI-2/DSI Lane 1 Differential positive Input. If unused, this pin should be
tied to GND.
100-Ω
Differential
Input
(Failsafe)
CSI-2/DSI Differential Clock positive Input
100-Ω
Differential
Input
(Failsafe)
CSI-2/DSI Lane 2 Differential positive Input. If unused, this pin should be
tied to GND.
CSI-2/DSI Lane 3 Differential positive Input. If unused, this pin should be
tied to GND.
10
100-Ω
Differential
Input
(Failsafe)
VCC
11
Power
1.8V (±10%) Supply.
VREG_OUT
12
Power
1.2 V Regulator Output. Requires a 0.1 µF capacitor to GND.
13
I/O
(3-level)
EQ/SCL
ERC/SDA
4
14
I/O
(3-level)
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CSI-2/DSI Lane 1 Differential negative input. If unused, this pin should be
tied to GND.
CSI-2/DSI Differential Clock negative Input
CSI-2/DSI Lane 2 Differential negative Input. If unused, this pin should be
tied to GND.
CSI-2/DSI Lane 3 Differential negative Input. If unused, this pin should be
tied to GND.
PU (100K)
PD (100K)
RX Equalization Select. Pin state sampled on rising edge of RSTN. This pin
also functions as I2C SCL pin.
VIL = 0 dB
VIM = 2.5 dB
VIH = 5 dB
PU (100K)
PD (100K)
Edge Rate Control for DB[4:0]P/N High speed transmitter rise and fall time.
Pin state sampled on rising edge of RSTN. This pin also functions as I2C
SDA pin.
VIL = 200 ps typical
VIM = 150 ps typical
VIH = 250 ps typical
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: SN65DPHY440SS SN75DPHY440SS
SN65DPHY440SS, SN75DPHY440SS
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SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
Pin Functions (continued)
PIN
I/O
NAME
NO.
DB3N
15
DB3P
16
DB2N
17
DB2P
18
DBCN
19
DBCP
20
DB1N
21
DB1P
22
DB0N
23
DB0P
24
100-Ω
Differential
Output
VDD
25
Power
26
I/O
(3-level)
PRE_CFG1
INTERNAL
PULLUP/PULLDOWN
DESCRIPTION
CSI-2/DSI Lane 3 Differential negative Output. If unused, this pin should be
left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Lane 3 Differential positive Output. If unused, this pin should be
left unconnected.
CSI-2/DSI Lane 2 Differential negative Output. If unused, this pin should be
left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Lane 2 Differential positive Output. If unused, this pin should be
left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Differential Clock negative Output
CSI-2/DSI Differential Clock positive Output
CSI-2/DSI Lane 1 Differential negative Output. If unused, this pin should be
left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Lane 1 Differential positive Output. If unused, this pin should be
left unconnected.
CSI-2/DSI Lane 0 Differential negative Output. Supports DSI LP Back
channel. If unused, this pin should be left unconnected.
CSI-2/DSI Lane 0 Differential positive Output. Supports DSI LP Back
channel. If unused, this pin should be left unconnected.
This pin must be connected to the VREG_OUT pin through at least a 10-mil
trace and a 0.1 µF capacitor to ground.
PU (100K)
PD (100K)
Controls DPHY TX HS pre-emphasis level and the LP TX rise and fall times.
Pin state is sampled on the rising edge of RSTN.
VIL = 0 dB
VIM = 0 dB
VIH = 2.5 dB
VSADJ_CFG0
27
I
(3-level)
PU (100K)
PD (100K)
Controls output voltage swing for DB HS transmitters and the LP TX rise
and fall times. Pin state is sampled on the rising edge of RSTN. Refer to
Table 3 for details on voltage swing settings based on this pin and
PRE_CFG1 sampled state.
VIL = 200 mV or 220 mV based on PRE_CFG1 sampled state.
VIM = 200 mV typical
VIH = 220 mV typical
RSTN
28
I
PU (300K)
Reset, active low. When low, all internal CSR are reset to default and
DPHY440 is placed in low power state.
GND
Thermal pad
GND
Copyright © 2016–2019, Texas Instruments Incorporated
Ground.
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SN65DPHY440SS, SN75DPHY440SS
SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
Voltage range
(1)
MIN
MAX
UNIT
VCC
–0.3
2.175
V
DPHY Lane I/O Differential Voltage
–0.3
1.4
V
RSTN
–0.3
2.175
V
All other terminals
–0.3
2.175
V
105
°C
150
°C
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
±1000
(2)
(1)
(2)
UNIT
±3000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
TA
MIN
NOM
MAX
UNIT
Supply voltage
1.62
1.8
1.98
V
Operating free-air temperature [SN65DPHY440SS]
–40
85
Operating free-air temperature [SN75DPHY440SS]
0
70
°C
6.4 Thermal Information
SNx5DPHY440SS
THERMAL METRIC
(1)
RHR (WQFN)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
42.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.3
°C/W
RθJB
Junction-to-board thermal resistance
12.8
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
12.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.2
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
6.5 Electrical Characteristics, Power Supply
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
PACTIVE1_SS
Power under normal operation for 4 data
lanes + clock.
DPHY Lanes at 1 Gbps; VCC supply stable,
VCC = 1.8 V;
150
mW
PACTIVE2_SS
Power under normal operation for 2 data
lanes + clock.
DPHY Lanes 1 Gbps; VCC supply stable,
VCC = 1.8 V;
115
mW
PLP11_SS
LP11 Power
All DPHY lanes in LP11; VCC supply stable;
VCC = 1.8 V;
14
mW
PRSTN_SS
RSTN Power
RSTN held in asserted state (low); VCC
supply stable; VCC = 1.8 V;
0.75
mW
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standard IO (RSTN, ERC, EQ, CFG[1:0])
VIL
Low-level control signal input voltage
VIM
Mid-level control signal input voltage
0.2 x VCC
VIH
High-level control signal input voltage
VF
Floating Voltage
VIN = High Impedance
VOL
Low level output voltage (open-drain).
ERC (SDA) only
At IOL max.
IOL
Low Level Output Current
3
mA
IIH
High level input current
±36
µA
IIL
Low level input current
±36
µA
RPU
Internal pull-up resistance
100
kΩ
RPD
Internal pull-down resistance
100
kΩ
R(RSTN)
RSTN control input pullup resistor
300
kΩ
VCC / 2
V
V
0.8 x VCC
V
VCC / 2
V
0.2 x VCC
V
MIPI Input Leakage (DA1P/N, DA2P/N, DA3P/N, DACP/N)
Ilkg
Input failsafe leakage current
VCC = 0 V; VDD = 0 V; MIPI DPHY pulled
up to 1.35 V
–65
65
µAV
330
mV
MIPI DPHY HS RECIEVER INTERFACE (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)
V(CM-RX_DC)
Differential Input Common-mode voltage
HS Receive mode
V(CM-RX) = (VA x P + VA x N)/2
70
| VID |
HS Receiver input differential voltage
| VID | = |VA x P – VA x N|
70
VIH(HS)
Single-ended input high voltage
VIL(HS)
Single-ended input low voltage
R(DIFF-HS)
Differential input impedance
V(RXEQ0)
Rx EQ gain when EQ/SCL pin ≤ VIL
0
dB
V(RXEQ1)
Rx EQ gain when EQ/SCL pin = VIM
At 750 MHz
2.5
dB
V(RXEQ2)
Rx EQ gain when EQ/SCL pin ≥ VIH
At 750 MHz
5
dB
mV
460
–40
80
mV
mV
100
125
Ω
MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)
V(LPIH)
LP Logic 1 Input Voltage
V(LPIL)
LP Logic 0 Input voltage
V(HYST)
LP Input Hysteresis
880
mV
550
25
mV
mV
MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)
V(CMTX)
HS Transmit static common-mode
voltage
V(CMTX) = (V(BP) + V(BN)) / 2
|∆V(CMTX) (1,0)|
VCMTX mismatch when output is
Differential-1 or differential-0.
∆V(CMTX) (1,0) = (V(CMTX) (1) – V(CMTX) (0)) /2
|VOD(VD0)|
HS Transmit differential voltage for
CFG0 = 2’b00 with TX pre-emphasis
disabled or for non-transition bit when
TX pre-emphasis is enabled.
|VOD| = |V(DP) - V(DN)|
140
|VOD(VD1)|
HS Transmit differential voltage for
CFG0 = VIM with TX pre-emphasis
disabled or for non-transition bit when
TX pre-emphasis is enabled.
|VOD| = |V(DP) - V(DN)| CFG0 = VIM
160
Copyright © 2016–2019, Texas Instruments Incorporated
150
200
300
mV
5
mV
180
220
mV
200
250
mV
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
170
220
270
mV
14
mV
430
mV
|VOD(VD2)|
HS Transmit differential voltage for
CFG0 = VIH with TX pre-emphasis
disabled or for non-transition bit when
pre-emphasis is enabled..
|VOD| = |V(DP) - V(DN)| CFG0 ≥ VIH
|∆VOD|
VOD mismatch when output is
differential-1 or differential-0.
∆VOD = |∆VO(D1)| - |∆VO(D0)|
VOH(HS)
HS Output high voltage for nontransition bit.
CFG0 ≥ VIH HS Pre = 2.5 dB
V(PRE1)
Pre-emphasis Level for HSTX_PRE =
2’b00.. Refer to Figure 3
PRE = 20 x LOG (VOD(TBx) / VOD(VDX))
1.5
dB
V(PRE2)
Pre-emphasis level for HSTX_PRE =
2’b1X. Refer to Figure 3
PRE = 20 x LOG (VOD(TBx) / VOD(VDX))
2.5
dB
MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)
V(LPOH)
LP Output High Level
1.1
V(LPOL)
LP Output Low Level
–50
VIH(CD)
LP Logic 1 contention threshold
450
VIL(CD)
LP Logc 0 contention threshold
ZO(LP)
Output Impedance of LP transmitter
1.2
1.3
V
50
mV
mV
200
mV
110
Ω
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
I2C (ERC (SDA), EQ (SCL))
tHD;STA
Hold Time (repeated) START condition. After this period, the first clock pulse is generated
4
µs
tLOW
Low period of SCL clock
4.7
µs
tHIGH
High period of SCL clock
4
µs
tSU;STA
Setup time for a repeated START condition
4.7
µs
tHD;DAT
Data hold time
5
µs
tSU;DAT
Data setup time
4
µs
tSU;STO
Setup time for STOP condition
4
µs
tBUF
Bus free time between a STOP and START condition
4.7
µs
MIPI DPHY HS Interface
tHSPD
Propagation delay from DA to DB.
4 + 12ns
4 + 40ns
UI
–5
5
%
0.1
UI
tDBC_DCYCLE
DAC to DBC output duty cycle distortion percentage
750 MHz clock with 50%-50%
duty cycle at DAC input.
tSKEW-TX-1G
Data to Clock variation from 0.5UI. Refer to Figure 2
Datarate ≤ 1 Gbps
–0.1
tSETUP-RX-1G
Data to Clock setup time. Refer to Figure 2
Datarate ≤ 1 Gbps
0.1
tHOLD-RX-1G
Clock to data hold time. Refer to Figure 2
Datarate ≤ 1 Gbps
0.1
tSKEW-TX-1P5G Data to Clock variation from 0.5UI. Refer to Figure 2
Datarate > 1 Gbps
–0.15
tSETUP-RX-
Datarate > 1 Gbps
0.15
UI
Datarate > 1 Gbps
0.15
UI
Data to Clock setup time. Refer to Figure 2
UI
UI
0.15
UI
1P5G
tHOLD-RX-1P5G Clock to data hold time. Refer to Figure 2
8
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SLLSEO9C – MARCH 2016 – REVISED AUGUST 2019
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
MAX
UNIT
100
kHz
300
ns
1000
ns
I2C (ERC (SDA), EQ (SCL))
F(SCL)
I2C Clock Freqency
tF_I2C
Fall time of both SDA and SCL signals
tR_I2C
Rise Time of both SDA and SCL signals
Load of 350 pF with 2-K pullup
resistor.
Measure at 30% - 70%
DPHY LINK
F(BR)
Bit Rate
1.5
Gbps
F(HSCLK)
HS Clock Input range
100
750
MHz
F(DESKEW)
Automatic Deskew range
220
750
MHz
100
mV
50
mV
MIPI DPHY HS Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)
∆V(CMRX_HF)
Common-mode Interface beyond 450 MHz
∆V(CMRX_LF)
Common-mode interference 50 MHz – 450 MHz
–50
MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)
∆V(CMRX_HF)
Common-level variations above 450 MHz
∆V(CMRX_LF)
Common-level variation between 50 MHz – 450 MHz.
tR and tF
20% - 80% rise time and fall time
5
mVrms
25
mVpeak
Datarate ≤ 1 Gbps
0.3
UI
Datarate > 1 Gbps
0.35
UI
100
ps
MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)
eSPIKE
Input Pulse rejection
tMIN(RX)
Minimum pulse width response
V(INT)
Peak interference amplitude
F(INT)
Interference Frequency
t(LP-PULSE-RX)
300
V ps
200
mv
20
Pulse Width of the XOR of DAxP and
DAxN
ns
450
Mhz
First LP XOR clock pulse after Stop
state or last pulse before Stop
state.
42
ns
All other pulses.
22
ns
MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)
tREOT
30% - 85% rise time and fall time
t(LP-PULSE-TX)
Pulse Width of the LP XOR clock
t(LP-PER-TX)
Period of the LP XOR clock
Measured at end of HS
transmission.
35
First LP XOR clock pulse after Stop
state or last pulse before Stop state
40
ns
All other pulses
20
ns
90
ns
Slew Rate at CLOAD = 70 pF
δV/δtsr
CLOAD
(1)
ns
150
Slew Rate at CLOAD = 0 pF Fallng edge only
30
Slew Rate at CLOAD = 0 pF Rising edge only
30
mV/ns
mV/ns
mV/ns
Load Capacitance
70
pF
(1) All typical values are at VCC = 3.3 V, and TA = 25°C.
SDA
tf
tHD;STA
tLOW
tr
tf
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 1. I2C Timing
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0.0UI
1.0UI
0.5UI
TSKEW-TX
THOLD-RX
TSETUP-RX
DCLK
D[3:0]
Figure 2. DPHY HS RX and TX Timing
DB*P
VOD_TBx
VOD_VDx
VCMTX
DB*N
Pre-Emphasis = 20 LOG ( VOD_TBX /
VOD_VDX )
Figure 3. DPHY HS TX Pre-emphasis
6.9 Typical Characteristics
0
-5
-5
-10
-10
-15
-20
S11 (dB)
S22 (dB)
-15
-25
-30
-20
-25
-30
-35
-35
-40
-40
-45
-50
10
-45
100
1k
10k
100k 1M 10M 100M
Frequency (Hz)
1G
Figure 4. Return Loss (RL), Transmitter
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10G
1
10
100
1k
D003
10k 100k 1M
Frequency (Hz)
10M 100M 1G
D004
Figure 5. Return Loss (RL), Receiver
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7 Detailed Description
7.1 Overview
The DPHY440SS is a one to four lane and clock MIPI DPHY re-driver that regenerates the DPHY signaling. The
device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at
datarates of up to 1.5 Gbps.
The device compensates for PCB, connector, and cable related frequency loss and switching related loss to
provide the optimum electrical performance from a CSI2/DSI source to sink. The DPHY440 DPHY inputs feature
configurable equalizers.
The output pins will automatically compensate for uneven skew between clock and data lanes. The DPHY440
output swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin
respectively.
The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link
interface that can transition into a lower power mode when in ULPS and LP states.
The device is characterized for an extended operational temperature range from –40ºC to 85ºC.
7.2 Functional Block Diagram
DA0P
DA0N
DA1P
DA1N
DACP
DACN
DA2P
DA2N
DA3P
DA3N
HS RX
LP RX/TX
CHANNEL
CONTROL
HS TX
LP RX/TX
HS RX
LP RX
CHANNEL
CONTROL
HS TX
LP TX
HS RX
LP RX
CHANNEL
CONTROL
HS TX
LP TX
HS RX
LP RX
CHANNEL
CONTROL
HS TX
LP TX
HS RX
LP RX
CHANNEL
CONTROL
HS TX
LP TX
DB0P
DB0N
DB1P
DB1N
DBCP
DBCN
DB2P
DB2N
DB3P
DB3N
I2C
Slave
EQ/SCL
VSADJ_CFG0
ERC/SDA
PRE_CFG1
VREG_OUT
VCC
VREG
LDO
VCC
CSR
Space
VCore
RRST=300k
RESET/EN
RSTN
GND
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7.3 Feature Description
7.3.1 HS Receive Equalization
The DPHY440 supports three levels of receive equalization to compensate for ISI loss in the channel. These
three levels are 0 dB, 2.5 dB, and 5 dB at 750MHz. The equalization level used by the DPHY440 is determined
by the state of the EQ/SCL pin at the rising edge of RSTN. If necessary, the receiver equalization level can also
be set through writing to the RXEQ register via the local I2C interface
Table 1. EQ/SCL pin Function
EQ/SCL PIN
HS Rx EQUALIZATION
≤ VIL
0 dB
VIM
2.1 dB at 500 MHz / 2.5 dB at 750 MHz
≥ VIH
4 dB at 500 MHz / 5 dB at 750 MHz
7.3.2 HS TX Edge Rate Control
The DPHY440 supports control of the rise and fall time for the DB[3:0]P/N and DBCP/N High Speed (HS)
transmitters. Depending on system operating datarate, the HS edge rate may need to be adjusted to help
improve EMI performance. The HS edge rate setting is determined through the sampled state of ERC/SDA pin at
the rising edge of RSTN. If necessary, the HS edge rate can be adjusted by writing to the HS_ERC register via
the local I2C interface.
Table 2. 8.3.2 HS TX Edge Rate Control
ERC/SDA PIN
HS RISE/FALL TIMES
≤ VIL
200 ps typical
VIM
150 ps typical
≥ VIH
250 ps typical
The DPHY440 also supports edge rate control for the LP interface. The adjustment of LP TX edge rate is
determined by the state of the VSADJ_CFG0 and PRE_CFG1 pins as depicted in Table 3, but can also be
modified by changing LP_ERC register through the local I2C interface
7.3.3 TX Voltage Swing and Pre-Emphasis Control
In some applications, the DPHY440 may be placed at a location in the system where the channel from DPHY440
DB[3:0]P/N interface to the DPHY Sink (CSI-2 or DSI) is extremely long and the DPHY Sink does not have
enough receive equalization to compensate for the ISI loss. In this application, the system architect may want to
use the DPHY440 TX pre-emphasis feature to compensate for the lack of equalization at the DPHY sink. The
DPHY440 provides two levels of pre-emphasis: 0 dB, and 2.5 dB. The TX Pre-emphasis settings is determined
through the sampled sate of PRE_CFG[1:0] pins at the rising edge of RSTN. If necessary, the TX Pre-emphasis
settings can be adjusted by writing to the HSTX_PRE register through the local I2C interface.
This feature must only be used when the HS pre-emphasis bit (transition bit) is attenuated by the channel.
Enabling pre-emphasis in a system that has little channel loss (transition bit is not attenuated) may result in
negative impact to system performance.
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Table 3. HS Voltage Swing, HS Pre-emphasis, LPTX Edge Rate Controls
VSADJ_CFG0
PRE_CFG1
HS TX VOD
HS TX PRE-EMPHASIS
DB[3:0] LP TX RISE/FALL
TIME
≤ VIL
≤ VIL
200 mV
0 dB
18 ns
VIM
≤ VIL
200 mV
0 dB
27 ns
≥ VIH
≤ VIL
220 mV
0 dB
18 ns
≤ VIL
VIM
200 mV
0 dB
27 ns
VIM
VIM
200 mV
0 dB
21 ns
≥ VIH
VIM
220 mV
0 dB
21 ns
≤ VIL
≥ VIH
220 mV
2.5 dB
27 ns
VIM
≥ VIH
200 mV
2.5 dB
21 ns
≥ VIH
≥ VIH
220 mV
2.5 dB
21 ns
7.3.4 Dynamic De-skew
The DPHY440 implements a dynamic de-skew feature which will continuously de-skew the HS data received on
the DA[3:0]P/N interface and provide a retimed version on the DB[3:0]P/N interface. The retimed version is
centered within the DBCP/N clock.
Lanes are skewed at Input
Lanes Deskewed at Output.
DACP
DBCP
DACN
DBCN
DA0P
DB0P
DA0N
DB0N
DA1P
DB1P
DA1N
DB1N
DA2P
DB2P
DA2N
DB2N
DA3P
DB3P
DA3N
DB3N
Data centered within clock
Data Delayed by
2 Clocks (4UI)
Figure 6. Dynamic De-skew
NOTE
The dynamic de-skew feature is only enabled in HS mode, and causes a 2 clock (4 UI)
delay of data while data traverses from DA to DB.
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7.4 Device Functional Modes
LP MODE
ULPS Exit
(LP11)
RSTN = 1
ULPS Entry
RSTN = 0
RSTN = 0
ULPS
HS Exit
(LP11)
HS Entry
SHUTDOWN
RSTN = 0
RSTN = 0
HS MODE
Figure 7. Functional Modes
7.4.1 Shutdown Mode
The DPHY440 can be placed into a low power consumption state by asserting the RSTN pin low while
maintaining a stable VCC and VDD power supply. While in the Shutdown state, the DPHY440 drives DB[3:0]P/N
and DBCP/N pins to the LP00 state. The DPHY440 ignores all activity on the DA[3:0]P/N and DACP/N pins while
in Shutdown mode. The Shutdown mode is exited by de-asserting the RSTN pin high. Upon exiting Shutdown
mode, the DPHY440 enters LP Mode operation and pass what is received on the DA interface to the DB
interface.
7.4.2 LP Mode
In this mode, the DPHY440 passes LP signals between DA[3:0]P/N and DB[3:0]P/N. The internal terminations for
the HS receiver and HS transmitter are disabled when operating in this mode.
The MIPI DSI specification defines bidirectional communication between the host and peripheral. When a
response is needed by the peripheral, the response is returned using LP signaling from DB0P/N to DA0P/N. The
DPHY440 only supports this communication over lane 0 (DB0P/N to DA0P/N). The remaining lanes cannot be
used for LP communications from peripheral to host (reverse direction).
7.4.3 ULPS Mode
The DPHY440 is continuously monitoring the DPHY LP protocol for entry into the ULPS state. Upon entry into
the ULPS state, the DPHY440 keeps active the logic necessary for LP signaling (LP rx, LPtx, LP state machine,
so forth). All logic needed for HS operation are disabled. This allows for a lower power state than can be
achieved when in operating other LP power states.
NOTE
ULPS mode can only be entered from LP Mode.
7.4.4 HS Mode
The HS mode is entered when the required sequence of LP signals is detected by the LP state machine. In this
mode, the internal termination for both the HS receiver and HS transmitter is enabled and the dynamic de-skew
feature is enabled. The DPHY440 remains in this mode until a HS exit is detected by the LP state machine.
Upon detecting the HS exit, the DPHY440 immediately transitions to LP Mode.
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7.5 Register Maps
The DPHY440 local I2C interface is enabled when RSTN is input high. Access to the CSR registers is supported
during ultra-low power state (ULPS). The EQ/SCL and ERC/SDA terminals are used for I2C clock and I2C data
respectively. The DPHY440 I2C interface conforms to the two-wire serial interface defined by the I2C Bus
Specification, Version 2.1 (January 2000) and supports up to 100 kHz.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for DPHY440 is factory preset to 1101100.
Table 4. DPHY440 I2C Target Address Description
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
1
1
0
1
1
0
0
0/1
Address Cycle is 0xD8 (Write) and 0xD9 (Read)
The following procedure should be followed to write to the DPHY440 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The DPHY440 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of
data, MSB-first
4. The DPHY440 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The DPHY440 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the DPHY440.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the DPHY440 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The DPHY440 acknowledges the address cycle.
3. The DPHY440 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the DPHY440 I2C register occurred prior to the read, then the DPHY440 starts at
the sub-address specified in the write.
4. The DPHY440 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the DPHY440 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The DPHY440 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of
data, MSB-first.
4. The DPHY440 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C write occurred prior to the read, then the reads start at the subaddress specified by the write.
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7.5.1 BIT Access Tag Conventions
A table of bit descriptions is typically included for each register description that indicates the bit field name, field
description, and the field access tags. The field access tags are described in Table 5.
Table 5. Tag Conventions
ACCESS TAG
NAME
DEFINITION
R
Read
The field may be read by software.
W
Write
The field may be written by software
S
Set
The field may be set by a write of one. Writes of zero to the field have no effect.
C
Clear
The field may be cleared by a write of one. Write of zero to the field have no effect.
U
Update
Hardware may autonomously update this field
N/A
No Access
Not accessible or not applicable
7.5.2 Standard CSR Registers (address = 0x000 - 0x07)
Figure 8. Standard CSR Registers (0x000 - 0x07)
7
6
5
4
3
2
1
0
R
R
R
R
DEVICE_ID
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Standard CSR Registers (0x000 - 0x07)
Bit
Field
Type
Reset
Description
7:0
DEVICE_ID
R
0
For the DPHY440 these fields return a string of ASCII characters
returning “DPHY100”.
Addresses 0x07 - 0x00 = {0x20, 0x30, 0x30, 0x31, 0x59, 0x48,
0x50, 0x44}
7.5.3 Standard CSR Register (address = 0x08)
Figure 9. Standard CSR Register (0x08)
7
6
5
4
3
2
1
0
R
R
R
R
DEVICE_REV
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Standard CSR Register (0x08)
16
Bit
Field
Type
Reset
Description
7:0
DEVICE_REV
R
0
Device revision.
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7.5.4 Standard CSR Register (address = 0x09)
Figure 10. Standard CSR Register(0x09)
7
6
5
4
3
Reserved
R
RW
2
1
RXEQ_CLK.
RW
RW
RW
0
RXEQ_DATA
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Standard CSR Register (0x09)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0
Reserved
3:2
RXEQ_CLK
RW
0
This field selects the EQ level of the DACP/N. The value in this
field will match the sampled state of EQ/SCL pin at the rising
edge of RSTN. Software can change the value of this field at a
later time.
00 – 0 dB (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM)
10 – Reserved.
11 – 5 dB (EQ/SCL pin = VIH)
1:0
RXEQ_DATA
RW
0
This field selects the EQ level of the DA[3:0]P/N . The value in
this field will match the sampled state of EQ/SCL pin at the
rising edge of RSTN. Software can change the value of this field
at a later time.
00 – 0 dB. (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM)
10 – Reserved.
11 – 5 dB. (EQ/SCL pin = VIH)
7.5.5 Standard CSR Register (address = 0x0A)
Figure 11. Standard CSR Register (0x0A)
7
6
LPTXDA_ERC
RW
RW
5
4
LPTXDB_ERC
RW
RW
3
2
1
Reserved
R
0
HSC_ERC
R
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Standard CSR Register (0x0A)
Bit
Field
Type
Reset
Description
7:6
LPTXDA_ERC
RW
0
This field controls the edge rate of the DA0P/N LP transmitters.
00 – 18 ns at 70 pF (Default)
01 – 21 ns at 70 pF
10 – 15 ns at 70 pF
11 – 27 ns at 70 pF
5:4
LPTXDB_ERC
RW
0
This field controls the edge rate of the DB[3:0]P/N LP
transmitters. The value in this field will be updated by hardware
based on the state of the CFG[1:0] pin. Refer to Table 3 for
settings based on sampled state of CFG[1:0] Software can
change the value of this field at a later time.
00 – 18 ns at 70 pF
01 – 21 ns at 70 pF
10 – 15 ns at 70 pF
11 – 27 ns at 70 pF
3:2
Reserved
R
1:0
HSC_ERC
RW
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Reserved
0
This field controls the edge rate of the DBCP/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM)
10 – 250 ps at 1 Gbps. (ERC pin = VIH)
11 – 300 ps at 1 Gbps
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7.5.6 Standard CSR Register (address = 0x0B)
Figure 12. Standard CSR Register (0x0B)
7
6
5
HSDB3_ERC
RW
4
3
HSDB2_ERC
RW
RW
RW
2
RHSDB1_ERC
RW
RW
1
0
HSDB0_ERC
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Standard CSR Register (0x0B)
18
Bit
Field
Type
Reset
Description
7:6
HSDB3_ERC
RW
0
This field controls the edge rate of the DB3P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM)
10 – 250 ps at 1 Gbps. (ERC pin = VIH)
11 – 300 ps at 1 Gbps
5:4
HSDB2_ERC
RW
0
This field controls the edge rate of the DB2P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM)
10 – 250 ps at 1 Gbps. (ERC pin = VIH)
11 – 300 ps at 1 Gbps
3:2
RHSDB1_ERC
RW
0
This field controls the edge rate of the DB1P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM)
10 – 250 ps at 1 Gbps. (ERC pin = VIH)
11 – 300 ps at 1 Gbps
1:0
HSDB0_ERC
RW
0
This field controls the edge rate of the DB0P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM)
10 – 250 ps at 1 Gbps. (ERC pin = VIH)
11 – 300 ps at 1 Gbps
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7.5.7 Standard CSR Register (address = 0x0D)
Figure 13. Standard CSR Register (0x0D)
7
6
5
CDB0N_STATUS
R
Reserved.
R
R
4
CDB0P_STATUS
R
3
2
1
CDA0N_STATUS
R
Reserved
R
R
0
CDA0P_STATUS
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Standard CSR Register (0x0D)
Bit
Field
Type
7:6
Reset
Description
Reserved.
R
5
CDB0N_STATUS
R
0
0 – Contention not detected on DB0N interface.(default)
1 – Contention detected on DB0N interface
4
CDB0P_STATUS
R
0
0 – Contention not detected on DB0P interface.(default)
1 – Contention detected on DB0P interface
3:2
Reserved.
Reserved
R
1
CDA0N_STATUS
R
0
Reserved
0 – Contention not detected on DA0N interface.(default)
1 – Contention detected on DA0N interface
0
CDA0P_STATUS
R
0
0 – Contention not detected on DA0P interface.(default)
1 – Contention detected on DA0P interface
7.5.8 Standard CSR Register (address = 0x0E)
Figure 14. Standard CSR Register (0x0E)
7
6
Reserved
R
R
5
4
HSTX_VSADJ
RW
RW
3
2
1
Reserved
R
0
HSTX_PRE
R
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Standard CSR Register (0x0E)
Bit
Field
Type
7:6
Reserved
R
5:4
HSTX_VSADJ
RWU
3:2
Reserved
R
1:0
HSTX_PRE
RWU
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Reset
Description
Reserved
0
This field controls the HS TX voltage swing level. The value of
this field will match the sampled state of the CFG[1:0] pins.
Software can change the value of this field at a later time.
00 – 180 mV
01 – 200 mV (CFG0 = VIM or (CFG0 = VIL and !CFG1 = VIH))
1X – 220mV (CFG0 = VIH or (CFG0 = VIL and CFG1 = VIH))
Reserved
0
This field controls the HS TX pre-emphasis level. The value of
this field will match the sampled state of CFG1 pin. Software can
change the value of this field at a later time.
00 – 1.5 dB
01 – 0 dB (CFG1 = VIM or VIL)
1X – 2.5 dB (CFG1 = VIH)
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7.5.9 Standard CSR Register (address = 0x10) [reset = 0xFF]
Figure 15. Standard CSR Register (0x10)
7
6
5
RW
RW
RW
4
3
LPTXDA_ERC
RW
RW
2
1
0
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Standard CSR Register (0x10)
Bit
Field
Type
Reset
Description
7:0
LPTXDA_ERC
RW
0xFF
This field represents the lower 8-bits of the 16-bit
BTA_TIMEOUT register. Timer is reset to default state when
BTA request is detected and is stopped when BTA is
acknowledged. If BTA is not acknowledged before this timer
expires, then DPHY440 will terminate BTA operation. This
counter operates on the LPTX clock. Defaults to 0xFF.
7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
Figure 16. Standard CSR Register (0x11)
7
6
5
RW
RW
RW
4
3
BTA_TIMEOUT_HI
RW
RW
2
1
0
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Standard CSR Register (0x11)
20
Bit
Field
Type
Reset
Description
7:0
BTA_TIMEOUT_HI
RW
0xFF
This field represents the upper 8-bits of the 16-bit
BTA_TIMEOUT register. Timer is reset to default state when
BTA request is detected and is stopped when BTA is
acknowledged. If BTA is not acknowledged before this timer
expires, then DPHY440 will terminate BTA operation. This
counter operates on the LPTX clock. Defaults to 0xFF.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information,
The DPHY440 supports up to 4 DSI DPHY lanes and a clock lane. One of the four lanes is used for back
channel communications between GPU and DSI panel. DPHY440’s lane 0 is the only lane that supports the back
channel. For this reason, DPHY440 lane 0 must always be connected to lane 0 of GPU and panel.
Other combinations, like 1 and 3 lane, examples are not shown, but are fully supported by the DPHY440. For all
DSI implementations, the polarity must be maintained between the DSI Source and DSI Sink. The DPHY440
does not support polarity inversion.
8.2 Typical Application, CSI-2 Implementations
The DPHY440 supports 4 CSI-2 DPHY lanes plus a clock. Unlike DSI, CSI-2 does not have a back channel path.
Because of this, there is no requirement on lane ordering. Because there is no lane ordering requirement, there
are more combinations which can be implemented. All possible combinations are supported by the DPHY440.
For all CSI-2 implementations, the polarity must be maintained between the CSI-2 Source and CSI-2 Sink. The
DPHY440 does not support polarity inversion.
12 inch FR-4,
10 mil
Camera
Input trace
SNx5D
PHY44
0SS
1 inch FR-4,
10 mil
APU
Output
trace
Figure 17. CSI-2 Example: Typical SNx5DPHY440SS Placement in the System
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Typical Application, CSI-2 Implementations (continued)
VCC_1.8V
DPHY440SS
VCC
RSTN
Camera
(CSI-2 Source)
100nF
VREG_OUT
200nF
VDD
APU
(CSI-2 Sink)
100nF
CSI TX
ERC/SDA
EQ/SCL
SDA
PRE_CFG1
CSI Slave
SCL
CSI0P
CSI0N
CSICP
CSICN
CSI1P
CSI1N
Vio
VSADJ_CFG0
CSI0P
CSI0N
CSICP
CSICN
CSI1P
CSI1N
CSI RX
DB0P
DB0N
DB1P
DB1N
DBCP
DBCN
DB2P
DB2N
DB3P
DB3N
DA0P
DA0N
DA1P
DA1N
DACP
DACN
DA2P
DA2N
DA3P
DA3N
2K
2K
CSI Master
SCL
R1
R2
R3
R4
R5
R6
R7
SDA
R8
VCC_1.8V
Copyright © 2016, Texas Instruments Incorporated
Figure 18. CSI-2 Two Lane Example
8.2.1 Design Requirements
Typically, in CSI-2 applications, the system trace length from the Camera (Source) to the DPHY440 device is
different from that of the trace length from DPHY440 to the APU (Sink). Consequently, different pre-emphasis
and equalization settings are required on the receiver and transmitter side of the device respectively.
For this design example, refer to Figure 17 and Figure 18. Shown is a CSI-2 system implementation in which the
DPHY device is placed close to the Sink (APU). Here, the input trace length is about 12 inch while the output
trace length is just 1 inch. The input signal characteristics assumed are shown in Table 15.
Table 15. Design Parameters
22
PARAMETER
VALUE
Data Rate (200 Mbps to 1.5 Gbps)
1 Gbps
Input trace length
12 inch
Output trace length
1 inch
Trace width
10 mils
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8.2.2 Detailed Design Procedure
The typical example describes how to configure the VSADJ, PRE, EQ and ERC configuration pins of the
DPHY440 device based on the board trace length between the Source (Camera) and DPHY440 and the
DPHY440 and Sink (APU). Actual configuration settings might differ due to additional factors such as board
layout, and connectors used in the signal path.
Though the data rate in this example is 1 Gbps, device is placed near to the Sink, with a short output trace of 1
inch. Consequently, the ERC pin can be configured to have a rise/fall time of 250 ps for the edge. Further, due to
the short output trace, the PRE pin must be configured to a setting of 0 dB and the VSADJ to be 200 mV. The
Application Curve in Figure 22 shows the FR-4 loss characteristics of a 10 mil wide, 12 inch long trace. From this
plot, the input signal trace suffers a loss of 1.5 dB at 500 MHz. Thus, the EQ setting can be either 0 dB or 2.5
dB. All the configuration settings and their corresponding inputs are tabulated in Table 16.
Table 16. Configuration Pin Settings
PIN
SETTING
INPUT VALUE
VSADJ
200 mV
VIM
PRE
0 dB
VIM
EQ
0 dB or 2.5 dB
VIL or VIM
ERC
250 ps
VIH
The configuration pins each have internal pull-up and pull-down resistors of 100 kΩ each. Thus, the
recommendation is an external pull-up/pull-down resistors of about 10 kΩ each, to meet the requirement of the
threshold levels for the VIL and VIH listed in the Electrical Characteristics table. The external resistors shown in
Figure 18 should be populated to produce corresponding configuration settings, according to the list given in
Table 17.
Table 17. Resistor Parameters
RESISTOR NAME
VALUE
R1
Leave unpopulated
R2
Leave unpopulated
R3
Leave unpopulated
R4
Leave unpopulated
R5
Leave unpopulated
R6
10 kΩ (EQ = 0 dB) or
Leave unpopulated (EQ = 2.5 dB)
R7
10 kΩ
R8
Leave unpopulated
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8.2.2.1 Reset Implementation
The DPHY440 RSTN input gives control over the device reset and to place the device into low power mode. It is
critical to reset the digital logic of the DPHY440 after the VCC supply is stable (that is, the power supply has
reached the minimum recommended operating voltage). This is achieved by transitioning the RSTN input from a
low level to a high level. A system may provide a control signal to the RSTN signal that transitions low to high
after the power supply is (or supplies are) stable, or implement an external capacitor connected between RSTN
and GND, to allow delaying the RSTN signal during power up. Both implementations are shown in Figure 19 and
Figure 20.
VCC
open drain
output
RST
GPO
RST
REN=150 k
C
C
DPHY440
controller
Figure 19. External Capacitor Controlled RSTN
DPHY440
Figure 20. RSTN Input from Active Controller
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of
the VCC supply, where a slower ramp-up results in a larger value external capacitor.
Refer to the latest reference schematic for the DPHY440 device and/or consider approximately 200-nF capacitor
as a reasonable first estimate for the size of the external capacitor.
When implementing an RSTN input from an active controller, it is recommended to use an open drain driver if the
RSTN input is driven. This protects the RSTN input from damage of an input voltage greater than VCC.
td1
tsu2
RSTN
VCC
th2
CFG[1:0], EQ, ERC
Figure 21. Power-Up Timing Requirements
Table 18. Timing Requirements
DESCRIPTION (1)
MIN
tD1
VCC stable before de-assertion of RSTN.
tsu2
Setup of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin before de-assertion of
RSTN.
th2
Hold of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin after de-assertion of
RSTN.
250 µs
tVCC_RAMP
VCC supply ramp requirements
0.2 ms
(1)
24
MAX
100 µs
0
100 ms
Unused DAxP/N pins shall be tied to GND.
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0
0
-0.5
-0.5
Loss (dB) (S(2,1))
Loss (dB) (S(2,1))
8.2.3 Application Curves
-1
-1.5
-2
-1
-1.5
-2
-2.5
1M
10M
100M
Frequency (Hz)
-2.5
1M
1G
10M
D001
12 inch long, 5 mil wide FR4 trace
100M
Frequency (Hz)
1G
D002
12 inch long, 10 mil wide FR4 trace
Figure 22. Loss vs Frequency
Figure 23. Loss vs Frequency
9 Power Supply Recommendations
Texas Instruments recommends a 0.1-µF capacitor on each power pin.
RESETN
C2
C1
0.1uF
VCC_1.8 V
25
26
VDD
PRE_CFG1
27
VSADJ_CFG0
28
RSTN
DA3P
DA3N
DPHY440SS
DB2P
DB2N
ERC/SDA
DA2P
DA2N
EQ/SCL
9
10
DPHYIN_A3P
DPHYIN_A3N
DBCP
DBCN
DB3P
DB3N
24
23
22
21
20
19
18
17
16
15
DPHYOUT_B0P
DPHYOUT_B0N
DPHYOUT_B1P
DPHYOUT_B1N
DPHYOUT_BCP
DPHYOUT_BCN
DPHYOUT_B2P
DPHYOUT_B2N
DPHYOUT_B3P
DPHYOUT_B3N
14
DPHYIN_A2P
DPHYIN_A2N
DACP
DACN
VREG_OUT
7
8
DB0P
DB0N
DB1P
DB1N
13
5
6
DPHYIN_ACP
DPHYIN_ACN
DA1P
DA1N
VCC
DPHYIN_A1P
DPHYIN_A1N
12
3
4
DA0P
DA0N
11
1
2
DPHYIN_A0P
DPHYIN_A0N
TP
U1
29
0.2 uF
C3
C4
0.1 uF
0.1 uF
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Supply Implementation
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
DAxP/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 15%) or 50-Ω
single-ended impedance (± 15%).
Keep away from other high speed signals.
Keep lengths to within 5 mils of each other.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left
and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will
minimize any length mismatch causes by the bends and; therefore, minimize the impact bends have on EMI.
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will; therefore, negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
10.2 Layout Example
Figure 25. Example Layout
26
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65DPHY440SS
Click here
Click here
Click here
Click here
Click here
SN75DPHY440SS
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65DPHY440SSRHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DPHY440
SN65DPHY440SSRHRT
ACTIVE
WQFN
RHR
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DPHY440
SN75DPHY440SSRHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
DPHY440
SN75DPHY440SSRHRT
ACTIVE
WQFN
RHR
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 70
DPHY440
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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