SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
D
D
D
D
D
D
D
D
Provides Differential SCSI From
Single-Ended Controller When Used With
the SN75LBC970A Control Transceiver
Designed to Operate at Fast-SCSI Speed of
Ten Million Data Transfers per Second
Meets or Exceeds the Requirements of EIA
Standard RS-485 and ISO-8482 Standards
Packaged in Shrink Small-Outline Package
With 25-Mil Terminal Pitch
Low Disabled-Supply Current
23 mA Typ
Thermal Shutdown Protection
Positive- and Negative-Current Limiting
Power-Up/-Down Glitch Protection
DL PACKAGE
(TOP VIEW)
description
The SN75LBC971A SCSI differential converter-data is
an adaptation of the industry’s first 9-channel RS-485
transceiver, the SN75LBC976. When used in conjunction with its companion control transceiver, the
SN75LBC970A, the resulting chip set provides the
superior electrical performance of differential SCSI
from a single-ended SCSI bus or controller. A 16-bit
SCSI bus can be implemented with just three devices
(two data and one control) in the space efficient, 56-pin,
shrink small-outline package (SSOP) and a few
external components. An 8-bit SCSI bus requires only
one data and one control transceiver.
SDB
DRVBUS
GND
ADBP –
NC
ADB7 –
NC
ADB6 –
NC
ADB5 –
NC
VCC
GND
GND
GND
GND
GND
VCC
ABD4 –
NC
ADB3 –
NC
ADB2 –
NC
ADB1 –
NC
ADB0 –
NC
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
DSENS
RESET
GND
BDBP –
BDBP +
BDB7 –
BDB7 +
BDB6 –
BDB6 +
BDB5 –
BDB5 +
VCC
GND
GND
GND
GND
GND
VCC
BDB4 –
BDB4 +
BDB3 –
BDB3 +
BDB2 –
BDB2 +
BDB1 –
BDB1 +
BDB0 –
BDB0 +
29
In a typical differential SCSI node, the SCSI controller
provides an enable for each external RS-485
Pins 13 – 17 and 40 – 44 are connected
transceiver channel. This could require as many as 27
together to the package lead frame and
extra terminals for a 16-bit differential bus controller or
to signal ground.
relegate a 16-bit, single-ended controller to only an
NC – No internal connection
8-bit differential bus. Using the standard nine SCSI
control signals, the SN75LBC970A control transceiver decodes the state of the bus and enables the
SN75LBC971A data transceiver to transmit the single-ended SCSI input signals (A side) differentially to the
cable or receive the differential cable signals (B side) and drive the single-ended outputs to the controller.
A reset function, which disables all outputs and clears internal latches, can be accomplished from two external
inputs and two internally-generated signals. RESET (reset) and DSENS (differential sense) are available to
external circuits for a bus reset or to disable all outputs should a single-ended cable be inadvertently connected
to a differential connector. Internally-generated power-up and thermal-shutdown signals have the same affect
when the supply voltage is below approximately 3.5 V or the junction temperature exceeds 175°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
description (continued)
The SCSI, differential, converter-data chip operates in two modes depending on the state of the DRVBUS input.
With DRVBUS low, a bidirectional latch circuit sets the direction of data transfer. Each data bit has its own latch,
and each bit’s direction is independent of all other bits. When neither the single-ended nor the differential sides
are asserted, the latch disables both A- and B-side output drivers. When the input to either side is asserted, the
latch enables the opposite side’s driver and sets data flow from the asserted input to the opposite side of the
device. When the input deasserts, the latch maintains the direction until the receiver on the enabled driver
detects a deassertion. The latch then returns to the initial state. No parity checking is done by this device; the
parity signal passes through the device like other data signals do.
When DRVBUS is high, direction is determined by the SDB signal. However, a change in SDB does not always
immediately change the direction. When DRVBUS first asserts, the direction indicated by SDB is latched and
takes effect immediately. When SDB changes while DRVBUS is high, the drivers that were on immediately turn
off. However, the other driver set does not turn on until the receivers sense a deasserted state on all nine data
lines. This is done to prevent the active drivers from turning on until all other drivers are off and the terminators
pull the lines to a deasserted state.
The single-ended SCSI bus interface consists of CMOS, bidirectional inputs and outputs. The drivers are rated
to ± 16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need
for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended
side of the device is not intended to drive the SCSI bus directly.
The differential SCSI bus interface consists of bipolar, bidirectional inputs and outputs that meet or exceed the
requirements of EIA-485 and ISO 8482-1982/TIA TR30.2 referenced by American National Standard of
Information Systems (ANSI) X3.131-1994 Small Computer System Interface-2 (SCSI-2).
The SN75LBC971A is characterized for operation over the temperature range of 0°C to 70°C.
TERMINAL FUNCTION
TERMINAL
I/O
DESCRIPTION
4, 6, 8, 10, 19,
21, 23, 25, 27
I/O, Single-ended
SCSI voltage levels,
Strong pullup
Bidirectional I/O for data and parity bits to and from the single-ended SCSI
controller. As outputs, these terminals can source or sink 16 mA. As inputs,
they are pulled up with about 4-mA to eliminate external resistors.
BDBn+, where
n = {0,1,2,3,4,5,6,7,P}
29, 31, 33, 35,
37, 46, 48, 50, 52
I/O, RS-485,
Weak pulldown
Bidirectional I/O for data and parity to and from the differential SCSI bus.
BDBn–, where
n = {0,1,2,3,4,5,6,7,P}
30, 32, 34, 36,
38,47, 49, 51, 53
I/O, RS-485,
Weak pulldown
Bidirectional I/O for the complement of data and parity to and from the
differential SCSI bus.
DRVBUS
2
Input, TTL levels,
Weak pulldown
A high-level logic signal from the control transceiver enables either the
single-ended or differential drivers as directed by SDB.
DSENS
56
Input, TTL levels,
Weak pullup
A low-level input initializes the internal latches and disables all drivers.
RESET
55
Input, TTL levels,
Weak pullup
A low-level input initializes the internal latches and disables all drivers.
SDB
1
Input, TTL levels,
Weak pulldown
A high-level logic signal from the control transceiver sends data from the
differential bus to the single-ended bus. A low-level signal reverses the
flow.
NAME
NO.
ADBn–, where
n = {0,1,2,3,4,5,6,7,P}
2
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
functional block diagram
SN75LBC971A
53
ADBP –
4
52
Control
Latch
ADB7 –
BDBP –
BDBP +
51 BDB7 –
50
BDB7 +
6
Control
Latch
(6 Identical Channels
Not Shown)
30
ADB0 –
27
29
Control
Latch
Power-Up
and Thermal
Shut-Down
Circuits
BDB0 –
BDB0 +
Steering and
Control Logic
2
1
55
56
DRVBUS
RESET
SDB
DSENS
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
schematics of inputs and outputs
RESET, AND DSENS
SDB AND DRVBUS
VCC
VCC
22 kΩ
200 Ω
200 Ω
Input
Input
50 kΩ
A
B + AND B –
VCC
VCC
4 mA
100 kΩ
(B – Pin Only)
3 kΩ
Input
Input
200 Ω
18 kΩ
100 kΩ
(B + Pin Only)
12 kΩ
1 kΩ
B + AND B –
VCC
A
100 kΩ
(B – Pin Only)
VCC
3 kΩ
Output
18 kΩ
Output
12 kΩ
1 kΩ
4
100 kΩ
(B + Pin Only)
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Differential bus voltage range (B side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V to 15 V
Single-ended bus voltage range (A side and control inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous total power dissipation (see Note 2) . . . . . . . . . . Internally Limited (see Dissipation Rating Table)
Electrostatic discharge (see Note 3): Class 1 A (all pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Class 1 B (all pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
Class 2 A (B-side and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Class 2 B (B-side and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
3. This absolute maximum rating is tested in accordance with MIL-STD-883C, Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DL
2500 mW
20 mW/°C
1600 mW
‡ This is the inverse of the traditional junction-to-case thermal resistance (RθJA).
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
High-level input voltage, VIH
A side and control
Low-level input voltage, VIL
A side and control
0.8
V
B side
12
–7
V
B side
– 60
A side
– 16
B side
60
A side
16
Voltage at any bus terminal (separately or common-mode), VO or VI
High level output current,
High-level
current IOH
Low level output current,
Low-level
current IOL
2
V
mA
mA
Operating case temperature, TC
0
125
°C
Operating free-air temperature, TA
0
70
°C
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VOD(H)
VOD(L)
See Figure 1
Driver low-level differential output voltage
See Figure 1
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
VIT+
Receiver positive-going
differential input
threshold voltage
VIT–
Receiver negative-going
differential input
threshold voltage
Vhys
Receiver input hysteresis
voltage (VIT + – VIT –)
II
TEST CONDITIONS
Driver high-level differential output voltage
Bus input current
A side
B side
A side
B side
B side
VID = – 200 mV,
IOH = – 60 mA
IOH = – 16 mA
VID = 200 mV,
IOL = 60 mA
IOL = 16 mA
IOH = – 16 mA
See Figure 2
IOL = 16 mA
See Figure 2
High-level input current
– 2.2
V
2.5
4.2
0.4
– 0.2
45
1
0.7
1
VI = – 7 V,,
Other input at 0 V
VCC = 5 V
VCC = 0
– 0.5
– 0.8
– 0.4
– 0.8
VIL = 0.8 V
–5
–8
– 70
– 100
8
20
–6
–8
– 66
– 100
±1
IOS
Short-circuit output
current
IOZ
High-impedance-state
g
output current
B side
Disabled
RESET at 0.8 V,
Others open
Supply current
B to A
Enabled
SDB and DRVBUS at 2 V,
All other inputs open,
VID = – 1 V,
No load
A to B
Enabled
SDB at 0.8 V,
All other inputs open,
DRVBUS at 2 V,
No load
VI = 0.6 sin(2π × 106t) + 1.5 V,
B to A,
ICC
± 250
VO = 5 V and 0
A side
CO
Output capacitance
Cpd
Power dissipation capacitance‡
V
mV
0.6
VIH = 2 V
V
V
SDB, DRVBUS
B side
0.8
0.2
– 2.9
RESET, DSENS
V
VCC = 5 V
VCC = 0
A side
Low-level input current
–1
1.6
SDB, DRVBUS
IIL
V
VI = 12 V,,
Other input at 0 V
B or B
UNIT
1.8
35
RESET, DSENS
MAX
1
3.4
A side
IIH
MIN TYP†
mA
mA
mA
µA
mA
µA
mA
See IIH and IIL
See II
23
33
36
4
9
BDBn to GND
19
21
One channel
100
mA
pF
pF
A to B,
One channel
450
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Cpd determines the no-load dynamic current consumption, IS = Cpd × VCC × f + ICC (ICC depends on the output states and load circuits and is
not necessarily the ICC specified in the Electrical Characteristics Table).
6
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
switching characteristics over recommended of operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figures 3 and 4
td1, td2
D l time,
ti
t B,
B highhi h to
t low-level
l
l
l or
Delay
A to
low- to high-level output
out ut
VCC = 5 V,
VCC = 5 V,
Delay
D
l time,
ti
B to
t A,
A highhi h to
t low-level
l
l
l or
low- to high-level output
out ut
VCC = 5 V,
VCC = 5 V,
MAX
UNIT
8.5
25.3
ns
TA = 25°C,
TA = 70°C,
See Figures 3 and 4
10
18
ns
See Figures 3 and 4
12.5
20.5
ns
21.5
36.2
ns
TA = 25°C,
TA = 70°C,
See Figures 5 and 6
23.6
32.6
ns
See Figures 5 and 6
24.4
33.4
ns
See Figures 5 and 6
td3, td4
MIN
A to B†
See Figures 5 and 6
8
ns
B to A
See Figures 5 and 6
9
ns
6
ns
tsk(lim)
Skew limit
tsk(p)
Pulse skew‡
tdis1
tdis2
Disable time, A to B
See Figures 3 and 4
200
ns
Disable time, B to A
See Figures 5 and 6
35
ns
ten1
ten2
Enable time, A to B
See Figures 3 and 4
65
ns
Enable time, B to A
See Figures 5 and 6
65
ns
ten(TX) Enable time, receive-to-transmit
See Figure 7
142
ns
† This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two devices.
‡ Pulse skew is the difference between the high-to-low and low-to-high propagation delay times of any single channel.
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
PARAMETER MEASUREMENT INFORMATION
5V
165 Ω
BDBn–
2 V or 0.8 V
ADBn –
VOD
75 Ω
VOH, VOL
VIH, VIL
BDBn +
165 Ω
VOH, VOL
NOTES: A. Resistance values are in ohms with a tolerance of ± 5%.
B. All input voltage levels are held to within 0.01 V.
C. The logical function is set with SDB at 0.8 V, DRVBUS at 3.5 V, and all others left open.
Figure 1. Differential Driver VOD, VOH, and VOL Test Circuit
BDBn –
II
VI
ADBn –
VID or VIT
BDBn +
IOH or IOL
VOL or VOL
NOTES: A. Resistance values are in ohms with a tolerance of ± 5%.
B. All input voltage levels are held to within 0.01 V.
C. The logical function is set with SDB and DRVBUS at 3.5 V, and all others left open.
Figure 2. Single-Ended Driver VOH, VOL, VIT +, and VIT – Test Circuit
8
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
PARAMETER MEASUREMENT INFORMATION
5V
165 Ω
BDBn +
ADBn –
75 Ω
50 pF
(see Note B)
Output
50 pF
Input (see Note A)
BDBn –
165 Ω
0.5 V
Input
Output
VOD(H)
~ – 0.925 V
VOD(L)
3V
1.5 V
0V
t0 or
t0
50%
ten td
td tdis
NOTES: A. The input pulse is supplied by a generator having the following
characteristics: PRR ≤ 1 MHz, 45% < duty cycle < 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. Resistance values are in ohms with a tolerance of ± 5%.
D. All input voltage levels are held to within 0.01 V.
Figure 3. A to B Propagation Delay Time Test Circuit
SDB
DSENS
RESET
ADBn –
DRVBUS
td1
td2
ten1
tdis1
BDBn –
BDBn +
VOD
Figure 4. A to B Timing Waveforms
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
PARAMETER MEASUREMENT INFORMATION
BDBn –
1.5 V
BDBn +
Input (see Note A)
ADBn –
Output
15 pF
(see Note B)
0.5 V
Input
Output
VOH
~ 2.5 V
1.5 V
3V
1.5 V
0V
t0 or t0
VOL
ten
td
td
tdis
NOTES: A. The input pulse is supplied by a generator having the following
characteristics: PRR ≤ 1 MHz, 45% < duty cycle < 50%, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. Resistance values are in ohms with a tolerance of ± 5%.
D. All input voltage levels are held to within 0.01 V.
Figure 5. B to A Propagation Delay Time Test Circuit
SDB
DSENS
RESET
BDBn –
DRVBUS
td3
td4
ten2
ADBn –
Figure 6. B to A Timing Waveforms
10
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tdis2
SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
PARAMETER MEASUREMENT INFORMATION
RESET
DRVBUS
BDB0 +
BDB0 –
ADB0 –
SDB
BDB1,2,3,4,5,7 +
ADB1,2,3,4,5,7–
and
BDB1,2,3,4,5,7 –
ADB6 –
BDB6 +
BDB6 –
ten(TX)
Output
Output
VOH
1.5 V
0V
BDB0 –
Input
ten(TX)
Input
≈3 V
1.5 V
BDB6 –
Output
VOL
Figure 7. Receive-to-Transmit (ten(TX)) Timing Waveforms
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
APPLICATION INFORMATION
SN75LBC970A
DIFFSENS
± BSY
± SEL
± RST
± I/O
± MSG
± C/D
± REQ
± ATN
± ACK
6
8
– BSY, – SEL, – I/O, – MSG,
– C/D, – REQ, – ATN, – ACK
8
– RST
20 kΩ
4
TEST
RSTFLTR
0.1 µF
CLK 40
(see Note A)
RESET
RESET
(from system)
X1/CLK20
20 MHz
(see Note A)
optional
(see Note B)
X2
SCSI
Controller
VCC
0.022 µF
TIMEOUT
DRVBUS
± DB(7 – 0)
± DBP(0)
16
SN75LBC971A
ADBn
BDBn
BDBP
ADBP–
DSENS
RESET
DRVBUS
± DBP(1)
DIFFSENS
8
2
DIFFSENS
± DB(15 – 8)
205 kΩ
SDB
16
2
– DB(7 – 0)
– DBP(0)
RESET
SDB
SN75LBC971A
BDBn
ADBn
BDBP
ADBP–
DSENS
RESET
8
– DB(15 – 8)
– DBP(1)
RESET
NOTES: A. When using the 40-MHz clock input, X1 must be connected to VCC.
B. The oscillator cell of the SN75LBC970A is for a series-resonant crystal and requires
approximately 10 pF (including fixture capacitance) from X1 and X2 to ground in order
to function.
Figure 8. Typical Application of the SN75LBC970A and SN75LBC971A
12
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SN75LBC971A
SCSI DIFFERENTIAL CONVERTER-DATA
SLLS186B – OCTOBER 1994 – REVISED JULY 1997
MECHANICAL INFORMATION
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
48
0.005 (0,13) M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°– 8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / C 03/97
NOTES: E.
F.
G.
H.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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13
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75LBC971ADL
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
SN75LBC971ADLR
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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