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SN75LVDS051D

SN75LVDS051D

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC16_150MIL

  • 描述:

    IC TRANSCEIVER FULL 2/2 16SOIC

  • 数据手册
  • 价格&库存
SN75LVDS051D 数据手册
SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 D D D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 155 Mbps Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100 Ω Load LVTTL Input Levels are 5 V Tolerant Driver is High Impedance When Disabled or With VCC < 1.5 V Receiver has Open-Circuit Fail Safe Surface-Mount Packaging – D Package (SOIC) Characterized For Operation From 0°C to 70°C description The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 155 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100 Ω load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are characterized for operation from 0°C to 70°C. SN75LVDS179D (Marked as DS179 or 7LS179) (TOP VIEW) VCC R D GND 1 8 2 7 3 6 4 5 3 A B Z Y D 5 6 8 2 R 7 Y Z A B SN75LVDS180D (Marked as 7LVDS180) (TOP VIEW) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC 5 10 D 4 DE 4 13 5 12 6 11 7 10 8 9 1Z DE 2Z 2Y 2D RE 12 2 R 3 1R 4 13 5 12 6 11 7 10 8 9 1Z 2DE 2Z 2Y 2D 11 14 13 10 11 2 1 4 RE 6 5 2R SN75LVDS051D (Marked as 75LVDS051) (TOP VIEW) 15 1D 1B 1 16 VCC 4 1DE 1A 2 15 1D 3 1R 1R 3 14 1Y 1DE 2R 2A 2B GND 9 2D 7 14 13 2 1 10 11 12 2DE 6 5 2R Y Z 3 SN75LVDS050D (Marked as 75LVDS050) 15 (TOP VIEW) 1D 12 1B 1 16 VCC DE 9 1A 2 15 1D 2D 1R 3 14 1Y RE 2R 2A 2B GND 9 7 A B 1Y 1Z 2Y 2Z 1A 1B 2A 2B 1Y 1Z 1A 1B 2Y 2Z 2A 2B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 Function Tables SN75LVDS179 RECEIVER INPUTS OUTPUT VID = VA – VB VID ≥ 100 mV R –100 MV < VID < 100 mV ? VID ≤ –100 mV Open H H L H = high level, L = low level, ? = indeterminate SN75LVDS179 DRIVER INPUT OUTPUTS D Y Z L L H H H L Open L H H = high level, L = low level SN75LVDS180, SN75LVDS050, and SN75LVDS051 RECEIVER INPUTS OUTPUT VID = VA – VB VID ≥ 100 mV RE R L H –100 MV < VID < 100 mV L ? VID ≤ –100 mV Open L L L H X H Z H = high level, L = low level, Z = high impedance, X = don’t care SN75LVDS180, SN75LVDS050, and SN75LVDS051 DRIVER INPUTS OUTPUTS D DE Y Z H L H L H H H L Open H L H X L Z Z H = high level, L = low level, Z = high impedance, X = don’t care 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 equivalent input and output schematic diagrams VCC VCC VCC 300 kΩ 50 Ω 5Ω 10 kΩ D or RE Input Y or Z Output 50 Ω DE Input 7V 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 7V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see dissipation rating table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C† TA = 70°C POWER RATING D8 725 mW 5.8 mW/°C 464 mW D14 or D16 950 mW 7.8 mW/°C 608 mW † This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 Low-level input voltage, VIL MAX UNIT 3.6 V V 0.8 Ť Ť Magnitude of differential input voltage, VID 0.1 V ID 2 Common–mode input voltage, VIC (see Figure 6) Operating free–air temperature, TA 4 2.4 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Ť Ť V 0.6 V * V2ID V VCC–0.8 70 °C SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 device electrical characteristics over recommended operating conditions (unless otherwise noted) TYP† MAX No receiver load, driver RL = 100 Ω 9 12 Driver and receiver enabled, No receiver load, Driver RL = 100 Ω 9 12 PARAMETER TEST CONDITIONS SN75LVDS179 SN75LVDS180 ICC Supply current SN75LVDS050 MIN Driver enabled, receiver disabled, RL = 100 Ω 5 7 Driver disabled, receiver enabled, No load 1.5 2 Disabled 0.5 1 Drivers and receivers enabled, no receiver loads, Driver RL = 100 Ω 12 20 Drivers enabled, receivers disabled, RL = 100 Ω 10 16 3 6 Disabled 0.5 1 Drivers enabled, no receiver loads, driver RL = 100 Ω 12 20 3 6 Drivers disabled, receivers enabled, no loads SN75LVDS051 Drivers disabled, No loads UNIT mA mA mA mA † All typical values are at 25°C and with a 3.3-V supply. driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOD Differential output voltage magnitude ∆VOD Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High level input current High-level IIL Low level input current Low-level IOS Short circuit output current Short-circuit VOY or VOZ = 0 V VOD = 0 V IOZ High impedance output current High-impedance VOD = 600 mV VO = 0 V or VCC IO(OFF) CIN Power-off output current VCC = 0 V, VO = 3.6 V 100Ω RL = 100Ω, See Figure 1 and Figure 2 MIN TYP MAX 247 340 454 –50 1.125 DE D DE D See Figure 3 VIH = 5 V VIL = 0 0.8 8V Input capacitance 50 1.2 –50 • DALLAS, TEXAS 75265 mV V 50 mV 50 150 mV – 0.5 – 20 2 20 – 0.5 –10 2 10 3 10 3 10 ±1 ±1 ±1 3 POST OFFICE BOX 655303 1.375 UNIT µA µA mA µA µA pF 5 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage II Input current (A or B inputs) II(OFF) IIH Power-off input current (A or B inputs) IIL IOZ Low-level input current (enables) See Figure 5 and Table 1 Negative-going differential input voltage threshold IOH = –8 mA IOL = 8 mA Low-level output voltage VI = 0 VI = 2.4 V High-level input current (enables) High-impedance output current MIN TYP† MAX 100 –100 2.4 UNIT mV V 0.4 –2 –11 –1.2 –3 –20 V µA VCC = 0 VIH = 5 V ±20 µA ±10 µA VIL = 0.8 V VO = 0 or 5 V ±10 µA ±10 µA CI Input capacitance † All typical values are at 25°C and with a 3.3-V supply. 5 pF driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output 6 ns Propagation delay time, high-to-low-level output 6 ns tr tf Differential output signal rise time 0.8 1.2 ns 0.8 1.2 ns 0.6 ps Channel-to-channel output skew§ Part-to-part skew¶ 0.6 ps 1 ps Propagation delay time, high-impedance-to-high-level output 25 ns Propagation delay time, high-impedance-to-low-level output 25 ns 25 ns tsk(p) tsk(o) tsk(pp) tPZH tPZL tPHZ RL = 100Ω, CL = 10 pF, See Figure 6 Differential output signal fall time Pulse skew (|tpHL – tpLH|)‡ Propagation delay time, high-level-to-high-impedance output See Figure 7 tpLZ Propagation delay time, low-level-to-high-impedance output 25 ns † All typical values are at 25°C and with a 3.3-V supply. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output § tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. ¶ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX 6 ns UNIT tPLH tPHL Propagation delay time, low-to-high-level output 2.1 Propagation delay time, high-to-low-level output 2.1 6 ns tr tf Output signal rise time 0.6 1.5 ns 0.7 1.5 ns tsk(p) tsk(o) Pulse skew (|tpHL – tpLH|)‡ tsk(pp) tPZH tPZL tPHZ F CL = 10 pF, See Figure 6 Output signal fall time 0.6 ns Channel-to-channel output skew§ Part-to-part skew¶ 0.6 ns 1 ns Propagation delay time, high-level-to-high-impedance output 25 ns Propagation delay time, low-level-to-low-impedance output 25 ns 25 ns See Figure 7 Propagation delay time, high-impedance-to-high-level output tPLZ Propagation delay time, low-impedance-to-high-level output 25 ns † All typical values are at 25°C and with a 3.3-V supply. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output ‡ tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. ‡ tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION driver IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY ) VOZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION driver (continued) Driver Enable Y VOD Input 100 Ω ±1% Z CL = 10 pF (2 Places) 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 49.9 Ω, ±1% (2 Places) Driver Enable 3V Y Input 0V Z VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VOC NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION driver (continued) 49.9 Ω, ±1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY VOZ 2V 1.4 V 0.8 V DE VOY or VOZ tPZH ~1.4 V 1.25 V 1.2 V D at 2 V and input to DE 1.2 V 1.15 V ~1 V D at 0.8 V and input to DE tPHZ VOZ or VOY tPZL tPLZ NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION receiver A V IA ) VIB R VID 2 VIA B VIC VO VIB Figure 5. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) 10 RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VIA 1.25 VIB 1.15 VID 100 VIC 1.2 1.15 1.25 – 100 1.2 2.4 2.3 100 2.35 2.3 2.4 – 100 2.35 0.1 0 100 0.05 0 0.1 – 100 0.05 1.5 0.9 600 1.2 0.9 1.5 – 600 1.2 2.4 1.8 600 2.1 1.8 2.4 – 600 2.1 0.6 0 600 0.3 0 0.6 – 600 0.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION receiver (continued) VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V – 0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 6. Timing Test Circuit and Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION receiver (continued) 1.2 V B 500 Ω A Inputs RE CL 10 pF + – VO VTEST NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST A 1V 2V 1.4 V RE 0.8 V tPZL tPZL tPLZ 2.5 V 1.4 V R VOL +0.5 V VOL 0V VTEST A 1.4 V 2V RE 1.4 V 0.8 V tPZH R tPZH tPHZ VOH 1.4 V VOH –0.5 V 0V Figure 7. Enable/Disable Time Test Circuit and Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 VIC – Common-Mode Input Voltage – V VCC > 3.15 V VCC = 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.5 0.4 0.3 0.6 |VID|– Differential Input Voltage – V Figure 8 DRIVER DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25°C VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 4 3 2 1 0 0 2 4 6 IOL – Low-Level Output Current – mA VCC = 3.3 V TA = 25°C 3 2.5 2 1.5 1 0.5 0 –4 –3 –2 –1 0 IOH – High-Level Output Current – mA Figure 9 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS RECEIVER RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C VOH – High-Level Output Voltage – V VOL – Low-Level Output Votlage – V 5 4 3 2 1 0 0 10 20 30 40 50 IOL – Low-Level Output Current – mA 60 3 2 1 0 –80 –40 –20 IOH – High-Level Output Current – mA Figure 12 Figure 11 14 –60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance – m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate – Mbps Figure 13. Data Transmission Distance Versus Rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 14. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt 100 Ω Typ Y B VIT ≈ 2.3 V Figure 14. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS179, SN75LVDS180, SN75LVDS050, SN75LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS361A – JUNE 1999 – REVISED MARCH 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN75LVDS051D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75LVDS051 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN75LVDS051D 价格&库存

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