SN75LVDS86DGGG4


    SLLS268D − MARCH 1997 − REVISED JULY 2006 D 3:21 Data Channel Expansion at up to D D D D D D D D D D D D 178.5 Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant SHTDN Input ESD Protection Exceeds 4 kV on Bus Pins Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz No External Components Required for PLL Open-Circuit Receiver Fail-Safe Design Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the Nationalt DS90C562 DGG PACKAGE (TOP VIEW) D17 D18 GND D19 D20 NC LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC D16 D15 D14 GND D13 VCC D12 D11 D10 GND D9 VCC D8 D7 D6 GND D5 D4 D3 VCC D2 D1 GND NC − Not Connected description The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors, and expansion to 21 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at seven times (7×) the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT). The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright  2006, Texas Instruments Incorporated      !"   #!$  % "& %!    #"  #" '" "  "(  !"   %% ) *& %!  #"+ %"  ""* !%" " +   #" "& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design, such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low level. This occurs even when the line is differentially terminated at the receiver inputs. The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0_C to 70_C. functional block diagram Serial-In/ParallelOut Shift Register A0P A0M Serial In CLK A, B, ...G Serial-In/ParallelOut Shift Register A1P A1M Serial In A, B, ...G CLK Serial-In/ParallelOut Shift Register Serial In Input Bus A2P A2M D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 A, B, ...G CLK Control Logic SHTDN D14 D15 D16 D17 D18 D19 D20 7× Clock/PLL CLKINP CLKINM 2 CLK Clock In POST OFFICE BOX 655303 Clock Out • DALLAS, TEXAS 75265 CLKOUT 

    CLKIN ÇÇ ÇÇ ÉÉÉ ÉÉÉ Previous Cycle D0−1 D6 A1 D7−1 A2 D14−1 ÇÇ ÇÇ ÇÇ ÇÇ ÉÉ ÉÉ Current Cycle A0 CLKOUT SLLS268D − MARCH 1997 − REVISED JULY 2006 Next Cycle D5 D4 D3 D2 D1 D0 D6+1 D13 D12 D11 D10 D9 D8 D7 D13+1 D20 D19 D18 D17 D16 D15 D14 D20+1 ÉÉ ÉÉ ÇÇ ÇÇ Dn − 1 D0 ÇÇÇ ÇÇÇ ÉÉ ÉÉ ÇÇ ÇÇ Dn Dn + 1 Figure 1. SN75LVDS86 Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC 300 kΩ VCC 300 kΩ 5Ω D Output AnM AnP VCC 7V 7V 7V SHTDN 50 Ω INPUT OUTPUT 7V INPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Output voltage range, VO (Dxx terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input voltage range, VI: Any terminal except SHTDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V SHTDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Lead temperature 1,6 mm (1/16 in) from case for 10 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND, unless otherwise noted. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1316 mW 13.1 mW/°C 726 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. recommended operating conditions (see Figure 2) MIN Supply voltage, VCC 3 High-level input voltage, VIH (SHTDN) 2 NOM MAX UNIT 3.6 V 3.3 V Low-level input voltage, VIL (SHTDN) 0.8 Differential input voltage, |VID| 0.1 |V ID 2 Common-mode input voltage, VIC (see Figure 2 and Figure 3) Operating free-air temperature, TA V 0.6 | 2.4 * V |V ID 2 | VCC − 0.8 70 0 V °C timing requirements MIN NOM MAX UNIT tc Cycle time, input clock§ 14.7 tc 32.4 ns tsu1 Setup time, input (see Figure 7) 600 ps 600 ps th1 Hold time, input (see Figure 7) § Parameter tc is defined as the mean duration of a minimum of 32 000 clock cycles. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input threshold voltage VIT− Negative-going differential input threshold voltage‡ VOH VOL High-level output voltage ICC IIH IIL High-level input current (SHTDN) II IOZ Input current (LVDS input terminals A and CLKIN) Low-level input current (SHTDN) MAX UNIT 100 mV mV 2.4 Disabled, All inputs open Enabled, AnM = 1.4 V, AnP = 1 V, tc = 15.38 ns V 58 Enabled, CL = 8 pF, Grayscale pattern (see Figure 4), tc = 15.38 ns Enabled, CL = 8 pF, Worst-case pattern (see Figure 5), tc = 15.38 ns VIH = VCC Quiescent current (average) TYP† −100 IOH = − 4 mA IOL = 4 mA Low-level output voltage MIN 0.4 V 280 µA 72 69 mA 94 VIL = 0 V 0 ≤ VI ≤ 2.4 V ±20 µA ±20 µA ±20 µA High-impedance output current VO = 0 or VCC ±10 µA † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tsu2 th2 Set up time, D0−D20 valid to CLKOUT↓ CL = 8 pF, See Figure 6 5 ns Hold time, CLKOUT↓ to D0−D20 valid CL = 8 pF, See Figure 6 5 ns tRSKM Receiver input skew margin§ (see Figure 7) tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps¶ 490 ps td Delay time, CLKIN↑ to CLKOUT↓ (see Figure 7) tc = 15.38 ns (± 0.2%), CL = 8 pF 3.7 ± 80 Cycle time, change in output clock period# tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns, See Figure 8 tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns, See Figure 8 ± 300 ∆ tc(o) ten Enable time, SHTDN↑ to Dn valid See Figure 9 tdis Disable time, SHTDN↓ to off state See Figure 10 tt tw Transition time, output (10% to 90% tr or tf) CL = 8 pF Pulse duration, output clock ns ps 1 ms 400 ns 3 ns 0.43 tc ns † All typical values are at VCC = 3.3 V, TA = 25°C. tc § The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by 14 * t su1 ńt h1. ¶ |Input clock jitter| is the magnitude of the change in input clock period. # ∆ tc(o) is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION AP VID VIAP (VIAP + VIAM)/2 AM VIC VIAM Figure 2. Voltage Definitions VIC − Common-Mode Input Voltage − V 2.5 Maximum at VCC >3.15 V Maximum at VCC = 3 V 2 1.5 1 0.5 Minimum 0 0 0.1 0.2 0.3 0.4 0.5 0.6 | VID | − Differential Input Voltage − V Figure 3. Common-Mode Input Voltage Vs Differential Input Voltage and VCC 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION CLKIN D0, D6, D12 D1, D7, D13 D2, D8, D14 D3, D9, D15 D18, D19, D20 All Others NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern Figure 4. 16-Grayscale Test Pattern tc CLKIN/CLKOUT Even Dn Odd Dn NOTE B: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs. Figure 5. Worst-Case Test Pattern tsu2 70% VOH D0 −D20 30% VOH th2 70% VOH CLKOUT 30% VOH Figure 6. Setup and Hold Time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION Tektronixt HFS9003/HFS9DG1 Stimulus System (repeating patterns of 1110111 and 0001000) An D0−D27 Device Under Test (DUT) CLKIN Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector CLKOUT tc 4 t ±t 7 c (RSKM) (see Note A) tsu1 3 t t ± 7 c (RSKM) (see Note A) An and An th1 ÉÉÉÇÇ ÉÉÉÇÇ ÇÇÇÉÉ ÇÇÇÉÉ ÉÉÉÇÇ ÉÉÉÇÇ ÇÇÇÉÉ ÇÇÇÉÉ CLKIN 7× CLK (Internal) td tW CLKOUT tr < 1 ns 80% CLKIN or An ≈ 300 mV 0V 20% ≈ −300 mV tW td VOH 1.4 V VOL CLKOUT NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed. The magnitude of the advance or delay is t(RSKM). Figure 7. Receiver Input Skew Margin, Setup/Hold Time, and Delay Timing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz to 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz to 4200 MHz Device Under Test Output RF OUTPUT CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 8. Output Clock Jitter Test Setup CLKIN An ten SHTDN ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Dn Invalid Valid Figure 9. Enable Time CLKIN tdis SHTDN CLKOUT Figure 10. Disable Time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 80 75 I CC − Supply Current − mA VCC = 3.6 V 70 65 60 VCC = 3.3 V 55 50 45 Grayscale Data Pattern CL = 8 pF TA = 25°C VCC = 3 V 40 30 40 50 60 70 fclk − Clock Frequency − MHz Figure 11. RMS Grayscale ICC vs Clock Frequency ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 300 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25°C Zero-to-Peak Output Jitter − ps 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 f(mod) − Modulation Frequency − MHz Figure 12. Typical FlatLinkt PLL Characteristics 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS84/5 Y0M 41 8 A0M 100 Ω Y0P Y1M 40 9 39 10 A0P A1M 100 Ω Y1P Y2M 38 11 35 14 A1P A2M 100 Ω Y2P CLKOUTM 34 15 33 16 A2P CLKINM 100 Ω CLKOUTP Graphics Controller SN75LVDS86 32 17 CLKINP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKOUT 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA − not applicable, these unused inputs should be left open. Figure 13. 18-Bit Color Host to Flat Panel Display Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

    SLLS268D − MARCH 1997 − REVISED JULY 2006 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS81/83 Y0M 48 8 A0M 100 Ω Y0P Y1M 47 9 46 10 A0P A1M 100 Ω Y1P Y2M 45 11 42 14 A1P A2M 100 Ω Y2P 41 15 40 16 CLKOUTM A2P CLKINM 100 Ω CLKOUTP Y3M Y3P Graphics Controller SN75LVDS86 39 17 CLKINP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKOUT 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 38 37 NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA − not applicable, these unused inputs should be left open. Figure 14. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application† † See the FlatLinkt Designer’s Guide (SLLA012) for more application information. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN75LVDS86DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 SN75LVDS86 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of