SN761644
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SLES252 – NOVEMBER 2009
DIGITAL TV TUNER IC
Check for Samples: SN761644
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Mixer/Oscillator/PLL and IF GCA
Mirror Pin Package of SN761640
VHF-L, VHF-H, UHF 3-Band Local Oscillator
RF AGC Detector Circuit
I2C Bus Protocol
Bidirectional Data Transmission
High-Voltage Tuning Voltage Output
Four NPN-Type Band Switch Drivers
One Auxiliary Port/5-Level ADC
Crystal Oscillator Output
Programmable Reference Divider Ratio
(24/28/32/64/80/128)
IF GCA Enable/Disable Control
Selectable digital IFOUT and Analog IFOUT
Standby Mode
5-V Power Supply
44-Pin Thin Shrink Small-Outline Package
(TSSOP)
APPLICATIONS
•
•
•
Digital TVs
Digital CATVs
Set-Top Boxes
DBT PACKAGE
(TOP VIEW)
BS4
UHF RF IN1
UHF RF IN2
VHI RF IN
VLO RF IN
RF GND
MIX OUT2
MIX OUT1
IF IN
RF AGC OUT
RF AGC BUF
BS3
BS2
BS1
SDA
SCL
AS
BUS GND
P5/ADC
XTAL OUT
XTAL2
XTAL1
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
VLO OSCB
VLO OSC C
VHI OSC B
VHI OSC C
UHF OSC B1
UHF OSC C1
UHF OSC C2
UHF OSC B2
OSC GND
CP
VTU
IF GND
AIF OUT
DIF OUT1
DIF OUT2
IF GCA CTRL
VCC
IF GCA IN1
IF GCA IN2
IF GCA GND
IF GCA OUT2
IF GCA OUT1
DESCRIPTION
The SN761644 is a low-phase-noise synthesized tuner IC designed for digital TV tuning systems. The circuit
consists of a PLL synthesizer, three-band local oscillator and mixer, RF AGC detector circuit, and IF
gain-controlled amplifier. The SN761644 is available in a small-outline package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN761644
SLES252 – NOVEMBER 2009
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VHF-L
Oscillator
VHF-H
Oscillator
IF IN
MIX OUT2
MIX OUT1
UHF OSC C2
UHF OSC B2
UHF OSC B1
UHF OSC C1
VHI OSC C
VHI OSC B
OSC GND
VLO OSC C
VLO OSC B
FUNCTIONAL BLOCK DIAGRAM
IF
Amplifier
UHF
Oscillator
DIF OUT1
DIF OUT2
AIF OUT
VLO RF IN
VHF-L
Mixer
VHF-H
Mixer
IF GND
UHF
Mixer
RF AGC OUT
RF
AGC
Detect
VHI RF IN
RF AGC BUFF
UHF RF IN1
UHF RF IN2
CP
Programmable
Divider
RF GND
XTAL1
XTAL2
VTU
Operational
Amplifier
XTAL
Oscillator
128/80/64/50/
28/24 Div
Phase
Detector
Charge
Pump
VCC
XTAL OUT
NPN Band-Switch Port
SCL
SDA
2
I C Bus
Interface
IF
GCA
IF GCA OUT2
AS
IF GCA GND
2
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IF GCA CTRL
IF GCA IN1
IF GCA IN2
BS1
BS2
BS3
BS4
5-Level
ADC
P5/ADC
BUS GND
IF GCA OUT1
Copyright © 2009, Texas Instruments Incorporated
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SN761644
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SLES252 – NOVEMBER 2009
TERMINAL FUNCTIONS
Table 1.
TERMINAL
NAME
DESCRIPTION
NO.
SCHEMATIC
AIF OUT
32
IF amplifier output (analog)
Figure 8
AS
17
Address selection input
Figure 1
BS1
14
Band switch 1 output
Figure 2
BS2
13
Band switch 2 output
Figure 2
BS3
12
Band switch 3 output
Figure 2
BS4
1
Band switch 4 output
Figure 2
BUS GND
18
BUS ground
CP
35
Charge-pump output
Figure 3
DIF OUT1
31
IF amplifier output 1
Figure 9
DIF OUT2
30
IF amplifier output 2
Figure 9
IF GCA CTRL
29
IF GCA CTRL voltage inout
Figure 4
IF GCA GND
25
IF GCA ground
IF GCA IN1
27
IF GCA input 1
Figure 5
IF GCA IN2
26
IF GCA input 2
Figure 5
IF GCA OUT1
23
IF GCA output 1
Figure 6
IF GCA OUT2
24
IF GCA output 2
Figure 6
IF GND
33
IF ground
IF IN
9
IF amplifier input
Figure 7
MIXOUT1
8
Mixer output 1
Figure 10
MIXOUT2
7
Mixer output 2
Figure 10
OSC GND
36
Oscillator ground
P5/ADC
19
Port-5 output/ADC input
Figure 11
RF AGC BUF
11
RF AGC buffer output
Figure 12
RF AGC OUT
10
RF AGC output
Figure 13
RF GND
6
RF ground
SCL
16
Serial clock input
Figure 14
SDA
15
Serial data input/output
Figure 15
UHF OSC B1
40
UHF oscillator base 1
Figure 16
UHF OSC B2
37
UHF oscillator base 2
Figure 16
UHF OSC C1
39
UHF oscillator collector 1
Figure 16
UHF OSC C2
38
UHF oscillator collector 2
Figure 16
UHF RF IN1
2
UHF RF input 1
Figure 17
UHF RF IN2
3
UHF RF input 2
Figure 17
VCC
28
Supply voltage
VHI OSC B
42
VHF-H oscillator base
Figure 18
VHI OSC C
41
VHF-H oscillator collector
Figure 18
VHI RF IN
4
VHF-H RF input
Figure 19
VLO OSC B
44
VHF-L oscillator base
Figure 20
VLO OSC C
43
VHF-L oscillator collector
Figure 20
VLO RF IN
5
VHF-L RF input
Figure 21
VTU
34
Tuning voltage amplifier output
Figure 3
XTAL1
22
4-MHz crystal oscillator
Figure 22
XTAL2
21
4-MHz crystal oscillator
Figure 22
XTALOUT
20
4-MHz crystal oscillator buffer output
Figure 23
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SN761644
SLES252 – NOVEMBER 2009
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100k
500
1
17
10
12
50k
13
14
Figure 1. AS
Figure 2. BS1, BS2, BS3, and BS4
1k
34
29
100k
25
35
25
Figure 3. CP and VTU
Figure 4. IF GCA CTRL
Vbias
1k
1k
26
27
15
23
24
Figure 5. IF GCA IN1 and IF GCA IN2
Figure 6. IF GCA OUT1 and IF GCA OUT2
2k
25
1k
A
10
32
25
1k
9
1k
Figure 7. IF IN
Figure 8. AIF OUT
25
7
25
8
10
A
30
31
Figure 9. DIF OUT1 and DIF OUT2
4
Figure 10. MIXOUT1 and MIXOUT2
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SLES252 – NOVEMBER 2009
25
25
50
11
19
Figure 11. P5/ADC
Figure 12. RF AGC BUF
10
1k
16
Figure 13. RF AGC OUT
Figure 14. SCL
38
25
39
1k
15
20
20
37
40
8k
8k
Figure 15. SDA
2
Figure 16. UHF OSC B1, UHF OSC B2, UHF OSC
C1, and UHF OSC C2
41
3
40
3k
42
8k
8k
Figure 17. UHF RF IN1 and UHF RF IN2
Figure 18. VHI OSC B and VHI OSC C
43
4
20
3k
44
8k
8k
Figure 19. VHI RF IN
Figure 20. VLO OSC B and VLO OSC C
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22
21
5
10
20
3k
50k
Figure 21. VLO RF IN
Figure 22. XTAL1 and XTAL2
50
20
Figure 23. XTALOUT
6
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SLES252 – NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS (1)
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
(2)
VCC
–0.4
6.5
V
VGND
Input voltage range 1
(2)
RF GND, OSC GND
–0.4
0.4
V
VVTU
Input voltage range 2
(2)
VTU
–0.4
35
V
VIN
Input voltage range 3
(2)
Other pins
–0.4
PD
Continuous total dissipation
TA
Operating free-air temperature range
–20
85
°C
Tstg
Storage temperature range
–65
150
°C
TJ
Maximum junction temperature
150
°C
tSC(max)
Maximum short-circuit time
10
s
(1)
(2)
(3)
(3)
TA ≤ 25°C
6.5
1438
Each pin to VCC or to GND
UNIT
V
mW
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the IF GND of the circuit.
Derating factor is 11.5 mW/°C for TA ≥ 25°C.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
VCC
VVTU
Tuning supply voltage
VTU
IBS
Output current of band switch
BS1 – BS4, one band switch on
IP5
Output current of port 5
P5/ADC
TA
Operating free-air temperature
4.5
–20
NOM
MAX
UNIT
5
5.5
30
33
V
10
mA
–5
mA
85
°C
V
xxx
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause
damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated
circuits may be more susceptible to damage because very small parametric chagnes could cause the device not
to meet its published specifications.
IF IN1, MIXOUT1, and MIXOUT2 (pins 7–9) withstand 1.5 kV, and all other pins withstand 2 kV, according to the
Human-Body Model (1.5 kΩ, 100 pF).
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ELECTRICAL CHARACTERISTICS
Total Device and Serial Interface
VCC = 4.5 V to 5.5 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
Supply current 1
BS[1:4] = 0100, IFGCA disabled
90
120
mA
ICC2
Supply current 2
BS[1:4] = 0100, IFGCA enabled
115
145
mA
ICC3
Supply current 3
BS[1:4] = 0100, IFGCA enabled,
IBS = 10 mA
125
155
mA
ICC-STBY
Standby supply current
BS[1:4] = 1100
VIH
High-level input voltage (SCL, SDA)
VIL
Low-level input voltage (SCL, SDA)
IIH
High-level input current (SCL, SDA)
IIL
Low-level input current (SCL, SDA)
–10
VPOR
Power-on-reset supply voltage (threshold of supply
voltage between reset and operation mode)
2.1
9
mA
2.3
V
1.05
V
10
μA
μA
2.8
3.5
V
I2C Interface
VASH
Address-select high-input voltage (AS)
VCC = 5 V
4.5
5
V
VASM1
Address-select mid-input 1 voltage (AS)
VCC = 5 V
2
3
V
VASM2
Address-select mid-input 2 voltage (AS)
VCC = 5 V
1
1.5
V
VASL
Address-select low-input voltage (AS)
VCC = 5 V
IASH
Address-select high-input current (AS)
IASL
Address-select low-input current (AS)
VADC
ADC input voltage
See Table 11
IADH
ADC high-level input current
VADC = VCC
IADL
ADC low-level input current
VADC = 0 V
VOL
Low-level output voltage (SDA)
VCC = 5 V, IOL = 3 mA
0.4
V
lSDAH
High-level output leakage current (SDA)
VSDA = 5.5 V
10
μA
fSCL
Clock frequency (SCL)
400
kHz
tHD-DAT
Data hold time
0.9
μs
tBUF
Bus free time
1.3
μs
tHD-STA
Start hold time
0.6
μs
tLOW
SCL-low hold time
1.3
μs
tHIGH
SCL-high hold time
0.6
μs
tSU-STA
Start setup time
0.6
μs
tSU-DAT
Data setup time
0.1
μs
tr
Rise time (SCL, SDA )
0.3
μs
tf
Fall time (SCL, SDA)
0.3
μs
tSU-STO
Stop setup time
8
0.5
V
50
μA
μA
–10
0
0
0.6
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V
10
μA
μA
–10
100
See Figure 24
VCC
μs
Copyright © 2009, Texas Instruments Incorporated
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SLES252 – NOVEMBER 2009
PLL and Band Switch
VCC = 4.5 V to 5.5 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
N
Divider ratio
15-bit frequency word
fXTAL
Crystal oscillator frequency
RXTAL = 25 Ω to 300 Ω
ZXTAL
Crystal oscillator input impedance
VXLO
XTALOUT output voltage
Load = 10 pF/5.1 kΩ, VCC = 5 V,
TA = 25°C
VVTUL
Tuning amplifier low-level output voltage
RL = 20 kΩ, VTU = 30 V
IVTUOFF
Tuning amplifier leakage current
Tuning amplifier = off, VTU = 30 V
ICP10
Charge-pump current
TYP
512
0.2
0.48
Vp-p
0.3
CP[2:0] = 010
350
CP[2:0] = 001
140
ICP00
CP[2:0] = 000
ICP100
CP[2:0] = 100, Mode = 1
900
1.95
PLL locked
ICPOFF
Charge-pump leakage current
VCP = 2 V, TA = 25°C
IBS
Band switch driver output current (BS1–BS4)
VBS1
VBS2
Band switch driver output voltage (BS1–BS4)
IBSOFF
Band switch driver leakage current
(BS1–BS4)
IP5
Band switch port sink current (P5/ADC)
VP5ON
Band switch port output voltage (P5/ADC)
MHz
kΩ
600
Charge-pump output voltage
UNIT
2.4
CP[2:0] = 011
VCP
MAX
32767
4
1.6
ICP11
ICP01
MIN
0.46
V
10
μA
μA
70
–15
IBS = 10 mA
V
15
nA
10
mA
3
IBS = 10 mA, VCC = 5 V, TA = 25°C
3.5
V
3.7
8
μA
–5
mA
0.6
V
VBS = 0 V
IP5 = –2 mA, VCC = 5 V, TA = 25°C
RF AGC (1)
VCC = 5 V, TA = 25°C, measured in Figure 25 reference measurement circuit at 50-Ω system, IF = 44 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
IOAGC0
IOAGC1
TEST CONDITIONS
MIN
ATC = 0
RF AGCOUT output source current
TYP
MAX
UNIT
300
nA
μA
ATC = 1
9
IOAGCSINK
RF AGCOUT peak output sink current
ATC = 0
100
VOAGCH
RFAGCOUT output high voltage (max level)
ATC = 1
VOAGCL
RFAGCOUT output low voltage (min level)
ATC = 1
0.3
V
IAGCBUF
RFAGCBUF output current
ATC = 0
1.5
mA
VOAGCBFH
RFAGCBUF output high voltage (max level)
ATC = 1
VOAGCBFL
RFAGCBUF output low voltage (min level)
ATC = 1
0.3
VAGCSP00
ATP[2:0] = 000
114
VAGCSP01
ATP[2:0] = 001
112
VAGCSP02
ATP[2:0] = 010
110
VAGCSP03
3.5
4
4
ATP[2:0] = 011
108
VAGCSP04
ATP[2:0] = 100
106
VAGCSP05
ATP[2:0] = 101
104
VAGCSP06
ATP[2:0] = 110
102
(1)
Start-point IF output level
3.5
μA
4.5
V
4.5
V
V
dBμV
When AISL=1, RF AGC function is not available at VHF-L band (output level is undefined).
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Mixer, Oscillator, IF Amplifier (DIF OUT)
VCC = 5 V, TA = 25°C, measured in Figure 25 reference measurement circuit at 50-Ω system, IF = 44 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
GC1D
Conversion gain (mixer-IF amplifier), VHF-LOW
GC3D
GC4D
Conversion gain (mixer-IF amplifier), VHF-HIGH
GC6D
GC7D
Conversion gain (mixer-IF amplifier), UHF
GC9D
NF1D
Noise figure, VHF-LOW
NF3D
NF4D
NF7D
CM1D
CM3D
CM4D
CM6D
CM7D
VIFO1D
VIFO4D
VIFO7D
ΦPLVL1D
ΦPLVL3D
ΦPLVL4D
ΦPLVL6D
ΦPLVL7D
ΦPLVL9D
10
35
fin = 467 MHz (1)
35
fin = 473 MHz (1)
35
fin = 864 MHz (1)
35
fin = 57 MHz
9
fin = 171 MHz
9
10
fin = 864 MHz
12
Input voltage causing 1% cross-modulation distortion,
VHF-LOW
fin = 57 MHz (2)
79
fin = 171 MHz (2)
79
Input voltage causing 1% cross-modulation distortion,
VHF-HIGH
fin = 177 MHz (2)
79
fin = 467 MHz (2)
79
fin = 473 MHz (2)
77
(2)
77
IF output voltage, UHF
VIFO9D
fin = 177 MHz (1)
fin = 473 MHz
IF output voltage, VHF-HIGH
VIFO6D
35
9
IF output voltage, VHF-LOW
VIFO3D
35
fin = 171 MHz (1)
10
Input voltage causing 1% cross-modulation distortion, UHF
CM9D
TYP
fin = 467 MHz
Noise figure, UHF
NF9D
fin = 57 MHz
(1)
fin = 177 MHz
Noise figure, VHF-HIGH
NF6D
(1)
(2)
(3)
(4)
TEST CONDITIONS
Phase noise, VHF-LOW
Phase noise, VHF-HIGH
Phase noise, UHF
fin = 864 MHz
fin = 57 MHz
117
fin = 171 MHz
117
fin = 177 MHz
117
fin = 467 MHz
117
fin = 473 MHz
117
fin = 864 MHz
117
fin = 57 MHz (3)
–90
fin = 171 MHz (4)
–85
fin = 177 MHz (3)
–85
(4)
–77
fin = 473 MHz (3)
–80
fin = 864 MHz (4)
–77
fin = 467 MHz
UNIT
dB
dB
dB
dB
dB
dB
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBc/Hz
dBc/Hz
dBc/Hz
IF = 44 MHz, RF input level = 70 dBμV, differential output
fundes = fdes ±6 MHz, Pin = 70 dBμV, AM 1 kHz, 30%, DES/CM = S/I = 46 dB
Offset = 1 kHz, CP current = 350 μA, reference divider = 64
Offset = 1 kHz, CP current = 900 μA, reference divider = 64
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Mixer, Oscillator, IF Amplifier (AIF OUT)
VCC = 5 V, TA = 25°C, measured in Figure 25 reference measurement circuit at 50-Ω system, IF = 45.75 MHz,
IF filter characteristics: fpeak = 44 MHz (unless otherwise noted)
PARAMETER
GC1A
GC3A
GC4A
GC6A
GC7A
GC9A
NF1A
NF3A
NF4A
NF6A
NF7A
NF9A
CM1A
CM3A
CM4A
CM6A
CM7A
CM9A
VIFO1A
VIFO3A
VIFO4A
VIFO6A
VIFO7A
VIFO9A
ΦPLVL1A
ΦPLVL3A
ΦPLVL4A
ΦPLVL6A
ΦPLVL7A
ΦPLVL9A
(1)
(2)
(3)
TEST CONDITIONS
Conversion gain (mixer-IF amplifier), VHF-LOW
Conversion gain (mixer-IF amplifier), VHF-HIGH
Conversion gain (mixer-IF amplifier), UHF
Noise figure, VHF-LOW
fin = 55.25 MHz
(1)
TYP
29
fin = 169.25 MHz (1)
29
fin = 175.25 MHz (1)
29
fin = 465.25 MHz (1)
29
fin = 471.25 MHz (1)
29
fin = 862.25 MHz (1)
29
fin = 55.25 MHz
9
fin = 169.25 MHz
9
fin = 175.25 MHz
9
fin = 465.25 MHz
10
fin = 471.25 MHz
10
fin = 862.25 MHz
12
Input voltage causing 1% cross-modulation distortion,
VHF-LOW
fin = 55.25 MHz (2)
79
fin = 169.25 MHz (2)
79
Input voltage causing 1% cross-modulation distortion,
VHF-HIGH
fin = 175.25 MHz (2)
79
fin = 465.25 MHz (2)
79
fin = 471.25 MHz (2)
79
(2)
77
Noise figure, VHF-HIGH
Noise figure, UHF
Input voltage causing 1% cross-modulation distortion, UHF
IF output voltage, VHF-LOW
IF output voltage, VHF-HIGH
IF output voltage, UHF
Phase noise, VHF-LOW
Phase noise, VHF-HIGH
Phase noise, UHF
fin = 862.25 MHz
fin = 55.25 MHz
117
fin = 169.25 MHz
117
fin = 175.25 MHz
117
fin = 465.25 MHz
117
fin = 471.25 MHz
117
fin = 862.25 MHz
117
fin = 55.25 MHz (3)
–95
fin = 169.25 MHz (3)
–95
fin = 175.25 MHz (3)
–90
(3)
–90
fin = 471.25 MHz (3)
–85
fin = 862.25 MHz (3)
–90
fin = 465.25 MHz
UNIT
dB
dB
dB
dB
dB
dB
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBc/Hz
dBc/Hz
dBc/Hz
IF = 44 MHz, RF input level = 70 dBμV
fundes = fdes ±6 MHz, Pin = 70 dBμV, AM 1 kHz, 30%, DES/CM = S/I = 46 dB
Offset = 10 kHz, CP current = 70 μA, reference divider = 128
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IF Gain Controlled Amplifier
VCC = 5 V, TA = 25°C, measured in Figure 25 reference measurement circuit at 50-Ω system, IF = 44 MHz
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIFGCA
Input current (IF GCA CTRL)
VIFGCA = 3 V
60
μA
VIFGCAMAX
Maximum gain control voltage
Gain maximum
3
VCC
V
VIFGCAMIN
Minimum gain control voltage
Gain minimum
0
0.2
GIFGCAMAX
Maximum gain
VIFGCA = 3 V
65
dB
GIFGCAMIN
Minimum gain
VIFGCA = 0 V
–1
dB
GCRIFGCA
Gain control range
VIFGCA = 0 V to 3 V
66
dB
VIFGCAOUT
Output voltage
Single-ended output,
VIFGCA = 3 V
2.1
Vp-p
NFIFGCA
Noise figure
VIFGCA = 3 V
11
dB
IM3IFGCA
Third order intermodulation distortion
fIFGCAIN1 = 43 MHz,
fIFGCAIIN2 = 44 MHz,
VIFGCAOUT = –2 dBm,
VIFGCA = 3 V
–50
dBc
IIP3IFGCA
Input intercept point
VIFGCA = 0 V
11
dBm
RIFGCAIN
Input resistance (IF GCA IN1, IF GCA IN2)
1
kΩ
RIFGCAOUT
Output resistance (IF GCA OUT1, IF GCA OUT2)
25
Ω
12
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FUNCTIONAL DESCRIPTION
I2C Bus Mode
I2C Write Mode (R/W = 0)
Table 2. Write Data Format
MSB
LSB
Address byte (ADB)
1
1
0
0
0
MA1
MA0
R/W = 0
A (1)
Divider byte 1 (DB1)
0
N14
N13
N12
N11
N10
N9
N8
A (1)
Divider byte 2 (DB2)
N7
N6
N5
N4
N3
N2
N1
N0
A (1)
Control byte 1 (CB1)
1
0
ATP2
ATP1
ATP0
RS2
RS1
RS0
A (1)
CP1
CP0
AISL
P5
BS4
BS3
BS2
BS1
A (1)
1
1
ATC
MODE
T3/DISGCA
T2/IFDA
T1/CP2
T0/XLO
A (1)
Band switch byte (BB)
Control byte 2 (CB2)
(1)
A : acknowledge
Table 3. Write Data Symbol Description
SYMBOL
DESCRIPTION
MA[1:0]
Address-set bits (see Table 4)
N[14:0]
Programmable counter set bits
DEFAULT
N14 = N13 = N12 = ... = N0 = 0
N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0
ATP[2:0]
RF AGC start-point control bits (see Table 5)
ATP[2:0] = 000
RS[2:0]
Reference divider ratio-selection bits (see Table 6)
RS[2:0] = 000
CP[1:0]
Charge-pump current-set bit (see Table 7)
CP[1:0] = 00
AISL (1)
RF AGC detector input selection bit
AISL = 0
AISL = 0: IF amplifier
AISL = 1: Mixer output
P5
Port output/ADC input control bit
P5 = 0
P5 = 0: ADC INPUT
P5 = 1: Tr = ON
BS[4:1]
Band switch control bits
BSn = 0
BSn = 0: Tr = OFF
BSn = 1: Tr = ON
Band selection by BS[1:2]
ATC
BS1
BS2
1
0
0
1
0
1
0
1
VHF-LO
VHF-HI
UHF
Standby mode/stop MOP function (XTALOUT is available in standby
mode)
RF AGC current-set bit
ATC = 0
ATC = 0: Current = 300 nA
ATC = 1: Current = 9 μA
Mode
T3/DISGCA
T2/IFDA
T1/CP2
T0/XLO
(1)
Mode
=0:
IFGCA enabled, DIFOUT1, 2 selected
MODE = 0
T3/DISGCA, T2/IFDA, T1/CP2, T0/XLO are Test bits and XTALOUT control bit T[3:0] = 0000
(see Table 8)
Mode
=1
T3/DISGCA = 0 : IF GCA enabled
T3/DISGCA = 1 : IF GCA disabled
T2/IFDA = 0 : DIFOUT1, 2 selected
T2/IFDA = 1 : AIFOUT selected
T1/CP2 : lcp control bit, See Table 7
T0/XLO = 0 : XTALOUT enabled
T0/XLO = 1 : XTALOUT disabled
When AISL = 1, RF AGC function is not available at VHF-L band (Output level is undefined.)
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Table 4. Address Selection
MA1
MA0
VOLTAGE APPLIED ON AS INPUT
0
0
0 V to 0.1 VCC (Low)
0
1
OPEN, or 0.2 VCC to 0.3 VCC (Mid2)
1
0
0.4 VCC to 0.6 VCC (Mid1)
1
1
0.9 VCC to VCC (High)
Table 5. RF AGC Start Point (1)
(1)
ATP2
ATP1
ATP0
IFOUT LEVEL (dBμV)
0
0
0
114
0
0
1
112
0
1
0
110
0
1
1
108
1
0
0
106
1
0
1
104
1
1
0
102
1
1
1
Disabled
When AISL=1, RF AGC function is not available at VHF-L band (output level is undefined).
Table 6. Reference Divider Ratio
RS2
RS1
RS0
REFERENCE DIVIDER RATIO
0
0
0
24
0
0
1
28
0
1
0
32
0
1
1
64
1
0
0
128
1
X
1
80
Table 7. Charge-Pump Current
14
MODE
CP2
CP1
CP0
CHARGE PUMP CURRENT
(μA)
X
0
0
0
70
X
0
0
1
140
X
0
1
0
350
X
0
1
1
600
1
1
0
0
900
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Table 8. Test Bits/XTALOUT Control
(1)
(1)
XTALOUT
4-MHz OUTPUT
MODE
T3/DISGCA
T2/IFDA
T1/CP2
T0/XLO
DEVICE OPERATION
0
0
0
0
0
Normal operation
Enabled
0
0
0
0
1
Normal operation
Disabled
1
X
X
X
0
Normal operation
Enabled
1
X
X
X
1
Normal operation
Disabled
0
X
1
X
X
Test mode
Not available
0
1
X
X
X
Test mode
Not available
RFAGC and XTALOUT are not available in test mode.
I2C Read Mode (R/W = 1)
Table 9. Read Data Format
MSB
Address byte (ADB)
Status byte (SB)
(1)
LSB
1
1
0
0
0
MA1
MA0
R/W = 1
A (1)
POR
FL
1
1
X
A2
A1
A0
–
A : acknowledge
Table 10. Read Data Symbol Description
SYMBOL
DESCRIPTION
MA[1:0]
Address-set bits (see Table 4)
POR
Power-on reset flag
DEFAULT
POR = 1
POR set: power on
POR reset: end-of-data transmission procedure
FL (1)
In-lock flag
A[2:0]
Digital data of ADC (see Table 11)
PLL locked (FL=1), Unlocked (FL=0)
Bit P5 must be set to 0.
(1)
Lock detector works by using phase error pulse at the phase detector. Lock flag (FL) is set or reset according to this pulse width
disciminator. Hence unstableness of PLL may cause the lock detect circuit to malfunction. In order to stable PLL, it is required to
evaluate application circuit in various condition of loop-gain (loo-p filter, CP current), and to verify with whole conditions of actual
application.
Table 11. Address Selection (1)
(1)
A2
A1
A0
VOLTAGE APPLIED ON ADC
INPUT
1
0
0
0.6 VCC to VCC
0
1
1
0.45 VCC to 0.6 VCC
0
1
0
0.3 VCC to 0.45 VCC
0
0
1
0.15 VCC to 0.3 VCC
0
0
0
0 to 0.15 VCC
Accuracy is 0.03 x VCC.
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Example I2C Data Write Sequences
Telegram examples:
Start-ADB-DB1-DB2-CB1-BB-CB2-Stop
Start-ADB-DB1-DB2-Stop
Start-ADB-CB1-BB-CB2-Stop
Start-ADB-CB1-BB-Stop
Start-ADB-CB2-Stop
Abbreviations:
ADB: Address byte
BB: Band switch byte
CB1: Control byte 1
CB2: Control byte 2
DB1: Divider byte 1
DB2: Divider byte 2
Start: Start condition
Stop: Stop condition
t HD STA
t SU STA
-
tHIGH
t
F
SCL
t SUDAT
tLOW
t SUSTO
-
tR
SDA
t HD DAT
tBUF
Figure 24. I2C Timing Chart
16
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APPLICATION INFORMATION
1
BS4
BS4
VLO OSC B
44
R5
C2
C37
UHF RF IN1
2
R36
UHF RF IN1
VLO OSC C
L1
43
C3
R2
C39
C40
VHI RF IN
R37
VLO RF IN
C42
R38
3
UHF RF IN2
VHI OSC B
42
4
VHI RF IN
VHI OSC C
41
R7
VC2 C11
5
VLO RF IN
UHF OSC B1
L2 C12
C4
R3
C5
40
L4
6
RF GND
UHF OSC C1
VC3
39
C14
L3
L6
C7
L11
7
MIX OUT2
UHF OSC C2
L10
8
MIX OUT1
9
IF IN
UHF OSC B2
R8
38
C13
C47
R42
R6
VC4
C6
C49
C9
C10
R1 C1 VC1
37
R4
C8
C15
R9
R10
L5
OSC GND
36
C16
C19
C18
10 RF AGC OUT
RF AGC OUT
CP
(See Note A)
35
R12
C51
R11
11 RF AGC BUFF
RF AGC BUFF OUT
VTU
34
VTU
C17
C52
BS3
12 BS3
IF GND
33
BS2
13 BS2
AIF OUT
32
BS1
14 BS1
DIF OUT1
31
15 SDA
DIF OUT2
30
16 SCL
IF GCA CTRL
29
C20
C21
R48
SDA
AIF OUT
R15
R21
DIF OUT1
C23 R17
R19
C62
R49
SCL
C30
17 AS
AS
VCC
C56
28
C65
C64
IF GCA CTRL
R46
C63
R50
VCC
C26
18 BUS GND
IF GCA IN1
27
19 P5/ADC
IF GCA IN2
26
IF GCA GND
25
IF GCA OUT2
24
C61
R24
C28
P5/ADC
IF GCA IN1
R25
R23
XTAL OUT
R47
20 XTAL OUT
C57
C58
21 XTAL2
C32
R28 R30
C34
R31
C59
X1
22 XTAL1
IF GCA OUT1
23
R34
IF GCA OUT1
C60
A.
To prevent abnormal oscillation, connect C16, which does not affect a PLL.
B.
This application information is advisory and performance-check is required at actual application circuits. TI assumes
no responsibility for the consequences of use of this circuit, such as an infringement of intellectual property rights or
other rights, including patents, of third parties.
Figure 25. Reference Measurement Circuit
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Table 12. Component Values for Measurement Circuit (1)
PARTS NAME
VALUE
PARTS NAME
VALUE
C1 (VLO OSC B)
1 pF
L1 (VLO OSC)
3.0 mm, 7T, wire 0.32 mm
C2 (VLO OSC C)
2 pF
L2 (VHI OSC)
2.0 mm, 3T, wire 0.4 mm
C3 (VHI OSC B)
7 pF
L3 (UHF OSC)
1.8 mm, 3T, wire 0.4 mm
C4 (VHI OSC C)
5 pF
L4 (UHF OSC)
1.8 mm, 3T, wire 0.4 mm
C5 (UHF OSCB1)
1.5 pF
L5 (MIX OUT)
680 nH (LK1608R68K-T)
C6 (UHF OSCC1)
1 pF
L6 (MIX OUT)
680 nH (LK1608R68K-T)
C7 (UHF OSCC2)
1 pF
L10 (MIX OUT)
Short
C8 (UHF OSCB2)
1.5 pF
L11 (MIX OUT)
Short
C9 (VLO OSC)
OPEN
R1(VLO OSC B)
0
C10(VLO OSC)
43 pF
R2 (VHI OSC B)
4.7 Ω
C11 (VHI OSC)
51 pF
R3 (UHF OSC B1)
4.7 Ω
C12 (VHI OSC)
0.5 pF
R4 (UHF OSC B2)
0
C13 (UHF OSC)
10 pF
R5 (VLO OSC)
3.3 kΩ
C14 (UHF OSC)
100 pF
R6 (VHI OSC)
3.3 kΩ
C15 (VTU)
2.2 nF/50 V
R7 (VHI OSC)
3.3 kΩ
C16 (CP)
150 pF/50 V
R8 (UHF OSC)
1 kΩ
C17 (VTU)
2.2 nF/50 V
R9 (UHF OSC)
2.2 k
C18(CP)
0.01 u/50 V
R10 (VTU)
3 kΩ
C19(CP)
22 pF/50 V
R11 (VTU)
20 kΩ
C20 (AIF OUT)
2.2 nF
R12 (CP)
47 kΩ
C21 (DIF OUT1)
2.2 nF
R15 (DIF OUT1)
200 Ω
C23 (DIF OUT2)
2.2 nF
R17 (DIF OUT2)
200 Ω
C26 (IF GCA IN1)
2.2 nF
R19 (DIF OUT2)
50 Ω
C28 (IF GCA IN2)
2.2 nF
R21 (DIF OUT1)
0
C30 (VCC)
0.1 uF
R23 (P5/ADC)
Open
C32 (IF GCA OUT1)
2.2 nF
R24 (IF GCA IN1)
(50 Ω)
C34 (IF GCA OUT2)
2.2 nF
R25 (IF GCA IN2)
0
C37 (UHF RF IN1)
2.2 nF
R28 (IF GCA OUT1)
200 Ω
C39 (UHF RFIN2)
2.2 nF
R30 (IF GCA OUT1)
50 Ω
C40 (VHI RF IN)
2.2 nF
R31 (IF GCA OUT2)
200 Ω
C42 (VLO RF IN)
2.2 nF
R34 (IF GCA OUT2)
0
C47 (MIX OUT)
6 pF
R36 (UHF RF IN1)
(50 Ω)
C49 (MIX OUT)
2.2 nF
R37 (VHI RF IN)
(50 Ω)
C51 (RF AGC OUT)
0.15 uF
R38 (VLO RF IN)
(50 Ω)
C52 (RF AGC BUF)
Open
R42 (MIX OUT)
0
C56 (IFGCA CTRL)
0.1 μF
R46 (IFGCA CTRL)
0
C57 (XTAL OUT)
0.01 uF
R47 (XTAL OUT)
5.1 kΩ
C58 (XTAL OUT)
10 pF
R48 (SDA)
330 Ω
C59(XTAL)
27 pF
R49 (SCL)
330 Ω
C60 (XTAL)
27 pF
R50 (AS)
Open
C61 (VCC)
2.2 nF
VC1 (VLO OSC)
MA2S374
C62 (SDA)
Open
VC2 (VHI OSC)
MA2S374
C63 (SCL)
Open
VC3 (UHF OSC)
MA2S372
C64 (AS)
Open
VC4 (VHI OSC)
MA2S372
C65 (AS)
22 pF
X1
4-MHz crystal
(1)
18
IF frequency = 44 MHz Local frequency range : VHF-LOW=101~215 MHz, VHF-HIGH: 221~511 MHz, UHF: 517~908 MHz
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APPLICATION INFORMATION (CONTINUED)
Test Circuits
DUT
SG
50 W
50 W
VIN
VLO RF IN
(VHI RF IN)
DIF OUT1
Spectrum
Analyzer
VOUT Diff 200 W
VOUT
DIF OUT2
50 W
Gv = 20log(VOUT Diff/VIN)
= 20log(VOUT/VIN) + 6 + 14
250 W
Figure 26. VHF-Conversion Gain-Measurement Circuit (at DIFOUT)
DUT
SG
50 W
50 W
VIN
VLO RF IN
(VHI RF IN)
Spectrum
Analyzer
AIFOUT
Gv = 20log(VOUT/VIN)
VOUT
50 W
Figure 27. VHF-Conversion Gain Measurement Circuit (at AIFOUT)
DUT
SG
UHF RF IN1
50 W
50 W
VIN
DIF OUT1
UHF RF IN2
VOUT Diff
200 W
VOUT
DIF OUT2
Spectrum
Analyzer
50 W
Gv = 20log(VOUT Diff/VIN)
= 20log(VOUT/VIN) + 6 + 14
250 W
Figure 28. UHF-Conversion Gain-Measurement Circuit (at DIFOUT)
DUT
SG
UHFRF IN1
50 W
50 W
VIN
Spectrum
Analyzer
AIFOUT
UHFRF IN2
Gv = 20log(VOUT/VIN)
VOUT
50 W
Figure 29. UHF-Conversion Gain Measurement Circuit (at AIFOUT)
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DUT
SG
IFGCAIN1
50 W
50 W
VIN
IFGCAIN2
IFGCAOUT1
VOUT
IFGCAOUT2
IFGCACTRAL
Spectrum
Analyzer
VOUT Diff 200 W
50 W
Gv = 20log(VOUT Diff/VIN)
= 20log(VOUT/VIN) + 6 + 14
250 W
DC Power
Source
Figure 30. IF GCA Gain Measurement Circuit
NF
Meter
Noise
Source
DUT
Figure 31. Noise-Figure Measurement Circuit
Signal
Generator
fdes: P = 70 dBmV
Signal
Generator
Mix
Pad
fdes ±6 MHz
AM 30%, 1 kHz
DUT
Modulation
Analyzer
Figure 32. 1% Cross-Modulation Distortion Measurement Circuit
20
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TYPICAL CHARACTERISTICS
Band Switch Driver Output Voltage (BS1–BS4)
BS OUTPUT CURRENT
vs
OUTPUT VOLTAGE
Band Switch Output Voltage – V
5.0
4.5
VCC = 5.5 V
4.0
VCC = 5.0 V
3.5
VCC = 4.5 V
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
14
16
18
20
Band Switch Current – mA
Figure 33. Band Switch Driver Output Voltage
70
60
50
Vcc=5.5V
Gain [dB]
40
Vcc=5.0V
Vcc=4.5V
30
20
10
0
-10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IF GCA CTRL voltage [V]
Figure 34. IF GCA Gain vs Control Voltage-1
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TYPICAL CHARACTERISTICS (continued)
70
60
Gain (dB)
85°C
–20°C
50
25°C
40
30
20
10
0
-10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IF GCA CTRL Voltage (V)
Figure 35. IF GCA Gain vs Control Voltage-2
S-Parameter
40
40MHz
MHz
500
500MHz
MHz
Figure 36. VLO RFIN, VHI RFIN
22
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TYPICAL CHARACTERISTICS (continued)
900
500MHz
MHz
350
40MHz
MHz
Figure 37. UHF RFIN
60 MHz
30 MHz
500MHz
Figure 38. DIFOUT
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TYPICAL CHARACTERISTICS (continued)
60 MHz
30 MHz
500MHz
Figure 39. AIFOUT
20 MHz
70 MHz
500MHz
40MHz
Figure 40. IF GCA IN
24
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TYPICAL CHARACTERISTICS (continued)
70 MHz
20 MHz
500MHz
40MHz
Figure 41. IF GCAOUT
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PACKAGE OPTION ADDENDUM
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10-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN761644DBTR
OBSOLETE
Package Type Package Pins Package
Drawing
Qty
TSSOP
DBT
44
Eco Plan
Lead/Ball Finish
(2)
TBD
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Call TI
Call TI
(4/5)
-20 to 85
SN761644
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 1
Samples
PACKAGE OUTLINE
DBT0044A
TSSOP - 1.2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6
TYP
6.2
A
C
0.1 C
PIN 1 INDEX
AREA
42X 0.5
44
1
2X
10.5
11.1
10.9
NOTE 3
22
23
44X
B
4.5
4.3
NOTE 4
0.27
0.17
0.08
1.2 MAX
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220223/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
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EXAMPLE BOARD LAYOUT
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
44X (1.5)
(R0.05) TYP
1
44
44X (0.3)
42X (0.5)
SYMM
23
22
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220223/A 02/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
44X (1.5)
SYMM
(R0.05) TYP
1
44
44X (0.3)
42X (0.5)
SYMM
23
22
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4220223/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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