SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B – APRIL 1982 – REVISED JANUARY 1995
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description
These octal D-type edge-triggered flip-flops
feature inverting 3-state outputs designed
specifically for bus driving. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
2D
1D
SN54ALS564B . . . FK PACKAGE
(TOP VIEW)
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
3D
4D
5D
6D
7D
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
The SN54ALS564B is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The SN74ALS564B is characterized for
operation from 0°C to 70°C.
3
1Q
•
•
•
SN54ALS564B . . . J OR W PACKAGE
SN74ALS564B . . . DW OR N PACKAGE
(TOP VIEW)
3-State Buffer-Type Inverting Outputs Drive
Bus Lines Directly
Bus-Structured Pinout
Buffered Control Inputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
OE
VCC
•
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
L
L
↑
L
H
L
L
X
Q0
H
X
X
Z
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B – APRIL 1982 – REVISED JANUARY 1995
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
logic diagram (positive logic)
EN
OE
C1
19
1D
3
18
4
17
5
16
6
15
7
14
8
13
9
12
CLK
1
11
1Q
C1
2Q
3Q
1D
2
19
1Q
1D
4Q
5Q
6Q
7Q
To Seven Other Channels
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS564B . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS564B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS564B
SN74ALS564B
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
High-level output current
–1
– 2.6
mA
IOL
fclock
Low-level output current
12
24
mA
30
MHz
tw
tsu
Pulse duration, CLK high or low
25
14
ns
Setup time, data before CLK↑
15
15
ns
th
TA
Hold time, data after CLK↑
2
High-level input voltage
2
Clock frequency
0
2
22
4
Operating free-air temperature
– 55
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0
V
0
125
0
V
V
ns
70
°C
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B – APRIL 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
5V
VCC = 4
4.5
IOH = – 1 mA
IOH = – 2.6 mA
VOL
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
ICC
SN54ALS564B
TYP†
MAX
TEST CONDITIONS
VCC = 5.5 V
MIN
SN74ALS564B
TYP†
MAX
MIN
– 1.2
VCC – 2
2.4
– 1.2
UNIT
V
VCC – 2
V
3.3
2.4
0.25
– 20
3.2
0.4
0.25
0.4
0.35
0.5
V
µA
20
20
– 20
– 20
µA
0.1
0.1
mA
20
20
µA
– 0.2
– 0.2
mA
– 112
mA
– 112
– 30
Outputs high
10
18
10
18
Outputs low
15
24
15
24
mA
Outputs disabled
16
30
16
30
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
SN54ALS564B
MIN
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
MAX
SN74ALS564B
MIN
22
CLK
An Q
Any
OE
An Q
Any
• DALLAS, TEXAS 75265
MAX
30
MHz
4
24
3
14
4
20
4
14
4
24
3
18
3
23
4
18
1
10
2
15
2
14
OE
Any Q
tPLZ
3
29
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303
UNIT
ns
ns
ns
3
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
Data
Input
tw
th
tsu
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
1.3 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
[0 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8872801RA
ACTIVE
CDIP
J
20
20
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8872801RA
SNJ54ALS564BJ
Samples
SN74ALS564BDW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS564B
Samples
SN74ALS564BN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS564BN
Samples
SN74ALS564BNSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS564B
Samples
SNJ54ALS564BJ
ACTIVE
CDIP
J
20
20
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8872801RA
SNJ54ALS564BJ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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