User's Guide
SNAU112A – December 2010 – Revised May 2018
SPIO-4 Precision Signal-Path Controller Board
This user’s guide describes the characteristics, operation, and use of the SPIO-4 precision signal-path
controller board. This document includes a schematic, reference printed circuit board (PCB) layouts, and a
complete bill of materials (BOM).
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1
2
3
Contents
System Overview ............................................................................................................ 3
System Functionality ........................................................................................................ 5
PCB Layout, Schematics, and Bill of Materials......................................................................... 11
List of Figures
1
SPIO-4 System Block Diagram ............................................................................................ 5
2
GPSI 16 DUT to SPIO4 Mating ............................................................................................ 7
3
GPSI 32 DUT to SPIO4 Mating ............................................................................................ 7
4
SPIO-4 Board Layout – Component Side ............................................................................... 11
5
Board Photo Showing Respective Layout From
6
7
8
9
10
11
12
13
14
15
16
......................................................................
SPIO-4 Interface Board Block Diagram .................................................................................
Atmel ARM Microcontroller: Power, Debug, and Analog .............................................................
Atmel ARM Microcontroller and Port Connection ......................................................................
SPIO4 PSRAM .............................................................................................................
SPIO-4 FPGA SRAM and Configuration Interface .....................................................................
SPIO-4 FPGA DEBUG, JTAG Interfaces and Power .................................................................
SPIO4 FPGA GPSI32 Interface ..........................................................................................
SPIO-4 Micro SD Card ....................................................................................................
USB, CPU JTAG ...........................................................................................................
SPIO-4 Power Distribution ................................................................................................
3.3-V, 1.2-V, 1.8-V, and DUT Power Supplies .........................................................................
11
12
13
14
15
16
17
18
19
20
21
22
List of Tables
1
Main Component Reference Designators ................................................................................ 4
2
Test Points .................................................................................................................... 4
3
LED Behavior
4
GPSI-32 Signals ............................................................................................................. 8
5
Bill of Materials
................................................................................................................
.............................................................................................................
6
23
Trademarks
All trademarks are the property of their respective owners.
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System Overview
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1
System Overview
The SPIO-4 is one of several National Semiconductor digital controller and capture boards that are used
by multiple evaluation systems. The objective of these software and hardware evaluation systems is to
allow our customers to easily and accurately evaluate TI's signal-path devices in a lab setting. At the time
of the SPIO-4 release, two different evaluation system software applications and graphical user interfaces
(GUIs) make use of this board: the WaveVision-5 and the Sensor AFE. The board ships with the current
version of the WaveVision-5 software.
In addition to the controller and capture board (in this case, the SPIO-4) and the evaluation GUI software
(for example, WaveVision-5 or Sensor AFE), the third essential element of an evaluation system is the
device or signalpath evaluation board that plugs into the controller board. This evaluation board is
generically referred to as the DUT board. Each DUT board comes with a user's guide that documents the
specific features of the board. Each DUT board also comes with some software that the user must install
before initial use. In the case of the WaveVision-5 GUI, this software is essentially a device-specific
module that adds support for the future device evaluation boards. In the case of Sensor AFE device
family, the evaluation board comes with a complete, custom Sensor AFE that is specifically paired with
that device.
The WaveVision-5 and Sensor AFE GUI software have respective user's guide documents that describe
how to interact with the respective GUI.
This user’s guide describes only the SPIO-4 board. The user is expected to refer to this guide only if
necessary. The DUT user’s guide and the GUI user's guide are the primary documents that describe how
to work with a TI signal-path evaluation board.
The latest version of this document may be obtained from the Texas Instruments web site at www.ti.com.
1.1
System Features
•
•
•
•
•
•
1.2
Captures or sources multiple signal-path data streams and transfers them to and from the PC-based
application software through a USB 2.0 connection (USB 1.1 compatible).
Supports a jumper-less, plug-and-play configuration. The GUI automatically discovers the attached
DUT board and loads the appropriate software module for it.
Supports a wide variety of signal-path evaluation board through a standardized connector (GPSI- 16 or
GPSI-32).
Capable of storing up to 8 MBytes of signal-path data.
DUT interface can be SPI, I2C, or parallel.
Powered either by PC via USB or external supply.
Packing List
The SPIO-4 kit (order number SPIO-4/NOPB) consists of the following components:
• SPIO-4 board
• USB cable
• User’s guide (this document)
• WaveVision-5 GUI software
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System Overview
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Component Description
Table 1 describes both the onboard connectors and the main components used in the SPIO-4 system
shown in Figure 4.
Table 1. Main Component Reference Designators
Component
1.4
Description
J1
Serial debug connector
J2
Header to provide access to the FPGA JTAG interface for debug
J3
Jumper to select J4 IO voltage (3.3 V or programmable)
J4 (DBG)
Debug and development connector(see Section 2.6)
J6 (GPSI-32)
GPSI-16/32 connector to DUT
J7 (micro_SD)
Holds the microSD card for storage or development purposes
J8 (USB)
USB cable connection
J9 (JTAG)
Atmel processor JTAG debug header
J10 (POWER)
5-v to 6-V power supply connection; optional (see Section 2.9)
J14 (USNAP)
Additional header providing power and serial interface to processor
JP1
Jumpers for test purposes only
U1
Atmel SAM3U processor
U4
8Mx16 PSRAM
U5
Xilinx Spartan LX16 FPGA
D1-D4
FPGA status LEDs (see Section 2.4)
D6
1.8-V PSRAM core voltage surface-mount power LED
D7
3.3-V DUT supply voltage surface-mount power LED
D8
5.0-V DUT supply voltage surface-mount power LED
D10
USB input power LED
D11
1.2-V FPGA Core voltage surface-mount power LED
SW1
Reset switch
SW2
Power on push-button
SPIO-4 Board Test Points
Table 2 describes the available test points.
Table 2. Test Points
Test Point
4
Description
TP1, TP3, TP16, TP18 (GND)
Ground test points
TP11
3.3-V digital I/O voltage for SPIO board
TP12
1.2 V for FPGA core voltage
TP13
1.8 V for PSRAM core voltage
TP14
3.3 V for DUT digital supply
TP15
5.0 V for DUT analog supply
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System Functionality
2.1
System Block Diagram
Debug
Connector
(J1)
Debug
Connector
(J9)
12 MHZ
Xtal
32 kHZ
Xtal
GPSI 32
Connector
(J6)
SD
Card
(J7)
GPSI A
GPIO
USB
Connector
(J8)
Micro-Controller
Atmel SAM3U
(U1)
USB
GPSI A
>
Level Shift
Pins 1, 3, 7, 8, 16
GPSI A
GPSI A
<
Level Shift
DUT3.3V_EN
VDDIO
Pins 5, 6, 9
Pin 15
3.3 V DUT
I2C
Static Mem intrfc
I2C(SCL)
NCS2
NCS3/
FPGA_CFG
Pin 12
3.3 V DUT
A23-1
D15-0
I2C(SCL)
NCS0
8MBx16
PSRAM
(U4)
Pin 11
Spartan 6
XC6SLX16
(U5)
NWR
NRD
DUT 3.3 V
DUT 5 V
GPSI B
NBS0-1
IO Voltage
Pin 13
Pin 14
Pin 23-30
3.3 V
1.8 V
1.2 V
USB 5 V
Ext Pwr
(J10)
Input
Protection
LP3910
Multiple
Supply
Switching
Regulator
(U11)
JTAG
(J2)
DEBUG
(J4)
3.3 V
DUT3.3V_EN
DUT 3.3 V
Boost
Regulator
(U12)
Filter
DUT 5 V
Figure 1. SPIO-4 System Block Diagram
2.2
General System Overview
The SPIO-4 board is controlled via the Atmel SAM3U, a microcontroller that is based on an ARM M3, 32bit embedded core. This miscrocontroller provides the interface to the computer via a USB interface. The
DUT board interfaces to the SPIO-4 via J6, the GPSI-16/32 connector. The GPSI-16/32 interface provides
control, data and power to the DUT board. The interfaces on the GPSI-32 can be I2C, SPI with multipledevice capability, or parallel interface. The dedicated I2C interface on the GPSI-16/32 is primarily for
control and DUT identification, while the dedicated SPI interface may be used for control or for data
transfer. The I2C interface is derived from the peripheral of the microcontroller. There can be a wide
variety of SPI requirements for DUTs; therefore, the SPI interface can be provided via a processor
peripheral and over the dedicated SPI lines as shown in this document, or the onboard Xilinx Spartan
XC6SLX16 FPGA may be used. In fact, the FPGA may be used to implement DUT interfaces other than
SPI, such as high-speed I2C for data purposes, and parallel data-plus-clock interfaces. A large external
SRAM 8Mx16 is connected to both the processor and the FPGA, and is used to provide additional device
data storage in case the microcontroller or FPGA onboard memory is insufficient.
Power is provided to the system via the USB cable or external power jack. A switching regulator is used to
produce the 3.3-V supply required by the microcontroller and GPSI-32 devices. A boost regulator creates
the regulated 5-V supply required by the devices interfaced to the GPSI-32 connector.
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Automatic Device Detection and Configuration
The SPIO-4 system supports automatic hardware detection and configuration of the device under test.
The GUI software actually carries out the device detection and configuration task. The FPGA is
reconfigured on-the-fly by the host PC when the SPIO-4 board is powered on, or whenever ADC
evaluation boards are exchanged and SPIO-4 power is cycled.
Each DUT board has either an FPGA configuration file or a microcontroller firmware module unique to the
board. The GUI software, in conjunction with the USB microcontroller, determines which DUT board has
been plugged in. The GUI then loads a configuration file tailored for that DUT board into the FPGA, the
microcontroller, or both.
Normally, the configuration process is totally transparent to the user, and requires no intervention.
However, some devices may allow this process to be overridden. Refer to the evaluation board manual for
more information.
NOTE: Many of our device evaluation boards do require jumper configurations to select channels,
voltages, or other options. Please consult the manual that came with the evaluation board for
specific information.
CAUTION
Be aware that DUT boards are NOT hot swappable. Power down both the
SPIO-4 board and the DUT board prior to swapping DUT board.
2.4
LED Indicators
There are several LED indicators on the SPIO-4 board. The LED indicators described in Table 3 are
driven directly by separate power rails on the SPIO-4 board. Those rails can only be controlled by the
processor; therefore, the LEDs not only indicate a particular rails is powered on, but the LEDs also show
the state of the SPIO-4 firmware, as shown in Table 3.
Table 3. LED Behavior
LED Number
2.5
Description
D10
Indicates power (USB or external) is present to SPIO board
D5
3.3-V digital I/O voltage for SPIO board is up (required for all operations)
D6
1.2 V for FPGA core voltage. Indicates processor has completed low-level hardware initialization, and is
ready to program the FPGA.
D11
1.8 V for PSRAM core voltage. Indicates processor has completed low-level hardware initialization, and
is able to use the PSRAM
D7 and D8
3.3-V and 5-V DUT supplies. Indicates the processor has detected a DUT board is inserted, and has
powered the board.
DUT Interface (GPSI-16/32)
The SPIO-4 data capture board is connected to the DUT through the GPSI-16/32 (J6) connector. As
described in this user's guide, the GPSI-32 interface provides control, data, and power to the DUT board.
See Table 4 for signal specifics. The GPSI-16/32 interface also supports a subset called GPSI-16 that
consists of the lower order pins 1 to 16. A given DUT board may use a 16-pin, GPSI-16 port only, or may
use the whole 32-pin port. GPSI-16 has level shifters allowing some of the DUT interface voltages to go
from 1.65-V to 5.5-V LVTTL levels under the direct control of the DUT board circuitry. To achieve that
voltage range, the voltage level shifters are NOT bidirectional. A DUT board requiring bidirectional signals
must use the upper-order portion of the GPSI-32. However, that upper-order portion of GPSI-32 requires
adherence to 3.3-V LVTTL voltage levels because the upper-order portion does not have level shifters.
Figure 2 and Figure 3 show two photos demonstrating the proper mating of a GPSI16 and a GPSI32 DUT
board to the SPIO4.
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Figure 2. GPSI 16 DUT to SPIO4 Mating
Figure 3. GPSI 32 DUT to SPIO4 Mating
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Level Shifters
The board incorporates level shifters to allow flexible output voltages on the unidirectional SPI signals of
GPSI-16 port, as shown in Figure 1. VDDIO, a supply voltage from the GPSI-16/32 connector coming from
the DUT board, provides the voltage to the output side of the level translators. If the DUT has no special
requirements for voltage and simply needs basic 3.3-V signal levels, the 3.3-V output from the GPSI
connector can be connected to VDDIO on the DUT board. The level shifters are unidirectional. If VDDIO is
not provided, the level shifters enter a shutdown state with all input pins in a tri-state condition. The state
passed along to the processor in this case is logic low. Table 4 shows the full list of available level-shifter
configurations.
Table 4. GPSI-32 Signals
Pin #
Signal Name
Signal Function
Voltage Level
Direction
(From SPIO-4)
1.65 V to 5.5 V
Output
N/A
N/A
1.65 V to 5.5 V
Output
N/A
Input
Pins 1-16 form the GPSI-16 subset:
1
SCS0_A~
Serial Bus A – Chip select for device 0.
2
GND
Ground
3
SCK_A
Serial Bus A – Serial clock from the master to the device.
DUT_Present~
The DUT board grounds this pin. The SPIO-4 senses this pin to
determine the DUT board presence.
SMISO_A
Serial Bus A – Data from the slave (device) to the master. The
device may implement this as a tri-state signal that can be driven
1.65 V to 5.5 V
by multiple devices on Serial Bus A in a bussed fashion. The pullup
resistor, if required, is on the DUT board.
Input
6
Dev_INT~/
SDRDY_A~
In certain applications, if required, this pin serves as the DRDY~
signal from the DUT to the SPIO-4. In other cases, this pin may be
a general interrupt pin from the device to the SPIO-4. On the SPIO- 1.65 V to 5.5 V
4 board, this signal connects to an interrupt pin on the
microcontroller.
Input
7
SMOSI_A
Serial Bus A – Data from the master to the slave (device).
1.65 V to 5.5 V
Output
8
SCS1_A~
Serial Bus A – Chip select for device 1.
1.65 V to 5.5 V
Output
9
Ref_CLK
Reference clock from the DUT board to the SPIO-4 board. If not
used, the DUT board should ground this pin.
1.65 V to 5.5 V
Input
10
GND
Ground
N/A
N/A
11
SDA
Data line of the I2C bus. Pulled up to +3.3V_DUT on the SPIO-4
board through a 1.5-kΩ resistor.
3.3 V
Bidirectional
12
SCL
Clock line of the I2C bus. Pulled up to +3.3V_DUT on the SPIO-4
board through a 1.5-kΩ resistor.
3.3 V
Bidirectional
+3.3V_DUT
Switched by the SPIO-4 conditional parameter on the
DUT_Present pin. The ID EEPROM and the entire I2C bus on the
DUT board must be unconditionally powered by this supply.
Maximum peak current = 50 mA (subject to total power budget limit
of 200 mW over both supplies). Maximum capacitor loading for this
node is not to exceed 50 µF.
3.3 V
Output
14
+5V_DUT
This supply is sourced by the SPIO-4 and is intended to power the
core functionality of the DUT board, if desired. Nominal current =
35 mA. Maximum peak current = 50 mA (subject to total power
budget limit of 200mW over both supplies). If power from the SPIO4 is not required, the DUT board must leave this pin open.
Maximum capacitor loading for this node is not to exceed 50 µF.
5.0 V
Output
15
VDDIO
1.65 V to 5.5 V
Input
16
SCS2_A~
1.65 V to 5.5 V
Output
17
DUT_PWR_Enable
4
5
13
8
3.3 V
Output
18
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open. (Possible use: DUT_RESET~)
3.3 V
N/A
19
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
3.3 V
N/A
20
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
3.3 V
N/A
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Table 4. GPSI-32 Signals (continued)
Pin #
Signal Name
Signal Function
Voltage Level
Direction
(From SPIO-4)
21
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
3.3 V
N/A
22
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
3.3 V
N/A
SCS0_B~
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Chip select for device 0.
3.3 V
N/A
24
SDRDY_B~
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
In certain SPI applications, if required, this pin serves as the
DRDY~ signal from the DUT to the SPIO-4.
3.3 V
N/A
25
SCK_B
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Serial clock from the master to the device.
3.3 V
N/A
26
SCS1_B~
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Chip select for device 1.
3.3 V
N/A
27
SMISO_B
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Data from the slave (device) to the master. The
device may implement this as a tri-state signal that can be driven
by multiple devices on Serial Bus B in a bussed fashion. The pullup
resistor, if required, is on the DUT board.
3.3 V
N/A
28
SCS2_B~
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Chip select for device 2.
3.3 V
N/A
29
SMOSI_B
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Data from the master to the slave (device).
3.3 V
N/A
30
SCS3_B~
Available for implementation-specific use. Refer to the DUT board
manual. If unused, leave it open.
If a second SPI bus is implemented, then use this pin as shown:
Serial Bus B – Chip Select for device 3.
3.3 V
N/A
31
Reserved
Reserved for future use. The DUT board leaves this pin open.
3.3 V
N/A
32
GND
Ground
N/A
N/A
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2.6
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Auxiliary Interface
The SPIO-4 board can be connected to auxiliary test equipment through debug connector J4 located on
the board.
2.7
Computer Interface
The SPIO-4 board communicates with a PC via standard USB 2.0 at high-speed (up to a 480 Mbits/sec
signaling rate). The board is fully backward-compatible with USB 1.1 devices and cables.
2.8
Memory
The SPIO-4 board comes with 8M × 16 bits of PSRAM for data storage. The memory is a single Micron
MT45W8MW16BGX PSRAM configured for asynchronous accesses. In asynchronous configuration, the
fastest access speed is 70 ns latency, or approximately 14.2 MHz per 16-bit transfer. Both the processor
and the FPGA have read and write access to the PSRAM. The processor’s static memory interface
mastership is controlled by firmware within the processor because there is no hardware mechanism to
share the bus.
2.9
Power Requirements
The SPIO-4 data capture board can be solely powered using the USB interface power, but can also be
powered by an external power supply. The SPIO-4 data capture board consumes up to 500 mA of current
depending on the DUT load. ADC evaluation boards differ widely in their power consumption; consult the
manual that came with your evaluation board, and verify if an external supply is required for your DUT
board. External power can be supplied via J10, and must be greater than 4.5 V and less than 6.0 V dc
with a current rating of at least 1 A.
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PCB Layout, Schematics, and Bill of Materials
The following section shows the printed circuit board (PCB) layout overview, the schematics, and the bill
of materials (BOM).
3.1
PCB Layout Overview
Figure 4 shows the component side of the SPIO-4 board layout.
5"
SW2
J14
DUT
5V
U12
5V
J2
D8
Ext
Pwr
J10
DUT SPIO PSRAM FPGA
3.3 V 3.3 V 1.8 V 1.2 V
D7
D4 D3
D5
D6
U11
LP3910
1.2 V, 1.8 V,
3.3 V
D11
U4
PSRAM
D2 D1
D10
J8
USB
SW1
J6 GPSI-16/32
U9
U6
U1
SAM3U
100 LQFP
16x16
U5
XC6SLX16 FPGA
324 FBGA
18x18
J9
JTAG Debug
Connector
U10
3"
U8
U7
J3
J4
JP1
J1
J7
SD
Card
Figure 4. SPIO-4 Board Layout – Component Side
Figure 5. Board Photo Showing Respective Layout From Figure 4
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Schematics
The following pages show the schematics of the board. These are provided for general information
purposes only. TI reserves the right to make modifications to the board design at any time.
Debug
Connector
(J1)
Debug
Connector
(J9)
12 MHZ
Xtal
32 kHZ
Xtal
GPSI 32
Connector
(J6)
SD
Card
(J7)
GPSI A
GPIO
USB
Connector
(J8)
Micro-Controller
Atmel SAM3U
(U1)
USB
GPSI A
>
Level Shift
Pins 1, 3, 7, 8, 16
GPSI A
GPSI A
<
Level Shift
DUT3.3V_EN
VDDIO
Pins 5, 6, 9
Pin 15
3.3 V DUT
I2C
Static Mem intrfc
I2C(SCL)
NCS2
NCS3/
FPGA_CFG
Pin 12
3.3 V DUT
A23-1
D15-0
I2C(SCL)
NCS0
8MBx16
PSRAM
(U4)
Pin 11
Spartan 6
XC6SLX16
(U5)
NWR
NRD
DUT 3.3 V
DUT 5 V
GPSI B
NBS0-1
IO Voltage
Pin 13
Pin 14
Pin 23-30
3.3 V
1.8 V
1.2 V
USB 5 V
Ext Pwr
(J10)
Input
Protection
LP3910
Multiple
Supply
Switching
Regulator
(U11)
JTAG
(J2)
DEBUG
(J4)
3.3 V
DUT3.3V_EN
DUT 3.3 V
Boost
Regulator
(U12)
Filter
DUT 5 V
Figure 6. SPIO-4 Interface Board Block Diagram
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Atmel ARM Microcontroller - Power, Debug, Analog
3p3V
JP1
JP
U1B
SAM3U
VANA
C1
137
138
142
135
136
10nF
9
R1
RSTN
DNS
ERASE
TEST
JTAGSEL
FWUP
SHDN
SW1
A
B
39
VBG
DGND
DGND
11
9
9
9
9
9
9
NRST_PWR
DHSD_P
DHSD_M
R2
R3
39R
39R
DFSD_M
DFSD_P
DHSDP
DHSDM
DFSDM
DFSDP
144
143
XIN32_CLK
XOUT32
C5
10uF
DGND
VCORE
DGND
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
17
51
85
104
127
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
XIN
XOUT
C4
0.1uF
C3
10uF
34
VDDPLL
XIN32
XOUT32
36
35
XIN_CLK
XOUT1
C2
0.1uF
16
27
44
50
86
125
VDDCORE1
VDDCORE2
VDDCORE3
VDDCORE4
VDDCORE5
VDDCORE6
TDI
TDO/TRACESWO
TMS/SWDIO
TCK/SWCLK
37
38
41
42
2
VDDOUT
NRST
NRSTB
1
4
7
9
TDI
TDO
TMS
TCK
3p3V
3
VDDIN
VBG
11
141
74
76
ADVREF
AD12BVREF
C11
0.1uF
C12
0.1uF
C13
10uF
DGND
3p3V
VUTMI
18
52
60
90
126
VBG
XIN32_CLK
C25
GND1
GND2
GND3
GND4
GND5
15pF
140
R4
6.8K
Y2
32.768KHz
C30
15pF
C16
0.1uF
DGND
139
VDDBU
3p3V
DGND
0R R66
DGND
3p3V
XIN_CLK
C24
C19
10uF
C23
0.1uF
GNDANA
C27
0.1uF
3p3V
L1
10uH/100mA
C18
0.1uF
VANA
GNDUTMI
VDDBU
VUTMI
C17
0.1uF
GNDPLL
75
XOUT32
C15
0.1uF
DGND
DGND
73
VDDANA
43
DGND
C14
0.1uF
C20
0.1uF
GNDBU
33
C21
10pF
40
VDDUTMI
DGND
C59
1.0uF
15pF
DGND
C26
0.1uF
R5
0R
Y1
12.000MHz
C22
10uF
XOUT1
C28
C29
DGND
15pF
3p3V
4.7uF
DGND
DGND
VANA
R69
DNS
499R
3p3V
L2
10uH/100mA
CLK_12MHZ2_R
3p3V
U2
1
R67
CLK_12MHZ 5
2
DNS
3p3V
C31
0.1uF
R6
0R
C32
2
4.7uF
DGND
DGND
1
3
U3
1
OE
VDD
GND
OUT
4
3
DNS
OSCIL_12M_SMD_3.3V
VCORE
U13
R8
CLK_12MHZA_R
2
CLK_12MHZA
1A
2A
GND
VCC
1Y
2Y
DNS
74LVC2G06
DNS
5
6
4
1.0K
DGND
R70
OE
VDD
GND
OUT
4
3
DNS
OSC_32768HZ_SMD
R7
CLK_32K_R
XIN32_CLK
DNS
DNS
CLK_12MHZ1_R
DNS
XIN_CLK
R68
DGND
R71
DNS
DGND
Figure 7. Atmel ARM Microcontroller: Power, Debug, and Analog
SNAU112A – December 2010 – Revised May 2018
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SPIO-4 Precision Signal-Path Controller Board
Copyright © 2010–2018, Texas Instruments Incorporated
13
PCB Layout, Schematics, and Bill of Materials
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Atmel ARM Microcontroller, Port Connection
D[15:0] 4,5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D9
D11
D12
D13
D14
D15
U1A
SAM3U
9,11 VUSB_DET
8
CD
7
DUTCLKIN
8
CK
8
CDA
8
DA0
8
DA1
8
DA2
8
DA3
11
SDA
11
SCL
TP17
DUT_SDA
1
7
7
7
7
DUT_SCL
11
11
CPUMISO_A
CPU_MOSI_A
CPU_SCLK_A
CPU_CS0N_A
ONSTAT
USBISEL
RXD_IN
TXD_OUT
USNAP_SCLK_N
USNAP_MOSI
USNAP_MISO
USNAP_SEL_N
USNAP_IRQ_N
TP4
7
DUT_SDA
7
DUT_SCL
5
SCC_TD
5
PCK
5
SCC_CLK
7 DUTDRDYN_A
5
SCC_TF
4 SRAM_CNTRL_REG
1
TP7
CK
CDA
DA0
DA1
DA2
DA3
1
TP19
CD
1
SDA
SCL
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
7 CPU_CS2N_A
4,5
NBS1
NBS1
109
111
113
115
117
119
121
123
128
130
132
133
134
87
88
91
93
95
99
100
101
102
77
103
105
106
107
64
45
46
78
48
110
112
114
116
118
120
122
124
129
131
89
92
94
98
28
81
PA0/WKUP0
PA1/WKUP1
PA2/WKUP2
PA3/CK
PA4/CDA
PA5/DA0
PA6/DA1
PA7/DA2
PA8/DA3
PA9/TWD0
PA10/TWCK0
PA11/URXD
PA12/UTXD
PA13/MISO
PA14/MOSI
PA15/SPCK
PA16/NPCS0
PA17/WKUP7
PA18/WKUP8
PA19/WKUP9
PA20/TXD1
PA21/RXD1
PA22/RTS1
PA23/CTS2
PA24/WKUP11
PA25/WKUP12
PA26/TD
PA27/PCK0
PA28/TK
PA29/PWMH1
PA30/TF
PA31/RF
PB0/PWMH0
PB1/PWMH1
PB2/PWMH2
PB3/AD12BAD2
PB4/AD12BAD3
PB5/AD1
PB6/D15
PB7/A0/NBS0
PB8/A1
PB9/D0
PB10/D1
PB11/D2
PB12/D3
PB13/D4
PB14/D5
PB15/D6
PB16/D7
PB17/NANDOE
PB18/NANDWE
PB19/NRD
PB20/NCS0
PB21/A21/NANDALE
PB22/A22/NANDCLE
PB23/NWR0/NWE
PB24/NANDRDY
PB25/D8
PB26/D9
PB27/D10
PB28/D11
PB29/D12
PB30/D13
PB31/D14
PC0/A2
PC1/A3
PC2/A4
PC3/A5
PC4/A6
PC5/A7
PC6/A8
PC7/A9
PC8/A10
PC9/A11
PC10/A12
PC11/A13
PC12/NCS1
PC13/RXD3
PC14/NPCS2
PC15/NWR1/NBS1
PC16/NCS2
PC17/AD12BAD6
PC18/AD12BAD7
PC19/NPCS1
PC20/A14
PC21/A15
PC22/A16
PC23/A17
PC24/A18
PC25/A19
PC26/PWMH2
PC27/A23
PC28/DA4
PC29/DA5
PC30/DA6
PC31/DA7
53
55
57
79
80
65
66
67
68
31
30
59
61
62
29
97
96
26
25
24
23
21
20
19
15
14
13
12
10
8
6
5
82
83
84
32
108
22
47
49
54
56
58
63
69
70
71
72
D15
NBS0
A1
D0
D1
D2
D3
D4
D5
D6
D7
NRD
NCS0
A21
A22
NWE
D8
D9
D10
D11
D12
D13
D14
A14
A15
A16
A17
A18
A19
A20
A23
USNAP_RST_N
FPGA_INIT_N 5
FPGA_M0 5
FPGA_M1 5
FPGA_PRGM_N 6
FPGA_DONE_N 6
DUT_PWR_EN 7
NBS0
4,5
A[23:1]
IRQ_PWR_N 11
DUT_PRSNT_N 7
NRD
4,5
NCS0
4,5
NWE
PCK1
4,5
5
NCS2
5
NCS3
5
NWAIT
4,5
CPU_CS1N_A 7
DUT_3VEN
DUT_5VEN
4,5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
11
11
USNAP INTERFACE
J14
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
PCB REVISION RESISTORS
USNAP_SEL_N
USNAP_IRQ_N
USNAP_SCLK_N
USNAP_MOSI
USNAP_MISO
USNAP_RST_N
USNAP_RST_N
UART Debug Interface header
R82 1.5K
J1
USNAP_IRQ_N
3p3V
R83 DNS
DGND
R82
REV
___ R83
___ PCB
______
DNS DNS A
2mm_hdr_6pin
1
2
3
4
5
1
2
3
4
5
RXD_IN
TXD_OUT
3p3V
hdr_5pin
1.5K DNS B
DNS 1.5K C
DGND
DGND
Figure 8. Atmel ARM Microcontroller and Port Connection
14
SPIO-4 Precision Signal-Path Controller Board
SNAU112A – December 2010 – Revised May 2018
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PCB Layout, Schematics, and Bill of Materials
www.ti.com
3,5
3,5
A[23:1]
U4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
3,5
3,5
3,5
3,5
NCS0
NRD
NWE
3,5
3,5
NBS1
NBS0
A3
A4
A5
B3
B4
C3
C4
D4
H2
H3
H4
H5
G3
G4
F3
F4
E4
D3
H1
G2
H6
E3
J4
B5
A2
G5
B2
A1
A6
J3
J2
SRAM_CNTRL_REG
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
CS
OE
WE
UB
LB
CRE
ADV
CLK
D[15:0]
MT45W8MW16BGX
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WAIT
RFU3
RFU4
B6
C5
C6
D5
E5
F5
F6
G6
B1
C1
C2
D2
E2
F2
F1
G1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
J1
NWAIT
3,5
J5
J6
3p3V
1p8V
VCCQ
VCC
VSSQ
VSSQ
3p3V
E1
D6
C33
0.1uF
C34
1.0uF
D1
E6
MT45W8MW16BGX
DGND
C35
0.1uF
C36
0.1uF
C37
10uF
DGND
DGND
Figure 9. SPIO4 PSRAM
SNAU112A – December 2010 – Revised May 2018
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SPIO-4 Precision Signal-Path Controller Board
Copyright © 2010–2018, Texas Instruments Incorporated
15
PCB Layout, Schematics, and Bill of Materials
3,4
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D9
D11
D12
D13
D14
D15
3,4
www.ti.com
U5-2
NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS
U5-3
D2
3 FPGA_INIT_N
3,4
NCS0
3,4
NWE
3,4
3,4
3,4
3,4
NRD
NBS0
NBS1
NWAIT
NCS0
D4
D15
D14
D13
D12
D11
D10
D9
D8
A[23:1]
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
NRD
NBS0
NBS1
NWAIT
FPGA_CFG_CSN
D5
D6
3
FPGA_M0
3
NCS2
D3
D1
FPGA_CCLK
CCLK R15
DATA_D7_CFG_D0
3
FPGA_M1
2
CLK_12MHZ
3
PCK1
D0
R3
U3
T4
U5
T5
V7
U7
T7
V8
U8
T8
V10
U10
T10
U11
T11
V13
U13
T13
V14
T14
T15
V16
U16
V6
V3
V4
V5
V9
T6
V11
T3
R15
R13
N12
P12
R11
R10
R8
T9
R7
R5
N5
P6
3p3V
IO_L62P_D5_2
VCCO_2
IO_L65P_INIT_B_2
VCCO_2
IO_L63P_2
VCCO_2
IO_L49P_D3_2
VCCO_2
IO_L48N_RDWR_B_VREF_2 VCCO_2
IO_L43N_2
VCCO_2
IO_L43P_2
IO_L46N_2
IO_L41N_VREF_2
IO_L41P_2
IO_L31N_GCLK30_D15_2
IO_L30N_GCLK0_USERCCLK_2
IO_L30P_GCLK1_D13_2
IO_L29N_GCLK2_2
IO_L23P_2
IO_L16N_VREF_2
IO_L14N_D12_2
IO_L14P_D11_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L12N_D2_MISO3_2
IO_L12P_D1_MISO2_2
IO_L1N_M0_CMPMISO_2
IO_L2N_CMPMOSI_2
IO_L2P_CMPCLK_2
IO_L45N_2
IO_L65N_CSO_B_2
IO_L63N_2
IO_L49N_D4_2
IO_L32N_GCLK28_2
IO_L45P_2
IO_L23N_2
IO_L62N_D6_2
IO_L1P_CCLK_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L13P_M1_2
IO_L13N_D10_2
IO_L16P_2
IO_L29P_GCLK3_2
IO_L31P_GCLK31_D14_2
IO_L32P_GCLK29_2
IO_L46P_2
IO_L48P_D7_2
IO_L64P_D8_2
IO_L64N_D9_2
P9
R12
R6
U14
U4
U9
XC6SLX9CSG324
REQUIRED SIGNALS TO CONFIG FPGA
VIA SERIAL OR BYTE WIDE (SELECTMAP)
D7 R5
D6 T3
CSI_B T13
D5 R3
RDWR_B T5
INIT U3
D4 V5
M1 N12
D3 U5
M0 T15
D2 V14
D1 T14
DO_DIN R13
D7
0R R74
3
SCC_TD
3
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
J18
K18
K17
K16
J16
L15
K15
H14
C17
C18
D17
D18
E16
E18
F18
F17
F16
F15
G18
G16
H18
H17
H16
H15
P18
P17
T17
U17
N18
N17
N16
P15
P16
M18
M16
N15
N14
L18
L17
L16
T18
U18
F14
G14
H12
G13
K12
K13
H13
J13
K14
L12
L13
M14
L14
M13
3p3V
IO_L44N_A2_M1DQ7_1
VCCO_1
IO_L45N_A0_M1LDQSN_1
VCCO_1
IO_L45P_A1_M1LDQS_1
VCCO_1
IO_L41N_GCLK8_M1CASN_1 VCCO_1
IO_L44P_A3_M1DQ6_1
VCCO_1
IO_L42P_GCLK7_M1UDM_1
VCCO_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L36N_A8_M1BA1_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L35N_A10_M1A2_1
IO_L35P_A11_M1A7_1
IO_L1N_A24_VREF_1
IO_L1P_A25_1
IO_L38N_A4_M1CLKN_1
IO_L38P_A5_M1CLK_1
IO_L43N_GCLK4_M1DQ5_1
IO_L43P_GCLK5_M1DQ4_1
IO_L37N_A6_M1A1_1
IO_L37P_A7_M1A0_1
IO_L49N_M1DQ11_1
IO_L49P_M1DQ10_1
IO_L51P_M1DQ12_1
IO_L52P_M1DQ14_1
IO_L48N_M1DQ9_1
IO_L48P_HDC_M1DQ8_1
IO_L50N_M1UDQSN_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1
IO_L47N_LDC_M1DQ1_1
IO_L47P_FWE_B_M1DQ0_1
IO_L50P_M1UDQS_1
IO_L53N_VREF_1
IO_L46N_FOE_B_M1DQ3_1
IO_L46P_FCS_B_M1DQ2_1
IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L51N_M1DQ13_1
IO_L52N_M1DQ15_1
IO_L30P_A21_M1RESET_1
IO_L30N_A20_M1A11_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L36P_A9_M1BA0_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1
IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L53P_1
IO_L61P_1
IO_L61N_1
XC6SLX9CSG324
DATA_D7_CFG_D0
3p3V
DNS R73
C47
1.0uF
NCS3
0R R76
3
SCC_TF
3
PCK
3
SCC_CLK
E17
G15
J14
J17
M15
R17
C40
0.1uF
C41
0.1uF
C42
0.1uF
C43
0.1uF
C44
0.1uF
C45
10uF
FPGA_CFG_CSN
DNS R75
DGND
DGND
0R R78
FPGA_CCLK
DNS R77
RSTUFF OPTIONS TO SUPPORT
SERIAL AND PARALLEL FPGA CONFIG
Figure 10. SPIO-4 FPGA SRAM and Configuration Interface
16
SPIO-4 Precision Signal-Path Controller Board
SNAU112A – December 2010 – Revised May 2018
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Copyright © 2010–2018, Texas Instruments Incorporated
PCB Layout, Schematics, and Bill of Materials
www.ti.com
XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE
3p3V
JUMER TO SELECT BANK VOUT
3p3V
DGND
J2
1
2
3
4
5
6
J4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
DBG2
DBG4
DBG6
DBG8
DBG10
DBG12
DBG14
DBG16
DBG18
DBG20
DBG22
DBG24
DBG26
DBG28
DBG30
DBG32
DBG34
DBG36
DBG38
DBG40
DBG42
DBG44
DBG46
DBG48
J3
U5-4
DBG1
DBG2
DBG3
DBG4
DBG5
DBG6
DBG7
DBG8
DBG9
DBG10
DBG11
DBG12
DBG13
DBG14
DBG15
DBG16
DBG17
DBG18
DBG19
DBG20
DBG21
DBG22
DBG23
DBG24
DBG25
DBG26
DBG27
DBG28
DBG29
DBG30
DBG31
3p3V
50PIN_MALE_HDR
DBG32
DBG33
DBG34
DBG35
DBG36
DBG37
DBG38
DBG39
DBG40
DBG41
DBG42
DBG43
DBG44
DBG45
DBG46
DBG47
DBG48
3p3V
R9 750R
R10 750R
R11 750R
R12 750R
D1
D2
GRN_LED
GRN_LED
D3 GRN_LED
D3
E4
E3
F6
F5
F4
F3
G6
H7
H6
H5
H4
H3
J7
J6
K6
J3
K3
K4
K5
L5
L7
L6
L4
C2
C1
D2
D1
E1
F2
F1
G1
G3
H1
H2
J1
K2
K1
L1
L2
M1
N2
N1
N3
P1
P2
P3
T1
T2
U1
U2
M3
P4
N4
M5
L3
IO_L54N_M3A11_3
VCCO_3
IO_L54P_M3RESET_3
VCCO_3
IO_L50P_M3WE_3
VCCO_3
IO_L55P_M3A13_3
VCCO_3
IO_L55N_M3A14_3
VCCO_3
IO_L51P_M3A10_3
VCCO_3
IO_L51N_M3A4_3
IO_L53N_M3A12_3
IO_L53P_M3CKE_3
IO_L49P_M3A7_3
IO_L49N_M3A2_3
IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3
IO_L47P_M3A0_3
IO_L47N_M3A1_3
IO_L45N_M3ODT_3
IO_L40P_M3DQ6_3
IO_L42N_GCLK24_M3LDM_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L43P_GCLK23_M3RASN_3
IO_L45P_M3A3_3
IO_L31P_3
IO_L39P_M3LDQS_3
IO_L83P_3
IO_L83N_VREF_3
IO_L52P_M3A8_3
IO_L52N_M3A9_3
IO_L50N_M3BA2_3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L46N_M3CLKN_3
IO_L46P_M3CLK_3
IO_L41N_GCLK26_M3DQ5_3
IO_L41P_GCLK27_M3DQ4_3
IO_L40N_M3DQ7_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L37N_M3DQ1_3
IO_L37P_M3DQ0_3
IO_L36N_M3DQ9_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L1N_VREF_3
IO_L34N_M3UDQSN_3
IO_L34P_M3UDQS_3
IO_L2N_3
IO_L33N_M3DQ13_3
IO_L33P_M3DQ12_3
IO_L32N_M3DQ15_3
IO_L32P_M3DQ14_3
IO_L36P_M3DQ8_3
IO_L2P_3
IO_L1P_3
IO_L31N_VREF_3
IO_L39N_M3LDQSN_3
D4 GRN_LED
E2
G4
J2
J5
M4
R2
BNK3_VDDIO
C49
1.0uF
DGND
1
2
3
3p3V
hdr_6pin
R72
10.0K
hdr_3pin
VTEST
3
3p3V
U5-5
A17
D15
B18
D16
R16
P13
V17
V2
A1
A18
B13
B7
C16
C3
D10
D5
E15
G12
G17
G2
G5
H10
H8
J11
J15
J4
J9
K10
K8
L11
L9
FPGA_TCK
FPGA_TDI
FPGA_TMS
FPGA_TDO
DGND
FPGA_DONE_N
3 FPGA_PRGM_N
PROGRAM V2
DONE V17
TP20
1
U5-6
E7
E8
F7
E6
G8
F8
G11
F10
F11
E11
D12
C12
C13
A13
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
F12
E12
U15
V15
T12
V12
N10
P11
M10
N9
M11
N11
N7
P8
M8
N8
N6
P7
DGND
TCK
TDI
TMS
TDO
SUSPEND
CMPCS_B_2
DONE_2
PROGRAM_B_2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC6SLX9CSG324
B1
B17
E14
E5
E9
G10
J12
K7
M9
P10
P14
P5
G7
H11
H9
J10
J8
K11
K9
L10
L8
M12
M7
M17
M2
M6
N13
R1
R14
R18
R4
R9
T16
U12
U6
V1
V18
1p2V
DGND
XC6SLX9CSG324
XC6SLX9CSG324
BNK3_VDDIO
C48
0.1uF
1
2
3
C53
0.1uF
C54
0.1uF
C55
0.1uF
C56
0.1uF
C57
0.1uF
C58
10uF
1p2V
C101
100uF
C50
0.1uF
C51
0.1uF
C52
0.1uF
C60
0.1uF
C61
0.1uF
3p3V
C62
10uF
TP1
C63
1.0uF
C100
100uF
DGND
DGND
TP3
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1
DBG1
DBG3
DBG5
DBG7
DBG9
DBG11
DBG13
DBG15
DBG17
DBG19
DBG21
DBG23
DBG25
DBG27
DBG29
DBG31
DBG33
DBG35
DBG37
DBG39
DBG41
DBG43
DBG45
DBG47
1
2
3
4
5
6
DGND
DGND
DGND
Figure 11. SPIO-4 FPGA DEBUG, JTAG Interfaces and Power
SNAU112A – December 2010 – Revised May 2018
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PCB Layout, Schematics, and Bill of Materials
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3p3V
DUT INPUT LEVEL SHIFTERS
U6
8
1
VCCB
VCCA
DUT_VDDIO
7
6
REF_CLKA
SDRDYN_A
B1
B2
A1
A2
DIRA2B
GND
8
7
6
VCCB
B1
B2
VCCA
A1
A2
DIRA2B
GND
7
6
SCS1N_A_R
R17 33R
SCLK_A
B1
B2
SCLK_A_R
A1
A2
DIRA2B
GND
1
U5-1
R15 33R
2
3
DUTMISO_A_R
5
4
CPUMISO_A_R
DUTMISO_A
CPUMISO_A 3
R53 0R
RSTUFF OPTIONS TO SUPPORT CPU ONLY
8
R18 33R
7
6
SCS0N_A_R
R19 33R
SMOSI_A
VCCB
B1
B2
SMOSI_A_R
VCCA
A1
A2
DIRA2B
GND
8
R20 33R
7
6
SCS2N_A_R
VCCB
B1
B2
VCCA
A1
A2
DIRA2B
GND
CAPABILITY (NO FPGA)
3p3V
CPU_CS1N_A 3
R55 0R
DUTCS1N_A
DUTSCLK_A
5
4
CPU_SCLK_A 3
R59 0R
1
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
SDRDYN_B
SCS1N_B
SCS2N_B
SCS3N_B
DGND
CPU_CS0N_A 3
2
3
R56 0R
DUTCS0N_A
DUTMOSI_A
5
4
CPU_MOSI_A 3
R57 0R
SN74LVC2T45SSOP
U10
SCS2N_A
DGND
2
3
SN74LVC2T45SSOP
U9
SCS0N_A
3
3p3V
DUT OUTPUT LEVEL SHIFTERS
U8
8
1
VCCB
VCCA
R16 33R
DUTDRDYN_A
DGND
SN74LVC2T45SSOP
SCS1N_A
DUTCLKIN 3
DUTCLKIN
DUTCLKIN_R R14 33R
DUTDRDYN_R
5
4
SN74LVC2T45SSOP
U7
SMISO_A
R13 33R
2
3
1
DGND
DUTCS2N_A
2
3
CPU_CS2N_A 3
R58 0R
5
4
SN74LVC2T45SSOP
DGND
C99
0.1uF
C98
0.1uF
C70
0.1uF
C71
0.1uF
C72
0.1uF
C73
10uF
DUT_PWR_EN
C68
0.1uF
C69
0.1uF
C105
0.1uF
C104
0.1uF
C106
1.0uF
A8
A11
A12
A10
A9
A14
A15
A16
A3
A5
A6
A4
A7
D4
C4
B2
A2
D6
C6
B3
B4
C5
C7
B6
D8
C8
B8
D9
C9
B9
D11
C11
C10
G9
F9
B11
B12
B14
F13
E13
C15
D14
C14
B16
IO_L33N_0
IO_L39N_0
IO_L41N_0
IO_L37N_GCLK12_0
IO_L35N_GCLK16_0
IO_L62N_VREF_0
IO_L64N_SCP4_0
IO_L66N_SCP0_0
IO_L4N_0
IO_L6N_0
IO_L8N_VREF_0
IO_L5N_0
IO_L10N_0
IO_L1P_HSWAPEN_0
IO_L1N_VREF_0
IO_L2P_0
IO_L2N_0
IO_L3P_0
IO_L3N_0
IO_L4P_0
IO_L5P_0
IO_L6P_0
IO_L10P_0
IO_L8P_0
IO_L11P_0
IO_L11N_0
IO_L33P_0
IO_L34P_GCLK19_0
IO_L34N_GCLK18_0
IO_L35P_GCLK17_0
IO_L36P_GCLK15_0
IO_L36N_GCLK14_0
IO_L37P_GCLK13_0
IO_L38P_0
IO_L38N_VREF_0
IO_L39P_0
IO_L41P_0
IO_L62P_0
IO_L63P_SCP7_0
IO_L63N_SCP6_0
IO_L64P_SCP5_0
IO_L65P_SCP3_0
IO_L65N_SCP2_0
IO_L66P_SCP1_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
B10
B15
B5
D13
D7
E10
XC6SLX9CSG324
DGND
DGND
DGND
R54 DNS
DUT_PRSNT_N 3
J6
3
DUT_SDA
3p3V_DUT
11 DUT_VDDIO
3 DUT_PWR_EN
SCS0N_A
SCLK_A
SMISO_A
SMOSI_A
REF_CLKA
DUT_SDA
DUT_VDDIO
DUT_PWR_EN
C109
1.0uF
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
DGND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
32PIN_FEM_HDR_RA
R79 1.5K
3p3V_DUT
SDRDYN_A
SCS1N_A
DUT_SCL
SCS2N_A
3p3V
DUT_SCL 3
DGND
C103
0.47uF
5p0V_DUT
C65
0.1uF
C67
1.0uF
5VDUT_FLTERD
SDRDYN_B
SCS1N_B
SCS2N_B
SCS3N_B
C46
0.1uF
C108
0.1uF
C66
0.1uF
C64
0.1uF
DGND
DGND
DUT_SCL
R80 1.5K DUT_SDA
Figure 12. SPIO4 FPGA GPSI32 Interface
18
SPIO-4 Precision Signal-Path Controller Board
SNAU112A – December 2010 – Revised May 2018
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Micro SD Card
3p3V
3p3V
R21
10.0K
R22
46.4K
R23
46.4K
R24
46.4K
3p3V
R25
46.4K
R26
10.0K
J7
3
3
3
DA2
DA3
CDA
3
CK
3
3
DA0
DA1
1
2
3
4
5
6
7
8
DA2
DA3
CDA
CK
DA0
DA1
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
CD
GND1
GND2
GND3
GND4
13
CD
CD
3
9
10
11
12
MICRO_SD
DGND
DGND
3p3V
C74
0.1uF
C75
10uF
DGND
Figure 13. SPIO-4 Micro SD Card
SNAU112A – December 2010 – Revised May 2018
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19
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USB, CPU JTAG
J8
USB TYPE B PORT
R27
2
2
6
5
3
2
4
1
VUSB_RTN
DHSD_P
DHSD_M
VUSB_DET
3,11 VUSB_DET
0R
R28
46.4K
VUSB
R29
68K
0R
C78
10pF
C76
0.1uF
C77
E_GND1
E_GND0
D+
DGND
VBUS
VUSB_IN
F1
4.7uF
DGND
DGND
DGND
DGND
3p3V
R30
10.0K
R31
10.0K
R32
10.0K
R33
10.0K
R34
10.0K
J9
IDC20-2.54mm
2
2
2
TDI
TMS
TCK
2
2
TDO
RSTN
R35
0R
1
3
5
7
9
11
13
15
17
19
VTref
Vsupply
nTRST
GND1
TDI
GND2
TMS
GND3
TCK
GND4
RTCK
GND5
TDO
GND6
nSRST
GND7
DBGRQ GND8
DBGACK GND9
2
4
6
8
10
12
14
16
18
20
C79
0.1uF
C80
10uF
DGND
DGND
Figure 14. USB, CPU JTAG
20
SPIO-4 Precision Signal-Path Controller Board
SNAU112A – December 2010 – Revised May 2018
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LP3910
5 Vin from Wall Supply
~5 Vin from USB
Vin
Switching
Li-Ion
Chrg
Circuit
Logic
& Cntrl
LDO1
FPGAIO
LDO2
1.8V_SRAM**
Buck1
1.2V_FPGA**
Buck2
3.3V_DUT_SW**
Buck/
Boost
3.3V_SPIO
FET
SW
3.3V_DUT
TO DUT
BOOST
Reg
NRST_PWR
3.3V_SPIO
5V
FPGAIO
I2C
1.8V_SRAM
3.3V_SPIO
1.2V_SRAM
J3
VDDIO
LDO
VDDcore
SAM3U
CPU
VDDIO
VDDIO
VDDCore
VDDIO
VDDCore
VDDIO
IO
SD Card
PSRAM
FPGA
J4
Figure 15. SPIO-4 Power Distribution
SNAU112A – December 2010 – Revised May 2018
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3p3V
3.3V, 1.2V, 1.8V, DUT Power Supply
1p8V
2
out
7
21
22
36
VIN
5VIN
PTC_1A_1812
D12
DIODE ZENER
C86
C38
C39
C87
C82
C83
C84
4.7uF
10uF
10uF
10uF
10uF
10uF
4.7uF
C85
0.1uF
46
42
41
DGND
PJ037A
DGND
DGND
47
R44 1.5K
3p3V
45
VUSB
R45 1.5K
VIN1
VIN2
VIN3
VIN4
VLDO1
VLDO2
VFB1
VBUCK1
BCKGND1
VDD1
VDD2
VDD3
VDDIO
VFB2
VBUCK2
BCKGND2
CHG_DET
USBPWR
VBBFB
VBBOUT
VBBL1
VBBL2
BBGND1
BBGND2
VBATT
A
B
29
27
3 SDA
3 SCL
SW2
PWR_ON
DGND
R49 10.0K
3
26
17
5
9
37
38
TP_PWRACK
TP_USBSP
1
TP9
DGND
USBISEL
TP10
1
2
44
43
VBATT
C102
J12
3p3V
+
-
TP_PWRACK
1
2
10uF
C92
100uF
1
TMP_SNS
12
11
DNS
R61 10.0K
TP8
D6
I2C_SDA
I2C_SCL
ON/~OFF
BUCK1EN
LDO2EN
POWERACK
USBSUSP
USBISEL
~NRST
ONSTAT
~IRQB
CHG
STAT
VBATT1
VBATT2
VBATT3
VREFH
I_SEN
I_REF
TS
ADC1
ADC2
DGND
AGND
DAP
LP3910
8
6
3p3V_DUT R36 750R
1p8V
18
20
19
5p0V_DUT R39 1.5K
C88
1
1V2_SW
2
L3
2.2uH
10uF
C89
10uF
DGND
R41 1.5K
3V3_DUT_SW
VIN
1
DGND
31
32
35
33
34
39
2
L4
DGND
2.2uH
3p3V
10uF
DGND
3V3_D_SW1 1
2.2uH
R46
R47
R48
10.0K 10.0K 10.0K
C91
1p2V
1
TP21
1
VREFH
ISEN
R51
4.64k_1%
IREF
R52
121K
C93
0.1uF
40
3
49
D11
650
NRST_PWR 2
ONSTAT 3
IRQ_PWR_N 3
TP_CHG
TP_STAT
4
10
48
R42
GRN_LED
10uF
DGND
3V3_D_SW2
DGND
14
30
13
15
16
3p3V
2
L5
D10
GRN_LED
C90
3p3V
D8
GRN_LED
3p3V
28
25
23
24
D7
GRN_LED
1p2V
3
2
RING
in
D9
1
F2
1 1
R37 0R
GRN_LED
C81
1.0uF
DGND
1
R43 10.0K
Q1
2
U11
DIODE_SCHOTTKY_1A
TIP
D5
GRN_LED
VTEST
TP5
J10
R38 750R
MMBT3904
TP22
DGND
DGND
DGND
1
3,9
J13
1
2
3
1
2
3
7
VUSB_DET
DGND
R60
DUT_VDDIO
10.0K
DUT_VDDIO_MEAS
DNS
R86
9.2K
R62 100K
DGND
Connector for using LI-Ion w/internal temp sense
DGND
C112
3p3V_DUT 100MHZ FERRITE
U14 0.1uF
3V3_DUT_SW
R63 680K
3
DUT_3VEN
4
6
5
VIN
R1/C1
OFF
VOUTA
VOUTB
R2
FDG6342L_SC70-6
R85
10.0K
3
2
C111
1
10uF
U12
8
9
C94
L8
10uF
R40
100K
1.0uF
DGND
DGND
DGND
DGND
3
CP1+
C96
CP1-
10
7
4
VIN1
VIN2
VOUT1
VOUT2
GND1
GND2
GND3
GND4
SD_N
3
5
6
DAP
5p0V_DUT
100MHZ FERRITE 100MHZ FERRITE
5V_DUT_OUT
C95
C97
10uF
C1+
C1-
DUT_5VEN
R64
10.0K
1
2
L6
L7
C107
C110
10uF
10uF
10uF
DGND
DGND
DGND
LM2750
DGND
DGND
Test Points
5p0V_DUT
1
3p3V_DUT
1
1p8V
1
DGND
1p2V
1
DGND
3p3V
1
1
TP18
1
TP16
TP11
TP12
TP13
TP14
TP15
Figure 16. 3.3-V, 1.2-V, 1.8-V, and DUT Power Supplies
22
SPIO-4 Precision Signal-Path Controller Board
SNAU112A – December 2010 – Revised May 2018
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Copyright © 2010–2018, Texas Instruments Incorporated
PCB Layout, Schematics, and Bill of Materials
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3.3
Bill of Materials (BOM)
Table 5 shows the bill of materials (BOM) for the SPIO-4 precision signal-path controller board.
Table 5. Bill of Materials
Item
Manufacturer Name
Manufacturer No.
1
CAP CER 10000PF 25V Y5V 0603
Description
Qty
1
C1
Reference
MURATA ELECTRONICS (VA)
GRM188F51E103ZA01D
2
CAP CER .47UF 10V X7R 0603
1
C103
TAIYO YUDEN (VA)
LMK107B7474KA-T
YAGEO (VA)
CC0603KRX7R7BB104
3
CAP .10UF 16V CERAMIC X7R 0603
58
C2,C4,C6,C7,C8,C9,C10,C11,C12,C14,C15,C16,
C17,C18,C20,C23,C26,C27,C31,C33,C35,C36,C40,
C41,C42,C43,C44,C46,C48,C50,C51,C52,C53,C54,
C55,C56,C57,C60,C61,C64,C65,C66,C68,C69,
C70,C71,C72,C74,C76,C79,C85,C93,C98,C99,C104,
C105, C108,C112
4
CAP CERAMIC 10PF 50V NP0 0603
2
C21,C78
KEMET (VA)
C0603C100J5GACTU
5
CAP CER 15PF 50V C0G 5% 0603
4
C24,C25,C29,C30
TDK CORPORATION (VA)
C1608C0G1H150J
6
CAP CER 4.7UF 10V Y5V 0603
5
C28,C32,C77,C84,C86
MURATA ELECTRONICS (VA)
GRM188F51A475ZE20D
TDK CORPORATION (VA)
C1608Y5V0J106Z
7
CAP CER 10UF 6.3V Y5V 0603
22
C3,C5,C13,C19,C22,C37,C38,C39,C45,C58,C62,
C73,C75,C80,C82,C83,C87,C88,C89,C90,C91,C102
8
CAP CER 1.0UF 10V X7R 0603
9
C34,C47,C49,C59,C63,C67,C81,C106,C109
TAIYO YUDEN (VA)
LMK107B7105KA-T
9
CAP CER 100UF 10V X5R 1210
3
C92,C100,C101
TAIYO YUDEN (VA)
LMK325BJ107MM-T
10
CAP CER 10UF 10V X5R 0805
6
C94,C95,C97,C107,C110,C111
JOHANSON DIELECTRICS INC (VA)
100R15X106KV4E
11
CAP CER 1.0UF 16V X7R 20% 1206
1
C96
TDK CORPORATION (VA)
C3216X7R1C105M/0.85
LG M67K-G1J2-24-0-2-R18-Z
12
LED TOPLED 570NM GREEN CLR SMD
10
D1,D2,D3,D4,D5,D6,D7,D8,D10,D11
OSRAM OPTO SEMICONDUCTORS
INC(VA)
13
DIODE ZENER 6.2V 3W DO214AA
1
D12
MICRO COMMERCIAL CO (VA)
3SMBJ5920B-TP
14
DIODE SCHOTTKY 1A 20V SOD-123
1
D9
MICRO COMMERCIAL CO (VA)
MBRX120LF-TP
15
RES 0.0 OHM 1/2W 1210 SMD
1
F1
VISHAY/DALE (VA)
CRCW12100000Z0EA
16
PTC RESETTABLE 1.10A 16V 1812
1
F2
BOURNS INC (VA)
MF-MSMF110/16-2
17
CONN HEADER VERT 5POS .100 TIN
1
J1
TYCO ELECTRONICS AMP
640454-5
18
CON PWR JCK 2.0 X 6.5MM W/O SW
1
J10
CUI INC
PJ-037A
19
CONN HEADER 10POS 2MM VERT T/H
1
J14
3M
951110-8622-AR
20
CONN HEADER VERT SGL 6POS GOLD
1
J2
3M
961106-6404-AR
21
BERGSTIK II .100" SR STRAIGHT
1
J3
FCI
68000-203HLF
22
CONN FEMALE 32POS DL .1" R/A TIN
1
J6
SULLINS CONNECTOR SOLUTIONS
PPTC162LJBN-RC
23
CONN MICRO SD R/A HING TYPE SMD
1
J7
HIROSE ELECTRIC CO LTD (VA)
DM3C-SF
24
CONN RCPT USB TYPE B R/A PCB
1
J8
FCI
61729-0010BLF
25
CONN HEADER 2.54MM 20POS GOLD
1
J9
SULLINS CONNECTOR SOLUTIONS
SBH11-PBPC-D10-ST-BK
26
BERGSTIK II .100" SR STRAIGHT
1
JP1
FCI
68001-202HLF
SNAU112A – December 2010 – Revised May 2018
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23
PCB Layout, Schematics, and Bill of Materials
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Table 5. Bill of Materials (continued)
Item
24
Description
Qty
Reference
Manufacturer Name
Manufacturer No.
27
INDUCTOR 10UH 100MA 0805
2
L1,L2
MURATA ELECTRONICS (VA)
LQM21FN100M70L
28
INDUCTOR 2.2UH 1.20A 20% 1210
3
L3,L4,L5
TDK CORPORATION (VA)
NLCV32T-2R2M-PFR
29
FERRITE CHIP 2700 OHM 200MA 0805
3
L6,L7,L8
MURATA ELECTRONICS (VA)
BLM21BD272SN1L
30
TRANSISTOR NPN GP 40V SOT23
1
Q1
MICRO COMMERCIAL CO (VA)
MMBT3904-TP
31
RES 33.0 OHM 1/10W 1% 0603 SMD
8
R13,R14,R15,R16,R17,R18,R19,R20
YAGEO (VA)
RC0603FR-0733RL
32
RES 39 OHM 1/10W 5% 0603 SMD
2
R2,R3
PANASONIC - ECG (VA)
ERJ-3GEYJ390V
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT10K0
33
RES 10K OHM 1/10W 1% 0603 SMD
17
R21,R26,R30,R31,R32,R33,R34,R43,R46,R47,R48,
R49,R60,R61, R64,R72,R85
34
RES 46.4K OHM 1/10W 1% 0603 SMD
5
R22,R23,R24,R25,R28
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT46K4
35
RES 68K OHM 1/10W 5% 0603 SMD
1
R29
PANASONIC - ECG (VA)
ERJ-3GEYJ683V
36
RES 1.5K OHM 1/10W 5% 0603 SMD
7
R39,R41,R44,R45,R79,R80,R82
STACKPOLE ELECTRONICS INC (VA)
RMCF0603JT1K50
37
RES 6.8K OHM 1/10W 1% 0603 SMD
1
R4
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT6K80
38
RES 100K OHM 1/10W 1% 0603 SMD
2
R40,R62
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT100K
39
RES 649 OHM 1/10W 1% 0603 SMD
1
R42
PANASONIC - ECG (VA)
ERJ-3EKF6490V
STACKPOLE ELECTRONICS INC (VA)
RMCF0603ZT0R00
40
RES 0.0 OHM 1/10W 0603 SMD
15
R5,R6,R27,R35,R37,R53,R55,R56,R57,R58,R59,
R66,R74,R76,R78
41
RES 4.64K OHM 1/10W 1% 0603 SMD
1
R51
PANASONIC - ECG (VA)
ERJ-3EKF4641V
42
RES 121K OHM 1/10W 1% 0603 SMD
1
R52
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT121K
43
RES 680K OHM 1/10W 5% 0603 SMD
1
R63
PANASONIC - ECG (VA)
ERJ-3GEYJ684V
44
RES 9.1K OHM 1/10W 5% 0603 SMD
1
R86
PANASONIC - ECG (VA)
ERJ-3GEYJ912V
45
RES 750 OHM 1/10W 1% 0603 SMD
6
R9,R10,R11,R12,R36,R38
STACKPOLE ELECTRONICS INC (VA)
RMCF0603FT750R
OMRON ELECTRONICS INC-ECB DIV
(VA)
B3U-1000P
46
SWITCH TACT SPST W/O GND SMD
2
SW1,SW2
47
PC TEST POINT MINIATURE SMT
14
TP1,TP3,TP4,TP5,TP7,TP11,TP12,TP13,TP14,TP15,
KEYSTONE ELECTRONICS (VA)
TP16,TP17, TP18,TP19
5015
48
ATSAM3U4EA-AU-ND
1
U1
ATSAM3U4EA-AU-ND
49
LP3910SQ-AA
1
U11
LP3910SQ-AA
50
LM2750LD-5.0CT-ND
1
U12
51
IC LOAD SWITCH INTEGRATED SC70-6
1
U14
FAIRCHILD SEMICONDUCTOR (VA)
FDG6342L
52
IC PSRAM 128MBIT 70NS 54VFBGA
1
U4
MICRON TECHNOLOGY INC (VA)
MT45W8MW16BGX-701 IT TR
53
XC6SLX16-2CSG324C
1
U5
54
IC BUS TRANSCVR 2BIT N-INV SM8
5
U6,U7,U8,U9,U10
TEXAS INSTRUMENTS (VA)
SN74LVC2T45DCTR
55
CRYSTAL 12.00 MHZ 8PF SMD
1
Y1
NDK (VA)
NX5032GA 12MHZ AT-W
56
CRYSTAL 32.768KHZ 12.5PF SMD
1
Y2
ABRACON CORPORATION (VA)
ABS10-32.768KHZ-T
57
PCB Fab
1
Fab
TEXAS INSTRUMENTS (VA)
551600474-001
LM2750LD-5.0CT-ND
XC6SLX16-2CSG324C
SPIO-4 Precision Signal-Path Controller Board
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25
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
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You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
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This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
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