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SRC4190IDBRQ1

SRC4190IDBRQ1

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SSOP28

  • 描述:

    IC 192KHZ SAMPL RATE CONV 28SSOP

  • 数据手册
  • 价格&库存
SRC4190IDBRQ1 数据手册
SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 192-kHz STEREO ASYNCHRONOUS SAMPLE-RATE CONVERTER Check for Samples: SRC4190-Q1 FEATURES 1 • • • • • • • • • • • • • Qualified for Automotive Applications Automatic Sensing of the Input-To-Output Sampling Ratio Wide Input-to-Output Sampling Range: 16:1 to 1:16 Supports Input and Output Sampling Rates up to 212 kHz Dynamic Range: 128 dB (–60 dBFS Input, BW = 20 Hz to fS/2, A-Weighted) THD+N: –125 db (0 dBFS Input, BW = 20 Hz to fS/2) Attenuates Sampling and Reference Clock Jitter High Performance, Linear Phase Digital Filtering Flexible Audio Serial Ports Master or Slave Mode Operation Supports I2S, Left Justified, Right Justified, and TDM Data Formats Supports 16, 18, 20, or 24-Bit Audio Data TDM Mode Allows Daisy Chaining of up to Eight Devices • • • • • • • • • Supports 24-, 20-, 18-, or 16-Bit Input and Output Data All Output Data Is Dithered From the Internal 28-Bit Data Path Low Group Delay Option for Interpolation Filter Soft Mute Function Bypass Mode Power Down Mode Operates From a Single 3.3-V Power Supply Small SSOP-28 Package Pin Compatible With the SRC4192, AD1895, and AD1896 APPLICATIONS • • • • • • Digital Mixing Consoles Digital Audio Workstations Audio Distribution Systems Broadcast Studio Equipment High-End A/V Receivers General Digital Audio Processing DESCRIPTION The SRC4190 is an asynchronous sample rate converter designed for professional and broadcast audio applications. The SRC4190 combines a wide input-to-output sampling ratio with outstanding dynamic range and low distortion. Input and output serial ports support standard audio formats, as well as a Time Division Multiplexed (TDM) mode. Flexible audio interfaces allow the SRC4190 to connect to a wide range of audio data converters, digital audio receivers and transmitters, and digital signal processors. The SRC4190 is a standalone pin-programmed device, with control pins for mode, data format, mute, bypass, and low group delay functions. The SRC4190 may be operated from a single 3.3-V power supply. A separate digital I/O supply (VIO) operates over the 1.65-V to 3.6-V supply range, allowing greater flexibility when interfacing to current and future generation signal processors and logic devices. The SRC4190 is available in an SSOP-28 package. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE SSOP – DB (2) Reel of 2000 ORDERABLE PART NUMBER SRC4190IDBRQ1 TOP-SIDE MARKING SRC4190Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com DB PACKAGE (TOP VIEW) LGRP RCKI NC SDIN BCKI LRCKI VIO DGND BYPAS IFMT0 IFMT1 IFMT2 RST MUTE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MODE2 MODE1 MODE0 BCKO LRCKO SDOUT VDD DGND TDMI OFMT0 OFMT1 OWL0 OWL1 RDY TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. LGRP 1 Low group delay control input (active high) RCKI 2 Reference clock input NC 3 No internal connection SDIN 4 Audio serial data input BCKI 5 Input port bit clock I/O LRCKI 6 Input port left/right word clock I/O VIO 7 Digital I/O supply, 1.65 V to VDD DGND 8 Digital ground BYPAS 9 ASRC bypass control input (active high) IFMT0 10 Input port data format control input IFMT1 11 Input port data format control input IFMT2 12 Input port data format control input RST 13 Reset input (active low) MUTE 14 Output mute control input (active high) RDY 15 ASRC ready status output (active low) OWL1 16 Output port data word length control input OWL0 17 Output port data word length control input OFMT1 18 Output port data format control input OFMT0 19 Output port data format control input TDMI 20 TDM data input (connect to DGND when not in use) DGND 21 Digital ground VDD 22 Digital core supply, 3.3 V SDOUT 23 Audio serial data output LRCKO 24 Output port left/right word clock I/O BCKO 25 Output port bit clock I/O MODE0 26 Serial port mode control input MODE1 27 Serial port mode control input MODE2 28 Serial port mode control input 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD Core supply voltage range –0.3 V to 4 V VIO I/O supply voltage range –0.3 V to 4 V VI Digital input voltage –0.3 V to 4 V TA Operating free-air temperature range –40°C to 85°C Tstg Storage temperature range –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (1) Resolution 24 bits fSIN Input sampling frequency 4 212 kHz fSOUT Output sampling frequency 4 212 kHz Input:output sampling ratio Dynamic range Total harmonic distortion + noise 1:16 Downsampling BW = 20 Hz to fSOUT/2, –60-dBFS Input, fIN = 1 kHz, Unweighted (add 3 dB to specification for A-weighted result) BW = 20 Hz to fSOUT/2, 0-dBFS Input, fIN = 1 kHz, Unweighted 16:1 44.1 kHz : 48 kHz 125 48 kHz : 44.1 kHz 125 48 kHz : 96 kHz 125 44.1 kHz : 192 kHz 125 96 kHz : 48 kHz 125 192 kHz : 12 kHz 125 192 kHz : 32 kHz 125 192 kHz : 48 kHz 125 32 kHz : 48 kHz 125 12 kHz : 192 kHz 125 44.1 kHz : 48 kHz –125 48 kHz : 44.1 kHz –125 48 kHz : 96 kHz –125 44.1 kHz : 192 kHz –125 96 kHz : 48 kHz –125 192 kHz : 12 kHz –125 192 kHz : 32 kHz –125 192 kHz : 48 kHz –125 32 kHz : 48 kHz –125 12 kHz : 192 kHz –125 dB dB Interchannel gain mismatch 0 dB Interchannel phase deviation 0 ° Mute attenuation (1) Upsampling 24-bit word length, A-weighted –128 dB Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 3 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Interpolation Filter Characteristics Passband Passband ripple 0.4535 × fSIN Hz ±0.007 dB 0.5465 × fSIN Hz Transition band 0.4535 × fSIN Stop band 0.5465 × fSIN Hz –125 dB Stop band attenuation Normal group delay time (LGRP = 0) 102.53125 / fSIN s Low group delay time (LGRP = 1) 70.53125 / fSIN s Digital Decimation Filter Characteristics Passband Passband ripple Transition band 0.4535 × fSOUT Stop band 0.5465 × fSOUT Stop band attenuation 0.4535 × fSOUT Hz ±0.008 dB 0.5465 × fSOUT Hz Hz –125 dB 36.46875 / fSOUT Group delay s Digital I/O Characteristics VIH High-level input voltage 0.7 × VIO VIO V VIL Low-level input voltage 0 0.3 × VIO V IIH High-level input current 0.5 10 μA IIL Low-level input current 0.5 10 μA VOH High-level output voltage IO = –4 mA VIO V VOL Low-level output voltage IO = 4 mA CIN Input capacitance 4 0.8 × VIO 0 0.2 × VIO 3 Submit Documentation Feedback V pF Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 128 × fSMIN 50 MHz 20 1/(128 × fSMIN) Switching Characteristics fRCKI RCKI frequency (2) (3) tRCKIP RCKI pulse duration tRCKIH RCKI pulse duration, high 0.4 × tRCKIP ns tRCKIL RCKI pulse duration, low 0.4 × tRCKIP ns tRSTL RST pulse duration, low 500 ns tLRIS LRCKI to BCKI setup time 10 ns tSIH BCKI pulse duration, high 10 ns tSIL BCKI pulse duration, low 10 ns tLDIS SDIN data setup time 10 ns tLDIH SDIN data hold time 10 tDOPD SDOUT data delay time tDOH SDOUT data hold time 2 ns tSOH BCKO pulse duration, high 10 ns tSOL BCKO pulse duration, low 5 ns tLROS LRCKO setup time 10 ns tLROH LRCKO hold time 10 ns tTDMS TDMI data setup time 10 ns tTDMH TDMI data hold time 10 ns ns ns 10 ns Power Supplies VDD Core supply voltage VIO Digital I/O supply voltage IDDPD VDD supply current, power down IDDD VDD supply current, dynamic IIOPD VIO supply current, power down IIOD VIO supply current, dynamic PD Total power dissipation, power down PD (2) (3) Total power dissipation, dynamic 3 3.3 3.6 V 1.65 3.3 3.6 V 100 μA RST = 0, No clocks VDD = 3.3 V, VIO = 3.3 V fSIN = fSOUT = 192 kHz 66 RST = 0, No clocks fSIN = fSOUT = 192 kHz mA 100 2 RST = 0, No clocks μA mA 660 μW VDD = 3.3 V, VIO = 3.3 V fSIN = fSOUT = 192 kHz 225 mW fSMIN = min (fSIN, fSOUT) fSMAX = max (fSIN, fSOUT) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 5 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (12kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (12kHz:192kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 20k 40k 60k 80k 96k 0 40k 60k 80k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (32kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (32kHz:48kHz) 0 –60 –20 –70 96k –80 –40 –90 –60 –100 dBFS dBFS 20k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 0 24k 10k 15k 20k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:48kHz) 0 –60 –20 –70 24k –80 –40 –90 –60 –100 dBFS dBFS 5k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 24k 0 Frequency (Hz) 6 5k 10k 15k 20k 24k Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 10k 20k 30k 40k 48k 0 20k 30k 40k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:192kHz) 0 –60 –20 –70 48k –80 –40 –90 –60 –100 dBFS dBFS 10k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 20k 40k 60k 80k 0 96k 40k 60k 80k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (48kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:44.1kHz) 0 –60 –20 –70 96k –80 –40 –90 –60 –100 dBFS dBFS 20k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 22k 0 Frequency (Hz) 5k 10k 15k 20k 22k Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 7 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (48kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 10k 20k 30k 40k 48k 0 20k 30k 40k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (48kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:192kHz) 0 –60 –20 –70 48k –80 –40 –90 –60 –100 dBFS dBFS 10k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 20k 40k 60k 80k 96k 0 40k 60k 80k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (96kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:44.1kHz) 0 –60 –20 –70 96k –80 –40 –90 –60 –100 dBFS dBFS 20k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 22k 0 Frequency (Hz) 8 5k 10k 15k 20k 22k Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (96kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:48kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 24k 0 10k 15k 20k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (96kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:192kHz) 0 –60 –20 –70 24k –80 –40 –90 –60 –100 dBFS dBFS 5k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 20k 40k 60k 80k 96k 0 20k 40k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:12kHz) 80k 96k FFT with 1kHz INPUT TONE at –60dBFS (192kHz:12kHz) 0 –60 –20 –70 –80 –40 –90 –60 –100 dBFS dBFS 60k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 1k 2k 3k 4k 5k 6k 0 Frequency (Hz) 1k 2k 3k 4k 5k 6k Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 9 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:32kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:12kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 2.5k 5k 7.5k 10k 12.5k 15k 16k 0 5k 7.5k 10k 12.5k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:44.1kHz) 0 –60 –20 –70 15k 16k –80 –40 –90 –60 –100 dBFS dBFS 2.5k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 22k 0 10k 15k 20k 22k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:48kHz) 0 –60 –20 –70 –80 –40 –90 –60 –100 dBFS dBFS 5k Frequency (Hz) –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 0 5k 10k 15k 20k 24k 0 10 5k 10k 15k 20k 24k Frequency (Hz) Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 10k 20k 30k 40k 48k 0 20k 30k 40k Frequency (Hz) FFT with 20kHz INPUT TONE at 0dBFS (44.1kHz:48kHz) FFT with 20kHz INPUT TONE at 0dBFS (48kHz:44.1kHz) 0 0 –20 –20 –40 –40 –60 –60 –80 –100 –100 –120 –140 –140 –160 –160 5k 10k 15k 20k 48k –80 –120 0 10k Frequency (Hz) dBFS dBFS 0 24k 0 5k 10k 15k 20k 22k Frequency (Hz) Frequency (Hz) FFT with 20kHz INPUT TONE at 0dBFS (48kHz:96kHz) FFT with 20kHz INPUT TONE at 0dBFS (96kHz:48kHz) –20 –40 –40 –60 –60 dBFS dBFS 0 –20 –80 –100 –80 –100 –120 –120 –140 –140 –160 –160 0 10k 20k 30k 40k 48k 0 5k 10k 15k 20k 24k Frequency (Hz) Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 11 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FFT with 80kHz INPUT TONE at 0dBFS (192kHz:192kHz) THD+N vs INPUT AMPLITUDE fIN = 1kHz (44.1kHz:48kHz) 0 Total Harmonic Distortion+Noise (dB) –100 –20 –40 dBFS –60 –80 –100 –120 –140 –160 0 20k 40k 60k 80k –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –140 96k –120 Frequency (Hz) Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –110 –115 –120 –125 –130 –135 –140 –145 –120 –100 –80 –60 –40 –20 –20 0 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –140 0 –120 –100 –80 –60 –40 –20 Input Amplitude (dBFS) Input Amplitude (dBFS) THD+N vs INPUT AMPLITUDE fIN = 1kHz (96kHz:48kHz) THD+N vs INPUT AMPLITUDE fIN = 1kHz (44.1kHz:192kHz) 0 –100 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –40 –100 –105 –100 –105 –110 –115 –120 –125 –130 –135 –140 –145 –120 –100 –80 –60 –40 –20 0 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –140 Input Amplitude (dBFS) 12 –60 THD+N vs INPUT AMPLITUDE fIN = 1kHz (48kHz:96kHz) –100 –150 –140 –80 Input Amplitude (dBFS) THD+N vs INPUT AMPLITUDE fIN = 1kHz (48kHz:44.1kHz) –150 –140 –100 –120 –100 –80 –60 –40 –20 0 Input Amplitude (dBFS) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) THD+N vs INPUT FREQUENCY WITH 0dBFS INPUT (44.1kHz:48kHz) THD+N vs INPUT AMPLITUDE fIN = 1kHz (192kHz:44.1kHz) –100 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –100 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –140 –100 –80 –60 –40 –20 –115 –120 –125 –130 –135 –140 –145 0 0 5k 10k 15k Input Amplitude (dBFS) Input Frequency (Hz) THD+N vs INPUT FREQUENCY WITH 0dBFS INPUT = 1kHz (48kHz:44.1kHz) THD+N vs INPUT FREQUENCY WITH 0dBFS (48kHz:96kHz) 20k –100 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –110 –150 –120 –100 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 0 5k 10k 15k 20k 0 5k 10k 15k Input Frequency (Hz) Input Frequency (Hz) THD+N vs INPUT FREQUENCY WITH 0dBFS (96kHz:48kHz) THD+N vs INPUT FREQUENCY WITH 0dBFS (44.1kHz:192kHz) –100 20k –100 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –105 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 –105 –110 –115 –120 –125 –130 –135 –140 –145 –150 0 5k 10k 15k 20k 0 5k 10k 15k 20k Input Frequency (Hz) Input Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 13 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) LINEARITY with fIN = 200Hz (44.1kHz:48kHz) THD+N vs INPUT FREQUENCY WITH 0dBFS (192kHz:44.1kHz) –105 –110 Output Amplitude (dBFS) Total Harmonic Distortion+Noise (dB) –100 –115 –120 –125 –130 –135 –140 –145 –150 0 5k 10k 15k 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 20k –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Input Frequency (Hz) LINEARITY with fIN = 200Hz (48kHz:96kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 Output Amplitude (dBFS) Output Amplitude (dBFS) LINEARITY with fIN = 200Hz (48kHz:44.1kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Input Amplitude (dBFS) Input Amplitude (dBFS) LINEARITY with fIN = 200Hz (96kHz:48kHz) LINEARITY with fIN = 200Hz (44.1kHz:192kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 Output Amplitude (dBFS) Output Amplitude (dBFS) –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Input Amplitude (dBFS) 14 0 Input Amplitude (dBFS) 0 Input Amplitude (dBFS) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VDD = 3.3 V, and VIO = 3.3 V (unless otherwise noted) FREQUENCY RESPONSE with 0dBFS INPUT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 dBFS Output Amplitude (dBFS) LINEARITY with fIN = 200Hz (192kHz:44.1kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 192kHz:48kHz 192kHz:32kHz 192kHz:96kHz 0 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 10k 20k 0 30k 40k 50k 60k Frequency (Hz) Input Amplitude (dBFS) PASS BAND RIPPLE (192k:48k) 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10 –0.11 –0.12 –0.13 –0.14 –0.15 (dBFS) (dBFS) PASS BAND RIPPLE (48k:48k) 0 5k 10k 15k 20k 22k 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10 –0.11 –0.12 –0.13 –0.14 –0.15 0 Input Frequency (Hz) 5k 10k 15k 20k 22k Input Frequency (Hz) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 15 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com DETAILED DESCRIPTION The SRC4190 is an asynchronous sample rate converter (ASRC) designed for professional audio applications. Operation at input and output sampling frequencies up to 212 kHz is supported, with an input/output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and Total Harmonic Distortion + Noise (THD+N) are achieved by employing high performance and linear phase digital filtering. Digital filtering options allow for lower group delay processing. The audio input and output ports support standard audio data formats, as well as a TDM interface mode. Word lengths of 24, 20, 18, and 16 bits are supported. Both ports may operate in slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port may operate in master mode while the other remains in slave mode. In master mode, the LRCK and BCK clocks are derived from the reference clock input, RCKI. The flexible configuration of the input and output ports allows connection to a wide variety of audio data converters, interface devices, digital signal processors, and programmable logic. A bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio data, or nonaudio control or status data. A soft mute function is available providing artifact-free operation while muting the audio output signal. The mute attenuation is typically –128 dB. Functional Block Diagram Figure 1 shows a functional block diagram of the SRC4190. Audio data is received at the input port, clocked by either the audio data source in Slave mode or by the SRC4190 in Master mode. The output port data is clocked by either the audio data source in Slave mode, or by the SRC4190 in Master mode. The input data is passed through interpolation filters which up-sample the data, which is then passed on to the re-sampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI, LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the coefficients needed for re-sampling function. The output of the re-sampler is then passed on to the decimation filter. The decimation filter performs down-sampling and anti-alias filtering functions. 16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 LRCKI Audio Input Port BCKI SDIN fSIN Interpolation Filters 16fSIN Re-Sampler 16fSOUT MODE [2:0] IFMT [2:0] REFCLK OFMT [1:0] LRCKI OWL [1:0] Control Logic MUTE Rate Estimator BYPAS LGRP RST LRCKO fSOUT RDY Decimation Filters LRCKO Audio Output Port BCKO SDOUT TDMI VDD DGND Power Reference Clock RCKI REFCLK VIO DGND Figure 1. Functional Block Diagram Reference Clock The SRC4190 requires a reference clock for operation. The reference clock is applied at the RCKI input, pin 2. Figure 2 illustrates the reference clock connections and requirements for the SRC4190. The reference clock may operate at 128fS, 256fS, or 512fS, where fS is the input or output sampling frequency. The maximum external reference clock input frequency is 50 MHz. SRC4190 RCKI 2 From External Clock Source 50MHz max tRCKIP RCKI tRCKIH tRCKIL tRCKIP > 20ns min tRCKIH > 0.4 tRCKIP tRCKIL > 0.4 tRCKIP Figure 2. Reference Clock Input Connections and Timing Requirements Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 17 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com Reset and Power Down Operation The SRC4190 may be reset using the RST input (pin 13). There is no internal power on reset, so the user should force a reset sequence after power up in order to initialize the device. In order to force a reset, the reference clock input must be active, with an external clock source supplying a valid reference clock signal (see Figure 2). The user must assert RST low for a minimum of 500 ns and then bring RST high again to force a reset. Figure 3 shows the reset timing for the SRC4190. The SRC4190 also supports a power-down mode. Powerdown mode may be set by holding the RST input low. RCKI RST tRSTL > 500ns Figure 3. Reset Pulse Width Requirement Audio Port Modes The SRC4190 supports seven serial port modes, which are shown in Table 1. The audio port mode is selected using the MODE0 (pin 26), MODE1 (pin 27), and MODE2 (pin 28) inputs. In slave mode, the port LRCK and BCK clocks are configured as inputs, and receive their clocks from an external audio device. In master mode, the LRCK and BCK clocks are configured as outputs, being derived from the reference clock input (RCKI). Only one port can be set to master mode at any given time, as indicated in Table 1. Table 1. Setting the Serial Port Modes MODE2 MODE1 MODE0 0 0 0 Both input and output ports are slave mode SERIAL PORT MODE 0 0 1 Output port is master mode with RCKI = 128fS 0 1 0 Output port is master mode with RCKI = 512fS 0 1 1 Output port is master mode with RCKI = 256fS 1 0 0 Both input and output ports are slave mode 1 0 1 Input port is master mode with RCKI = 128fS 1 1 0 Input port is master mode with RCKI = 512fS 1 1 1 Input port is master mode with RCKI = 256fS Input Port Operation The audio input port is a three-wire synchronous serial interface that may operate in either slave or master mode. The SDIN input (pin 4) is the serial audio data input. Audio data is input at this pin in one of three standard audio data formats: Philips I2S, left justified, or right justified. The audio data word length may be up to 24 bits for I2S and left justified formats, while the right justified format supports 16-, 18-, 20-, or 24-bit data. The data formats are shown in Figure 4, while critical timing parameters are shown in Figure 5 and listed in the Electrical Characteristics table. The bit clock is either an input or output at BCKI (pin 5). In slave mode, BCKI is configured as an input pin, and may operate at rates from 32fS to 128fS, with a minimum of one clock cycle per data bit. In master mode, BCKI operates at a fixed rate of 64fS. 18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 Left Channel Right Channel LRCKO BCKI SDIN MSB LSB MSB LSB (a) Left Justified Data Format LRCKI BCKI MSB SDIN LSB MSB LSB (b) Right Justified Data Format LRCKI BCKI SDIN MSB LSB MSB LSB (c) I2S Data Format 1/fS Figure 4. Input Data Formats LRCKI tLRIS tSIH BCKI tLDIS tSIL SDIN tLDIH Figure 5. Input Port Timing The left/right word clock, LRCKI (pin 6), may be configured as an input or output pin. In slave mode, LRCKI is an input pin, while in master mode LRCKI is an output pin. In either case, the clock rate is equal to fS, the input sampling frequency. The LRCKI duty cycle is fixed to 50% for master mode operation. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 19 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com Table 2 illustrates data format selection for the input port. The IFMT0 (pin 10), IFMT1 (pin 11), and IFMT2 (pin 12) inputs are utilized to set the input port data format. Table 2. Input Port Data Format Selection IFMT2 IFMT1 IFMT0 INPUT PORT DATA FORMAT 0 0 0 24-bit left justified 0 0 1 24-bit I2S 0 1 0 Unused 0 1 1 Unused 1 0 0 16-bit right justified 1 0 1 18-bit right justified 1 1 0 20-bit right justified 1 1 1 24-bit right justified Output Port Operation The audio output port is a four-wire synchronous serial interface that may operate in either slave or master mode. The SDOUT output (pin 23) is the serial audio data output. Audio data is output at this pin in one of four data formats: Philips I2S, left justified, right justified, or TDM. The audio data word length may be 16, 18, 20, or 24 bits. For all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data formats (with the exception of TDM mode) are shown in Figure 6, while critical timing parameters are shown in Figure 7 and listed in the Electrical Characteristics table. The TDM format and timing are shown in Figure 11 and Figure 12, respectively, while examples of standard TDM configurations are shown in Figure 13 and Figure 14. The bit clock is either input or output at BCKO (pin 25). In slave mode, BCKO is configured as an input pin, and may operate at rates from 32fS to 128fS, with a minimum of one clock cycle for each data bit. The exception is the TDM mode, where the BCKO must operate at N × 64fS, where N is equal to the number of SRC4190 devices included on the TDM interface. In master mode, BCKO operates at a fixed rate of 64fS for all data formats except TDM, where BCKO operates at the reference clock (RCKI) frequency. Additional information regarding TDM mode operation is included in the Application Information section of this data sheet. The left/right word clock, LRCKO (pin 24), may be configured as an input or output pin. In slave mode, LRCKO is an input pin, while in master mode it is an output pin. In either case, the clock rate is equal to fS, the output sampling frequency. The clock duty cycle is fixed to 50% for I2S, left justified, and right justified formats in master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in master mode. 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 Left Channel Right Channel LRCKO BCKO SDOUT MSB LSB MSB LSB (a) Left Justified Data Format LRCKO BCKO MSB SDOUT LSB MSB LSB (b) Right Justified Data Format LRCKO BCKO SDOUT MSB LSB MSB LSB (c) I2S Data Format 1/fS Figure 6. Output Data Formats LRCKO tSOH BCKO tSOL tDOPD SDOUT tDOH Figure 7. Output Port Timing Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 21 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com Table 3 illustrates data format selection for the output port. The OFMT0 (pin 19), OFMT1 (pin 18), OWL0 (pin 17), and OWL1 (pin 16) inputs are utilized to set the output port data format and word length. Table 3. Output Port Data Format Selection OFMT1 OFMT0 OUTPUT PORT DATA FORMAT 0 0 Left justified 0 1 I2S 1 0 TDM 1 1 Right justified OWL1 OWL0 OUTPUT PORT DATA WORD LENGTH 0 0 24 bits 0 1 20 bits 1 0 18 bits 1 1 16 bits Bypass Mode The SRC4190 includes a bypass function, which routes the input port data directly to the output port, bypassing the ASRC function. Bypass mode may be invoked by forcing the BYPAS input (pin 9) high. For normal ASRC operation, the BYPAS pin should be set to 0. No dithering is applied to the output data in bypass mode; digital attenuation and mute functions are also unavailable in this mode. Soft Mute Function The soft mute function of the SRC4190 may be invoked by forcing the MUTE input (pin 14) high. The Soft mute function slowly attenuates the output signal level down to all zeroes plus ±4 LSB of dither. This provides an artifact-free muting of the audio output port. Ready Output The SRC4190 includes an active-low ready output named RDY (pin 15). This is an output from the rate estimator block, which indicates that the input-to-output sampling frequency ratio has been determined. The ready signal can be used as a flag or indicator output. The ready signal can also be connected to the active-high MUTE input (pin 14) to provide an auto-mute function, so that the output port is muted when the rate estimator is in transition. 22 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 APPLICATION INFORMATION This section of the data sheet provides practical applications information for hardware and systems engineers who will be designing the SRC4190 into end equipment. Recommended Circuit Configuration The typical connection diagram for the SRC4190 is shown in Figure 8. Recommended values for power-supply bypass capacitors are included. These capacitors should be placed as close to the IC package as possible. From Control Logic SRC4190 1 2 3 Reference Clock 4 5 6 7 8 9 10 11 12 13 14 Audio Input Device From/To Control Logic LGRP RCKI NC MODE2 MODE1 MODE0 SDIN BCKI LRCKI VIO DGND BYPAS IFMT0 IFMT1 IFMT2 RST MUTE BCKO LRCKO SDOUT VDD DGND TDMI OFMT0 OFMT1 OWL0 OWL1 RDY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD = +3.3V VIO = +1.65V to V DD 10µF Audio Output Device To Pin 7 To Pin 22 To Pin 8 To Pin 21 0.1µF 0.1µF 10µF Figure 8. Typical Connection Diagram Interfacing to Digital Audio Receivers and Transmitters The SRC4190 input and output ports are designed to interface to a variety of audio devices, including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications. Texas Instruments manufactures the DIR1703 digital audio interface receiver and DIT4096/4192 digital audio transmitters to address these applications. Figure 9 illustrates interfacing the DIR1703 to the SRC4190 input port. The DIR1703 operates from a single 3.3-V supply, which requires the VIO supply (pin 7) for the SRC4190 to be set to 3.3 V for interface compatibility. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 23 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 www.ti.com SRC4190 DIR1703 LRCKI LRCKO AES3, S/PDIF Input RCV DIN BCKO BCKI DATA SDIN SCKO RCLI Clock Generator Clock Select Assumes V IO = +3.3V for SRC4190 Figure 9. Interfacing the SRC4190 to the DIR1703 Digital Audio Interface Receiver Figure 10 shows the interface between the SRC4190 output port and the DIT4096 or DIT4192 audio serial port. Once again, the VIO supplies for both the SRC4190 and DIT4096/4192 are set to 3.3 V for compatibility. SRC4190 DIT4096, DIT4192 LRCKO SYNC TX+ BCKO SCLK TXÐ SDOUT SDATA RCKI AES3, S/PDIF OUTPUT MCLK REF Clock Generator DIT Clock Generator Clock Select Assumes V IO = +3.3V for SRC4190 and DIT4096, DIT4192 Figure 10. Interfacing the SRC4190 to the DIT4096/4192 Digital Audio Interface Transmitter Like the SRC4190 output port, the DIT4096 and DIT4192 audio serial port may be configured as a Master or Slave. In cases where the SRC4190 output port is set to Master mode, it is recommended to use the reference clock source (RCKI) as the master clock source (MCLK) for the DIT4096/4192, to ensure that the transmitter is synchronized to the SRC4190 output port data. TDM Applications The SRC4190 supports a TDM output mode, which allows multiple devices to be daisy-chained together to create a serial frame. Each device occupies one sub-frame within a frame, and each sub-frame carries two channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each channel. The audio data for each channel is left justified within the allotted 32 bits. Figure 11 illustrates the TDM frame format, while Figure 12 shows the TDM input timing parameters, which are listed in the Electrical Characteristics table of this data sheet. 24 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 SRC4190-Q1 www.ti.com SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 LRCKO BCKO SDOUT Left Right Left Sub-Frame 1 Right Sub-Frame 2 Left Right Sub-Frame N One Frame = 1/f s N = Number of Daisy-Chained Devices One Sub-Frame contains 64 bits, with 32 bits per channel. For each channel, the audio data is Left Justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits . Figure 11. TDM Frame Format tLROS LRCKO tLROH BCKO tTDMS TDMI tTDMH Figure 12. TDM Input Timing The frame rate is equal to the output sampling frequency, fS. The BCKO frequency for the TDM interface is N × 64fS, where N is the number of devices included in the daisy chain. For Master mode, the output BCKO frequency is fixed to the reference clock (RCKI) input frequency. The number of devices that can be daisy-chained in TDM mode is dependent upon the output sampling frequency and the BCKO frequency, leading to the following numerical relationship: Number of daisy-chained devices = (fBCKO / fS) / 64 Where: fBCKO = Output port bit clock (BCKO), 27.136 MHz maximum fS = Output port sampling (or LRCKO) frequency, 212 kHz maximum This relationship holds true for both slave and master modes. Figure 13 and Figure 14 show typical connection schemes for the TDM mode. Although the TMS320C671x DSP family is shown as the audio processing engine in these figures, other TI digital signal processors with a multi-channel buffered serial port (McBSPTM) may also function with this arrangement. Interfacing to processors from other manufacturers is also possible. See Figure 7 in this data sheet, along with the equivalent serial port timing diagrams shown in the DSP data sheet, to determine compatibility. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 25 SRC4190-Q1 SBFS034A – SEPTEMBER 2008 – REVISED OCTOBER 2009 SRC4190 Slave #N TDMI www.ti.com SRC4190 Slave #2 TDMI SDOUT SRC4190 Slave #1 SDOUT TDMI TMS320C671x McBSP SDOUT DRn FSRn LRCKO LRCKO LRCKO BCKO BCKO BCKO RCKI RCKI RCKI n = 0 or 1 CLKRn CLKIN or CLKSn Clock Generator Figure 13. TDM Interface Where All Devices are Slaves SRC4190 Master TDMI SRC4190 Slave #2 SDOUT DRn LRCKO LRCKO LRCKO FSRn BCKO BCKO BCKO RCKI RCKI RCKI SDOUT TDMI TMS320C671x McBSP SRC4190 Slave #1 SDOUT TDMI n = 0 or 1 CLKRn CLKIN or CLKSn Clock Generator Figure 14. TDM Interface Where One Device is Master to Multiple Slaves Pin Compatibility With the Analog Devices AD1895 and AD1896 The SRC4190 is pin-compatible and function-compatible with the AD1895 and AD1896 when observing the guidelines indicated in the following paragraphs. Power Supplies. To ensure compatibility, the VDD_IO and VDD_CORE supplies of the AD1895 and AD1896 must be set to 3.3 V, while the VIO and VDD supplies of the SRC4190 must be set to 3.3 V. Pin 1 connection. For the AD1895, pin 1 is a no connect (NC) pin. For the SRC4190, pin 1 functions as the low group delay selection input and should not be left unconnected. Pin 1 must be connected to either digital ground or the VIO supply, dependent upon the desired group delay. Crystal Oscillator. The SRC4190 does not have an on-chip crystal oscillator. An external reference clock is required at the RCKI input (pin 2). Reference Clock Frequency. The reference clock input frequency for the SRC4190 must be no higher than 30 MHz, in order to match the master clock frequency specification of the AD1895 and AD1896. In addition, the SRC4190 does not support the 768fS reference clock rate. Master Mode Maximum Sampling Frequency. When the input or output ports are set to Master mode, the maximum sampling frequency must be limited to 96 kHz in order to support the AD1895 and AD1896 specification. This is despite the fact that the SRC4190 supports a maximum sampling frequency of 212 kHz in Master mode. The user should consider building an option into the design to support the higher sampling frequency of the SRC4190. Matched Phase Mode. Due to the internal architecture of the SRC4190, it does not require or support the matched phase mode of the AD1896. Given multiple SRC4190 devices, if all reference clock (RCKI) inputs are driven from the same clock source, the devices will be phase matched. 26 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): SRC4190-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SRC4190IDBRQ1 ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SRC4190Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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SRC4190IDBRQ1
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  • 1+67.847201+8.20690
  • 10+61.2934010+7.41410
  • 25+58.4363025+7.06850
  • 100+50.71630100+6.13470
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  • 500+44.16250500+5.34200
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