User’s Guide
July 2004
SBAU096
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the absolute operating conditions shown in
Table 2−1.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
+70°C. The EVM is designed to operate properly with certain components above +70°C as
long as the input and output ranges are maintained. These components include but are not
limited to linear regulators, switching transistors, pass transistors, and current sense
resistors. These types of devices can be identified using the EVM schematic located in the
EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Contents
Preface
About This Manual
This document contains the information required to setup and operate the
SRC4194EVM evaluation module. For a more detailed description of the
SRC4194, please refer to the product datasheet available from the Texas Instruments web site at http://www.ti.com. Additional support documents are
listed in the sections of this guide entitled Related Documentation from Texas Instruments and Additional Documentation.
How to Use This Manual
Throughout this document, the term EVM and the phrase evaluation module
are synonymous with the SRC4194EVM.
Chapter 1 provides a product overview for the SRC4194 four-channel asynchronous sample rate converter. The SRC4194EVM block diagram and primary features are also discussed.
Chapter 2 provides general information regarding EVM handling and unpacking, as well as absolute operating conditions for power supplies and input/output connections.
Chapter 3 provides general hardware descriptions and configuration information for the EVM. The information in this chapter is designed to guide the user
in the setup of the EVM.
Chapter 4 includes the EVM electrical schematic, printed circuit board (PCB)
layout, and the bill of materials
Contents
iii
Contents
Information About Cautions
This document contains cautions. The information in a caution is provided for
your protection. Please read each caution carefully.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
iv
Contents
Related Documentation From Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in the assembly of the SRC4194EVM. These documents
are available from the TI web site at http://www.ti.com. The last character of
the literature number corresponds to the document revision, which is current
at the time of the writing of this User’s Guide. Newer revisions may be available
from the TI web site, or by calling the Texas Instruments Literature Response
Center at (800) 477−8924 or the Product Information Center at (972)
644−5580. When ordering, identify the document(s) by both title and literature
number.
Data Sheets:
Literature Number:
SRC4194
SBFS025A
DIT4192
SBOS229B
PLL1705
SLES046A
REG1117
SBVS001B
SN74ALVC125
SCES110E
SN74ALVC244
SCES188B
SN74ALVC245
SCES271B
SN74LVC1G04
SCES214M
SN74LVC1G08
SCES217L
SN74LVC244A
SCAS414U
Additional Documentation
The following documents or references provide information regarding selected non-TI components used in the assembly of the SRC4194EVM. These
documents are available from the corresponding manufacturer.
Document:
Manufacturer:
CS8414 Data Sheet
Cirrus Logic, web site: http://www.cirrus.com
HCM49 Series Crystals
Citizen, web site: http://www.citizencrystals.com
Contents
v
Contents
If You Need Assistance
If you have questions regarding either the use of this evaluation module or the
information contained in the accompanying documentation, please contact
the Texas Instruments Product Information Center at (972) 644−5580 or visit
the TI Semiconductor Online Technical Support pages at http://www.ti.com.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It may
generate, use, or radiate radio frequency energy and has not been tested for
compliance with the limits of computing devices pursuant to sub−part J of part
15 of the FCC regulations, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
All trademarks are the property of their respective owners.
vi
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
SRC4194 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
SRC4194 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
SRC4194EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
SRC4194EVM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
1-2
1-3
1-5
1-6
2
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Electrostatic Discharge Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Unpacking the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Absolute Maximum Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-2
2-3
2-4
3
Hardware Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
SRC4194 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.1 SRC4194 Hardware (or Standalone) Mode Configuration . . . . . . . . . . . . . . . . . 3-4
3.2.2 SRC4194 Software Mode Configuration Via The Host Port . . . . . . . . . . . . . . . . 3-6
3.3
Audio Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4
Audio Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5
Reference Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6
TDM Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
4
Schematic, PCB Layout, and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Contents
vii
Contents
1−1.
1−2.
3−1.
3−2.
3−3.
3−4.
4−1.
4−2.
4−3.
4−4.
4−5.
4−6.
4−7.
4−8.
SRC4194 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
SRC4194EVM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
SRC4194EVM Power Supply Configuration and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Input Port External Connections and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Output Port External Connections and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Reference Clock Generation, Connections, and Configuration . . . . . . . . . . . . . . . . . . . . . 3-10
SRC4194EVM Schematic Diagram, Page 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
SRC4194EVM Schematic Diagram, Page 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Top Side Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Bottom Side Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Top Layer (Component Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Ground Plane Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Power Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Bottom layer (Solder Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
2−1.
3−1.
3−2.
3−3.
3−4.
3−5.
3−6.
4−1.
viii
Absolute Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Common Configurations using a +5V Supply and an Optional EXT VIO Supply . . . . . . . . 3-3
Setting the Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Hardware Mode Setup Matrix Using Switches SW1, SW2, SW4 and SW5 (x = A or B) 3-5
Transmitter Clock Divider Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Transmitter Stereo/Mono Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
PLL Configuration for U25 and U28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Chapter 1
This chapter provides a brief technical overview for the SRC4194 four-channel
audio asynchronous sample rate converter, as well as a general description
and feature list for the SRC4194EVM.
Topic
Page
1.1
SRC4194 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
SRC4194 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
SRC4194EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4
SRC4194EVM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Introduction
1-1
SRC4194 Product Overview
1.1 SRC4194 Product Overview
The SRC4194 is a four-channel, asynchronous sample rate converter
(ASRC), implemented as two stereo sections referred to as SRC A and SRC
B. Operation at input and output sampling frequencies up to 212kHz is
supported, with a continuous input/output sampling ratio range of 16:1 to 1:16.
Excellent dynamic range and THD+N are achieved by employing high
performance, linear phase digital filtering with better than 140dB of image
rejection. The digital filters provide settings for lower latency processing,
including low group delay options for the interpolation filter and a direct
down-sampling option for the decimation filter. Digital de-emphasis filtering is
also included, supporting 32kHz, 44.1kHz, and 48kHz input sampling
frequencies.
The audio input and output ports support standard audio data formats, as well
as a time division multiplexed (TDM) format. Word lengths of 24, 20, 18, and
16 bits are supported. Input and output ports may operate in Slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port may operate in Master mode while the other remains in Slave
mode. In Master mode, the LRCK and BCK clocks are derived from the reference clock inputs, either RCKIA or RCKIB. The flexible configuration options
for the input and output ports allows connection to a variety of audio data converters, digital audio interface devices, and digital signal processors.
A bypass mode is included, which allows audio data to be passed directly from
the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through compressed or encoded audio data, as well
as non-audio data (that is, control or status information).
A soft mute function is available for the SRC4194 in both Hardware and Software modes. Digital output attenuation is available only in Software mode.
Both soft mute and digital attenuation functions provide artifact-free operation.
The mute attenuation is typically −144dB, while the digital attenuation function
is programmable from 0dB to −127.5dB in 0.5dB steps.
The SRC4194 includes a four-wire SPI port, which is used to access on-chip
control and status registers in Software mode. The SPI port facilitates interfacing to microprocessors or digital signal processors that support synchronous
serial peripherals. In Hardware (or Standalone) mode, dedicated control pins
are provided for the majority of the SRC4194 functions. These pins can be either hardwired or driven by logic or host control.
1-2
SRC4194 Functional Block Diagram
1.2 SRC4194 Functional Block Diagram
Figure 1−1 shows a functional block diagram of the SRC4194. The SRC4194
is segmented into two stereo SRC sections referred to as SRC A and SRC B.
Each section can operate independently from the other. Each section has its
own set of configuration pins in Hardware mode, and its own bank of control
and status registers in Software mode.
SRC A and SRC B have identical operations. Audio data is received at the input serial port, clocked by either the audio source device in Slave mode, or by
the SRC4194 in Master mode. The output port data is clocked by either the
audio output device in Slave mode, or by the SRC4194 in Master mode. The
input data is passed through interpolation filters that up-sample the data,
which is then passed on to the re-sampler. The rate estimator compares the
input and output sampling frequencies by comparing LRCKI, LRCKO, and a
reference clock. The results of the rate estimation are used to configure the
re-sampler coefficients and data pointers.
The output of the re-sampler is passed on to either the decimation filter or
direct down-sampler function. The decimation filter performs down-sampling
and antialias filtering functions, and is required when the output sampling
frequency is equal to or lower than the input sampling frequency. The direct
down-sampling function does not provide any filtering, and may be used in
cases when the output sampling frequency is greater than the input sampling
frequency. The advantage of the direct down-sampling function is a significant
reduction in the group delay associated with the decimation function, allowing
lower latency processing.
For additional information regarding the SRC4194, please refer to the product
datasheet available from the TI web site, located at http://www.ti.com.
Introduction
1-3
SRC4194 Functional Block Diagram
Figure 1−1. SRC4194 Functional Block Diagram
LRCKIA
BCKIA
SDINA
Input
Serial
Port
Digital
De−Emphasis and
Interpolation Filters
Digital
Decimation
Filter
Re−Sampler
Output
Serial
Port
LRCKOA
BCKOA
SDOUTA
TDMIA
fsOUT
fsIN
Rate
Estimator
RDYA
RATIOA
RCKIA
IFMTA0
LGRPA0
LGRPB0
IFMTA1
LGRPA1
LGRPB1
DDNA
IFMTA2
OFMTA0
OFMTA1
Control
SRC A
OWLA0
OWLA1
BYPA
LRCKIB
BCKIB
SDINB
DDNB
DEMA0
DEMB0
DEMA1
DEMB1 (CDOUT)
MODEA0
MODEB0 (CS)
MODEA1
MODEB1 (CCLK)
MODEA2
MODEB2 (CDIN)
MUTEA
Input
Serial
Port
Digital
De−Emphasis and
Interpolation Filters
Digital
Decimation
Filter
Re−Sampler
Rate
Estimator
fsOUT
RDYB
RATIOB
1-4
SPI Port
and
Reset
MUTEB
fsIN
RCKIB
Control
SRC B
Output
Serial
Port
IFMTB0
IFMTB1
IFMTB2
OFMTB0
OFMTB1
OWLB0
OWLB1
BYPB
H/S
RST
LRCKOB
BCKOB
SDOUTB
TDMIB
VIO
DGND
VDD18 (2)
VDD33 (2)
DGND
REGEN
SRC4194EVM Features
1.3 SRC4194EVM Features
The SRC4194EVM provides a convenient platform for evaluating the performance and functionality of the SRC4194 product. Key EVM features include:
- Supports operation from a single +5V power supply
- Flexible power-supply configuration using either onboard voltage regula-
tors or external supplies
- Buffered input and output serial ports support connection to external hard-
ware and test systems
- Two 75Ω AES3 inputs with onboard receivers supporting input sampling
rates up to 108kHz
- Two 75Ω AES3 outputs supporting sampling rates up to 192kHz
- Flexible SRC reference clock generation using onboard PLL circuitry or
external clock sources
- Supports hardware mode operation using onboard switches
- Supports software mode operation using the buffered host port interface
Introduction
1-5
SRC4194EVM Functional Block Diagram
1.4 SRC4194EVM Functional Block Diagram
The SRC4194EVM functional block diagram is shown in Figure 1−2. Besides
the SRC4194, there are multiple audio input and output port interfaces, reference clock generation circuitry, switches for Hardware mode configuration and
logic functions, and a buffered host port interface for communications with the
SRC4194 SPI port when configured for Software mode operation. Chapter 3
provides operational and configuration details for the various hardware functions included on the EVM board.
Figure 1−2. SRC4194EVM Functional Block Diagram
AES3 Tx
DIT4192
AES
OUT B
DIT
CLOCK B
SW8
OUTPUT
PORT B
H
D
R
H
D
R
SW4
SW5
4−CHANNEL ASYNCHRONOUS
SAMPLE RATE CONVERTER
SRC4194
SW8
INPUT
PORT B
CLOCK GEN
PLL1705
RCKIB
PORT
BUFFERS
AES3 Rx
CS8414
AES
IN B
SRC B
EXT CLOCK
SW10
HOST PORT
BUFFER
PORT
BUFFERS
HDR
RCKIA
INPUT
PORT A
H
D
R
CLOCK GEN
PLL1705
SW6
SW10
H
D
R
1-6
SRC A
EXT CLOCK
Power Supplies are not shown in this diagram. Refer
to Figure 3−1 for power supply configuration details
PORT
BUFFERS
SW6
AES
OUT A
SW2
SW1
AES3 Rx
CS8414
AES
IN A
OUTPUT
PORT A
PORT
BUFFERS
HOST
PORT
AES3 Tx
DIT4192
DIT
CLOCK A
Chapter 2
This chapter provides information regarding SRC4194EVM handling and
unpacking, as well as absolute operating conditions.
Topic
Page
2.1
Electrostatic Discharge Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Unpacking the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
Absolute Maximum Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 2-4
Getting Started
2-1
Electrostatic Discharge Warning
2.1 Electrostatic Discharge Warning
Failure to observe proper ESD handling precautions may result in
damage to EVM components.
Many of the components on the SRC4194EVM are susceptible to damage by
electrostatic discharge (ESD). Customers are advised to observe proper ESD
handling procedures when unpacking and handling the EVM, including the
use of a grounded wrist strap at an approved ESD workstation. Failure to observe ESD handling procedures may result in damage to EVM components.
2-2
Unpacking the EVM
2.2 Unpacking the EVM
Upon opening the SRC4194EVM package, please check to make sure that the
following items are included:
- One SRC4194EVM
- One printed copy of the SRC4194 data sheet
- One printed copy of the SRC4194EVM User’s Guide
If any of these items are missing, please contact the Texas Instruments Product Information Center nearest you to inquire about replacements.
Getting Started
2-3
Absolute Maximum Operating Conditions
2.3 Absolute Maximum Operating Conditions
Exceeding the Absolute Operating Conditions may result in
damage to the evaluation module and/or the equipment connected
to it.
The user should be aware of the absolute operating conditions for the
SRC4194EVM. Exceeding these conditions may result in damage to the EVM
and possibly the equipment connected to it. Table 2−1 summarizes the critical
data points.
Table 2−1. Absolute Operating Conditions
MIN
MAX
UNIT
+5V
+4.5
+6.0
V
EXT +1.8V
+1.65
+2.0
V
EXT +3.3V
+3.0
+3.6
V
EXT VIO(1)
+1.65
+3.6
V
Power Supplies
Input Port A and B, Output Port A and B, Host Port, SRC A and B EXT Clock, and DIT
Clock A and B(1)
VIH
VIL
VIO + 0.3
−0.3
V
V
AES IN A and B Ports
VIH
+7.0
V
VIL
−0.5
V
(1) VIO may be set to +1.8V or +3.3V using onboard regulators, or +1.65V to +3.6V using an
external power supply connected to the EXT VIO terminal located on connector J14.
2-4
Chapter 3
This chapter provides hardware description and configuration information for
the SRC4194EVM.
Topic
Page
3.1
Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
SRC4194 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
SRC4194 Hardware (or Standalone) Mode Configuration . . . . . . . . . . . . 3-4
SCR4194 Software Mode Configuration Via The Host Port . . . . . . . . . . . 3-6
3.3
Audio Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4
Audio Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5
Reference Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6
TDM Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Hardware Description and Configuration
3-1
Power Supply Configuration
3.1 Power Supply Configuration
Changes to settings for jumpers J15 through J17, as well as
changes to the state of the REGEN element of switch SW2, should
be performed with all power supplies connected to terminal block
J14 powered off, thereby avoiding potential damage to the EVM and
external components.
The SRC4194EVM provides several options for power-supply configuration
using onboard regulators and/or external supplies. Onboard jumpers and a
switch are used to select the available options. Figure 3−1 illustrates the EVM
power-supply configuration using jumpers J15 through J17 and terminal block
J14. Table 3−1 summarizes the common jumper configurations based upon
a setup using a +5V supply and an optional EXT VIO supply.
Figure 3−1. SRC4194EVM Power Supply Configuration and Jumpers
+5V
GND
GND +1.8V +3.3V
EXT
VIO
REG +1.8V
6
4
2
J14
EXT EXT
+1.8V +3.3V
EXT
VIO
REG +3.3V
5
3
1
VIO
U32
+5V
J15
EXT VIO
J16
REG +3.3V
NC(1)
+3.3V
REG
REG +3.3V
VDD33
EXT +3.3V
U33
J17
+1.8V
REG
REG +1.8V
NC(1)
REG +1.8V
VDD18
NOTE: (1) NC = not connected.
EXT +1.8V
Referring to Figure 3−1, the SRC4194EVM includes two onboard linear voltage regulators, U32 and U33, which are used to derive +1.8V and +3.3V from
a single +5V external power supply. The outputs of the two regulators may be
connected to the onboard VDD18, VDD33, or VIO power busses using jumpers J15 through J17. The jumpers also allow for connection to external power
supplies using terminal block J14.
Table 3−1 summarizes five common supply configurations for the
SRC4194EVM. Jumper settings for J15 through J17 are indicated, as well as
the state of the REGEN element of switch SW2. The user is reminded to power
down all supplies connected to terminal block J14 of the EVM before changing
the jumper and switch configurations.
3-2
Power Supply Configuration
Table 3−1. Common Configurations using a +5V Supply and an Optional EXT VIO Supply
Description
J15
J16(1)
J17(1)
REGEN
(SW2)
Core Voltage = +1.8V
using onboard regulator (U33)
—
NC
REG + 1.8V
LO
VIO = +1.8V
using onboard regulator (U33)
REG + 1.8V
Core Voltage = +1.8V
using onboard regulator (U33)
—
NC
REG + 1.8V
LO
VIO = +3.3V
using onboard regulator (U32)
REG + 3.3V
Core Voltage = +3.3V
using onboard regulator (U32)
—
REG + 3.3V
NC
HI
VIO = 3.3V
using onboard regulator (U32)
REG + 3.3V
Core Voltage = +1.8V
using onboard regulator (U33)
—
NC
REG + 1.8V
LO
VIO = +1.65V to 3.6V
using EXT VIO supply
EXT VIO
Core Voltage = +3.3V
using onboard regulator (U32)
—
REG + 3.3V
NC
HI
VIO = +1.65V to 3.6V
using EXT VIO supply
EXT VIO
Case
1
2
3
4
5
1)
NC = not connected.
Hardware Description and Configuration
3-3
SRC4194 Configuration Modes
3.2 SRC4194 Configuration Modes
The SRC4194 can be set to one of two configuration modes: Hardware (or
Standalone) or Software (via a four-wire SPI port). The H/S element of switch
SW2 is used to set the mode. Table 3−2 summarizes the H/S mode switch settings.
Table 3−2. Setting the Configuration Mode
3.2.1
H/S Switch Setting
SRC4194 Configuration Mode
LO
Software Mode
HI
Hardware (or Standalone) Mode
SRC4194 Hardware (or Standalone) Mode Configuration
In Hardware mode, switches SW1, SW2, SW4, and SW5 are used to set the
dedicated control pins to either a low or high logic level. The switches correspond one-to-one with the pin names of the SRC4194 device. Table 3−3 summarizes the switch functions and available settings for each element of switch
SW1, SW2, SW4, and SW5.
In addition to the switches already mentioned, a momentary pushbutton switch
(SW3) is used for the SRC4194 reset function. The RST input (pin 21) of the
SRC4194 is normally pulled high via an external 10kΩ resistor connected to
the VIO supply bus. When the pushbutton is pressed, the switch shorts the
RST pin to ground. Releasing the switch then causes the RST pin to be pulled
high again. By momentarily pressing and then releasing SW3, the user can
generate a reset pulse for the SRC4194.
3-4
IFMTx1
LO
LO
HI
HI
LO
LO
HI
HI
IFMTx0
LO
HI
LO
HI
LO
HI
LO
HI
LO
LO
LO
LO
HI
HI
HI
HI
IFMTx2
LO
HI
LO
HI
OFMTx0
LO
LO
HI
HI
OFMTx1
LO
HI
LO
HI
OWLx0
LO
LO
HI
HI
OWLx1
LO
HI
BYPx
LO
HI
LO
HI
LRGPx0
LO
LO
HI
HI
LGRPx1
LO
HI
DDNx
LO
HI
LO
HI
DEMx0
LO
LO
HI
HI
DEMx1
LO
HI
LO
HI
LO
HI
LO
HI
MODEx0
LO
LO
HI
HI
LO
LO
HI
HI
MODEx1
Table 3−3. Hardware Mode Setup Matrix Using Switches SW1, SW2, SW4 and SW5 (x = A or B)
LO
LO
LO
LO
HI
HI
HI
HI
MODEx2
LO
HI
MUTEx
Function/Description
Input Port Data Format
24-bit Left Justified
24-bit I2S
Unused
Unused
16-bit Right Justified
18-bit Right Justified
20-bit Right Justified
24-bit Right Justified
Output Port Data Format
Left Justified
I2S
TDM
Right Justified
Output Port Word Length
24 bits
20 bits
18 bits
16 bits
Bypass Mode
Disabled
Enabled
Interpolation Filter Group Delay
Buffer 64 samples before resampling
Buffer 32 samples before resampling
Buffer 16 samples before resampling
Buffer 8 samples before resampling
Decimation Mode
Decimation Filter Enabled
Direct Downsampling Enabled
De-Emphasis Filter Function
Disabled
Enabled for fs = 48kHz
Enabled for fs = 44.1kHz
Enabled for fs = 32kHz
Input & Output Serial Port Mode
Input and Output Ports are Slave
Output Port is Master w/ RCKI =128fs
Output Port is Master w/ RCKI =512fs
Output Port is Master w/ RCKI =256fs
Input and Output Ports are Slave
Input Port is Master w/ RCKI =128fs
Input Port is Master w/ RCKI =512fs
Input Port is Master w/ RCKI =256fs
Output Soft Mute
Disabled
Enabled
SRC4194 Configuration Modes
Hardware Description and Configuration
3-5
3.2.2
SRC4194 Software Mode Configuration Via The Host Port
In Software mode, the SRC4194 relies upon an external host device to program the internal control registers via the four-wire SPI port. The SPI port is
accessed using the Host Port header, connector J1. The header is buffered
by U2, an octal buffer IC with tri-state outputs. The buffer outputs are enabled
only when the H/S element of switch SW2 is set to the LO state. When H/S is
HI, the buffer outputs are set to a high-impedance state.
The Host Port header provides a convenient interface point for connection to
an external host device, such as a microprocessor, a digital signal controller/
processor, or a digital input/output card installed in a PC.
Refer to the SRC4194 datasheet for a description of the SPI port protocol and
control register definitions.
3-6
Audio Input Ports
3.3 Audio Input Ports
The SRC4192EVM includes four audio input ports, two each for the SRC A and
SRC B sections of the SRC4194. Each section is provided with an
AES3/SPDIF-compatible input, along with a buffered I/O header. Figure 3−2
illustrates the input port external connections and associated switch settings.
Figure 3−2. Input Port External Connections and Configuration
Switch SW6 or SW8
x_DIR
LO = Output Enabled
HI = Output Disabled
NOTE: x = A or B
U14 or U24
CS8414−CS
Switch SW6 or SW8
x_IM/S
LO = SRC is Slave
HI = SRC is Master
U1
SRC4194IPAG
SCK
BCKx
FSYNC
LRCKx
SDATA
SDINx
RCKIx
RCKIx
SDINx
LRCKx
BCKx
From
RCKIx
Source
2
1
INPUT PORT A (J5)
or
INPUT PORT B (J10)
The SRC A section input port selection and Master/Slave mode operation are
configured using the A_DIR and A_IM/S elements of switch SW6. The SRC
B section input port selection and Master/Slave mode operation are configured using the B_DIR and B_IM/S elements of switch SW8.
The AES IN A (J6) and AES IN B (J11) connectors accept 75Ω coaxial cable
connections terminated with RCA plugs. The onboard AES3 receivers (U14
and U24) recover audio clocks and data from the AES3 encoded input stream.
The receivers are configured to output 24-bit I2S-formatted audio data with a
serial bit (or data) clock rate of 64fs and a left/right word clock rate of fs, where
fs is the frame or sampling rate of the incoming AES3-formatted data stream.
Sampling rates up to 108kHz are supported. The AES IN A and B input ports
provide a convenient, standard interface to consumer and professional audio
equipment, as well as common audio test systems.
The buffered input serial ports INPUT PORT A (J5) and INPUT PORT B (J10)
support Left-Justified, Right-Justified, and I2S-formatted audio data with word
lengths up to 24 bits and sampling rates up to 212kHz. The input ports may
be operated in either Slave or Master mode, but must match the input port setup for the SRC4194 device, as defined in Table 3−3. The buffered serial input
ports provide a convenient method for interfacing to audio devices that support
an audio serial data interface, including external digital audio receivers, audio
data converters, and digital signal processing components.
3-7
Audio Output Ports
3.4 Audio Output Ports
The SRC4192EVM includes four audio output ports, two each for the SRC A
and SRC B sections of the SRC4194. Each section is provided with an
AES3/SPDIF-compatible output, along with a buffered I/O header. Figure 3−3
illustrates the output port external connections and associated switch settings.
The SRC A section output port selection and Master/Slave mode operation are
configured using switch SW6. The SRC B section output port selection and
Master/Slave mode operation are configured using switch SW8.
The AES OUT A (J3) and AES OUT B (J8) connectors accept 75Ω coaxial
cable connections terminated with RCA plugs. The onboard AES3 transmitters (U7 and U17) provide the AES3 encoded data streams for each output.
Both transmitters are configured to accept 24-bit I2S-formatted audio data at
sampling rates up to 192kHz. The AES OUT A and B output ports provide a
convenient, standard interface to consumer and professional audio equipment, as well as common audio test systems.
Figure 3−3. Output Port External Connections and Configuration
U1
SRC4194IPAG
Switch SW6 or SW8
x_OM/S
LO = SRC is Slave
HI = SRC is Master
NOTE: x = A or B
U7 or U17
DIT4192IPW
BCKx
SCLK
LRCKx
SYNC
SDOUTx
SDATA
MCLK M/S
TDMIx
RCKIx
RCKIx
TDMIx
SDOUTx
LRCKx
BCKx
From
RCKIx
Source
2
1
OUTPUT PORT A (J2)
or
OUTPUT PORT B (J7)
3-8
Switch SW6 or SW8
x_OM/S
LO = DIT CLOCK x
HI = RCKI x
Switch SW6 or SW8
x_DIT
LO = DIT is Slave Only
HI = See Text Box Below
DIT CLOCK A (J4)
or
DIT CLOCK B (J9)
Switch SW6 or SW8
x_OM/S
LO = DIT is Master
HI = DIT is Slave
Audio Output Ports
The DIT4192 transmitters (U7 and U17) have additional configuration
switches, summarized in Table 3−4 and Table 3−5. For the clock divider, the
corresponding control pins need to be set dependent upon the incoming master clock (MCLK) and output sampling rates, fSout. The master clock (MCLK)
rate is set by either reference clock RCKIA or RCKIB, or by the corresponding
DIT CLOCK input at connector J4 or J9 (dependent upon the clock configuration; see Figure 3−3 and Figure 3−4).
Stereo mode operation is the default for most test cases. The Mono mode configuration is utilized primarily to support testing at 176.4kHz and 192kHz output
sampling rates using an Audio Precision System Two Cascade or Cascade
Plus test system with Dual Channel mode support.
The buffered output serial ports OUTPUT PORT A (J2) and OUTPUT PORT
B (J7) support Left-Justified, Right-Justified, I2S, and time division multiplexed
(TDM) formatted audio data with word lengths up to 24 bits and sampling rates
up to 212kHz. The output ports may be operated in either Slave or Master
mode, but must match the output port setup for the SRC4194 device as defined in Table 3−3. The buffered serial output ports provide a convenient method for interfacing to audio devices which support an audio serial data interface,
including external digital audio transmitters, audio data converters, and signal
processing components.
Table 3−4. Transmitter Clock Divider Configuration
If MCLK Rate Equal To:
Set Transmitter Clock Divider Switches To:
128 × fsOUT
x_CLK0 = LO, x_CLK1 = LO
256 × fsOUT
x_CLK0 = HI, x_CLK1 = LO
384 × fsOUT
x_CLK0 = LO, x_CLK1 = HI
512 × fsOUT
x_CLK0 = HI, x_CLK1 = HI
Where fsOUT = the output sampling rate
Where x = A (switch SW6) or B (switch SW8)
Table 3−5. Transmitter Stereo/Mono Mode Configuration
Transmitter Output Mode
Set Mode Switches To:
Stereo
x_MONO = LO, x_MDAT = LO
Mono with Left Channel Data Source
x_MONO = HI, x_MDAT = LO
Mono with Right Channel Data Source
x_MONO = HI, x_MDAT = HI
Where x = A (switch SW6) or B (switch SW8)
3-9
Reference Clock Generation
3.5 Reference Clock Generation
The SRC4194EVM supports a flexible configuration for the SRC4194 reference clock generation. Figure 3−4 illustrates the PLL and clock connections
used for the reference clocks.
Both SRC A and SRC B have their own reference clocks, referred to as RCKIA
and RCKIB, respectively. The reference clocks may be derived by onboard
PLL clock generators (U25 and U28), or by external clock sources applied at
connectors J12 and J13. Table 3−6 summarizes the output rates available
from the onboard PLL circuits.
The reference clocks are also used by the transmitter sections of the EVM, and
are made available at the audio input and output ports for use by external hardware.
Figure 3−4. Reference Clock Generation, Connections, and Configuration
To RCKIA
Switch SW10
A_PLL
LO = Use PLL (U25)
HI = Use Ext Clock (J12)
Switch SW10
B_PLL
LO = Use PLL (U28)
HI = Use Ext Clock (J13)
U25
PLL1705DBQ
U28
PLL1705DBQ
SCKO2
SR
FS1
FS2
SCKO2
FS1
FS2
To RCKIB
SRC B EXT
CLOCK (J13)
Switch SW10
A_FS1
A_FS2
A_SR
Switch SW10
B_CLK
LO = Use PLL or EXT CLK
HI = Use RCKIA
SR
SRC A EXT
CLOCK (J12)
Switch SW10
B_FS1
B_FS2
B_SR
Table 3−6. PLL Configuration for U25 and U28
x_SR (switch SW10)
x_FS2 (switch SW10)
x_FS1 (switch SW10)
PLL Output Rate
LO
LO
LO
12.288 MHz
LO
LO
HI
11.2896 MHz
LO
HI
LO
8.192 MHz
LO
HI
HI
Reserved
HI
LO
LO
24.576 MHz
HI
LO
HI
22.5792 MHz
HI
HI
LO
16.384 MHz
HI
HI
HI
Reserved
Where x = A or B
Where x = A or B
Where x = A or B
3-10
TDM Test Mode
3.6 TDM Test Mode
Jumper J18 is provided to allow a simple onboard connection between
SDOUTA (pin 64) and TDMIB (pin 52). This provides a test mode for evaluating
the TDM output data format. When J18 is shorted, the TDMIB pin at header
J7 should be floating, with no external connection.
3-11
3-12
Chapter 4
! "# ! $
This chapter provides the electrical schematic and physical layout information
for the SRC4194EVM. The bill of materials is included for component and
manufacturer reference.
Topic
Page
4.1
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Schematic, PCB Layout, and Bill of Materials
4-1
Schematic
4.1 Schematic
The electrical schematic for the SRC4194EVM is shown in Figure 4−1 and
Figure 4−2. Descriptions of the components shown on the schematics are
listed in Table 4−1.
4-2
1
2
3
4
5
6
7
8
9
10
SW2
SW1
VIO
RN4
10K
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
11
13
15
17
19
VIO
A1
A2
A3
A4
G
RST
SW3
Y1
Y2
Y3
Y4
R1
10K
VIO
Schematic, PCB Layout, and Bill of Materials
SN74ALVC244PW
9
7
5
3
U3B
C1
0.01uF
D1
RN5
10K
RATIOA
D2
/RDYA
IFMTA0
IFMTA1
IFMTA2
OFMTA0
OFMTA1
OWLA0
OWLA1
BYPA
LGRPA0
LGRPA1
DDNA
DEMA0
DEMA1
MODEA0
MODEA1
MODEA2
RCKIA
VIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RN3
10K
0.1uF
10uF
C23
C8
VIO
SDINA
RATIOA
RDYA
MUTEA
RCKIA
RST
H/S
DGND
VDD33
VDD33
REGEN
VDD18
VDD18
RCKIB
MUTEB
RDYB
RATIOB
10K
R20
HOST PORT
1 2
3 4
5 6
7 8
9 10
VIO
J1
10uF
C9
100
C10
10uF
VDD18
C24
0.1uF
RN14
VDD33
RN1
100
D3
C26
0.1uF
9
7
5
3
2
4
6
8
D4
VIO
18
16
14
12
/RDYB
A1
A2
A3
A4
G
11
13
15
17
19
U2B
SN74ALVC244PW
Y1
Y2
Y3
Y4
U2A
RCKIB
VIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SRC4194IPAG
SN74ALVC244PW
Y1
Y2
Y3
Y4
A1
A2
A3
A4
0.1uF
1
G
C25
U1
BCKIB
LRCKIB
SDINB
IFMTB0
IFMTB1
IFMTB2
OFMTB0
OFMTB1
OWLB0
OWLB1
BYPB
LGRPB0
LGRPB1
DDNB
DEMB0
DEMB1 (CDOUT)
MODEB0 (CS)
MODEB1 (CCLK)
MODEB2 (CDIN)
RATIOB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
RN2
10K
VIO
64
63
62
61
60
59
58
SDOUTA
BCKOA
LRCKOA
TDMIA
BCKIA
LRCKIA
SDINA
56
VIO
57
DGND
55
54
53
52
51
50
49
SDINB
LRCKIB
BCKIB
TDMIB
LRCKOB
BCKOB
SDOUTB
20
VCC
GND
10
RN6
10K
VIO
C27
18
16
14
12
A1
A2
A3
A4
G
U3A
2
4
6
8
1
0.1uF
2
C28
1
2
3
4
5
6
7
8
VIO
SW6
4
SW8
U4
RN8
10K
1
2
3
4
5
6
7
8
SN74ALVC244PW
VIO
SN74LVC1G04DBV
Y1
Y2
Y3
Y4
0.1uF
20
VCC
GND
10
16
15
14
13
12
11
10
9
RN11
10K
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
VIO
VIO
RN9
10K
SW5
SW4
RN7
10K
16
15
14
13
12
11
10
9
RN10
10K
VIO
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
A_IM/S
A_/DIR
J18
2
B_IM/S
B_/DIR
TDM
1
11
13
15
17
19
2
4
6
8
1
11
13
15
17
19
2
4
6
8
1
Y1
Y2
Y3
Y4
18
16
14
12
0.1uF
U6A
C29
9
7
5
3
Y1
Y2
Y3
Y4
0.1uF
U16A
C30
18
16
14
12
Y1
Y2
Y3
Y4
9
7
5
3
U16B
OUTPUT PORT B
J7
SN74ALVC244PW
A1
A2
A3
A4
G
SN74ALVC244PW
A1
A2
A3
A4
G
VIO
RN15
100
SN74ALVC244PW
Y1
Y2
Y3
Y4
U6B
SN74ALVC244PW
A1
A2
A3
A4
G
A1
A2
A3
A4
G
VIO
20
VCC
GND
10
20
VCC
GND
10
2
3
4
5
6
7
8
9
10
1
1
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
GND
OE
B1
B2
B3
B4
B5
B6
B7
B8
VCC
19
18
17
16
15
14
13
12
11
20
RN18
100
0.1uF
2
4
2
5
9
12
1
4
10
13
U20
4
0.1uF
2
5
9
12
1
4
10
13
U10
C36
SN74LVC1G04DBV
C39 VIO
VIO
J2
OUTPUT PORT A
2
0.1uF
19
GND
1Y
2Y
3Y
4Y
VCC
C37VIO
GND
1Y
2Y
3Y
4Y
VCC
4
U18
7
3
6
8
11
14
VIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U7
CSS
COPY/C
L
CLK1
CLK0
MCLK
VIO
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
MODE
U
V
BLS
BLSM
EMPH
AUDIO
MONO
MDAT
VDD
TX+
TX−
DGND
RST
0.1uF
C35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.1uF
C40
MODE
U
V
BLS
BLSM
EMPH
AUDIO
MONO
MDAT
VDD
TX+
TX−
DGND
RST
VIO
R3
10K
R9
75
C43
C41
R6
150
AES OUT A
J3
R4
120
C42
0.1uF
10uF
0.1uF
C13
+5V
C3
120
R7
150
10uF
C44
AES OUT B
0.1uF
R5
J8
0.1uF
C14
+5V
SW9 0.01uF
VIO
C2
0.01uF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
J9
B_DITRST
DIT CLOCK B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
J4
DIT CLOCK A
DIT4192IPW
CSS
COPY/C
L
CLK1
CLK0
MCLK
VIO
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
U17
R8
75
A_DITRST
SW7
DIT4192IPW
VIO
R2
4
U8
10K
SN74LVC1G08DBV
VIO
100
10uF
SN74LVC1G08DBV
SN74ALVC125PW
1A
2A
3A
4A
1OE
2OE
3OE
4OE
U19
1
2
100
C38
0.1uF
10uF
RN19
0.1uF
C12
VIO
VIO
7
3
6
8
11
14
1
2
VIO
C32
0.1uF
C11
RN16
C33
0.1uF
0.1uF
C31
SN74ALVC125PW
1A
2A
3A
4A
1OE
2OE
3OE
4OE
U9
VIO
20
18
17
16
15
14
13
12
11
SN74ALVC245PW
OE
VCC
DIR
U5
SN74LVC1G04DBV
VIO
C34
2
3
4
5
6
7
8
9
10
SN74ALVC245PW
A1
A2
A3
A4
A5
A6
A7
A8
GND
DIR
U15
1 2
3 4
5 6
7 8
9 10
1 2
3 4
5 6
7 8
9 10
5
3
5
3
5
3
LRCKIA
5
3
5
3
BCKIA
Schematic
Figure 4−1. SRC4194EVM Schematic Diagram, Page 1 of 2
4-3
SN74LVC1G04DBV
0.1uF
2
C48
VIO
R12
75
U27
4
VIO
0.01uF
R11 0.01uF
75
C7
C6
J12
SRC A EXT CLOCK
J11
AES IN B
+5V
0.01uF
R10 0.01uF
75
C5
C4
+5V
2
5
9
12
1
4
10
13
C16
10uF
C15
10uF
GND
1Y
2Y
3Y
4Y
VCC
14
C17
10uF
R13
75
0.1uF
REG +3.3V
7
3
6
8
11
C47
FILT
MCK
M2
M3
SEL
CBL
AGND
VERF
CE/F2
SDATA
ERF
M1
M0
VCC
FILT
MCK
M2
M3
SEL
CBL
AGND
VERF
CE/F2
SDATA
ERF
M1
M0
VCC
VIO
CS8414−CS
RXP
RXN
FSYNC
SCK
CS12/FCK
U
DGND
C
CD/F1
CC/F0
CB/E2
CA/E1
C0/E0
VDD
U24
CS8414−CS
RXP
RXN
FSYNC
SCK
CS12/FCK
U
DGND
C
CD/F1
CC/F0
CB/E2
CA/E1
C0/E0
VDD
SN74ALVC125PW
1A
2A
3A
4A
1OE
2OE
3OE
4OE
U26
9
10
11
12
13
14
C46
0.1uF 8
1
2
3
4
5
6
7
9
10
11
12
13
14
C45
0.1uF 8
1
2
3
4
5
6
7
U14
C54
0.1uF
20
19
18
17
16
15
21
28
27
26
25
24
23
22
20
19
18
17
16
15
21
28
27
26
25
24
23
22
R19
475
0.068uF
C72
C18
10uF
C73
C19
10uF
VDD3
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
VDD2
CSEL
XT2
27.000 MHz
X1
PLL1705DBQ
VDD1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
VCC
AGND
XT1
0.1uF
C52
+5V
+5V
U25
C74
27pF
1
2
3
4
5
6
7
8
9
10
REG +3.3V
0.068uF
+5V
475
LOCK B
R18
C50
0.1uF
D6
475
R17
+5V
475
LOCK A
R16
C49
0.1uF
D5
20
19
18
17
16
15
14
13
12
11
11
13
15
17
19
11
13
15
17
19
Y1
Y2
Y3
Y4
U13B
Y1
Y2
Y3
Y4
U23B
C53
0.1uF
10uF
0.1uF
C20
REG +3.3V
C51
C75
27pF
J10
RN20
100
9
7
5
3
INPUT PORT B
SN74LVC244APW
A1
A2
A3
A4
G
B_/DIR
J5
RN17
100
9
7
5
3
INPUT PORT A
SN74LVC244APW
A1
A2
A3
A4
G
1 2
3 4
5 6
7 8
9 10
1 2
3 4
5 6
7 8
9 10
11
13
15
17
19
11
13
15
17
19
1
2
3
4
5
6
7
8
9
10
Y1
Y2
Y3
Y4
9
7
5
3
Y1
Y2
Y3
Y4
U22B
9
7
5
3
A1
A2
A3
A4
G
0.1uF
SW10
VIO
VIO
20
19
18
17
16
15
14
13
12
11
18
16
14
12
18
16
14
12
SN74ALVC244PW
Y1
Y2
Y3
Y4
U22A
SDINB
0.1uF
C57
VIO
SN74ALVC244PW
Y1
Y2
Y3
Y4
U12A
SDINA
REG +3.3V
A1
A2
A3
A4
G
0.1uF
RN12
10K
2
4
6
8
1
C58
SN74ALVC244PW
A1
A2
A3
A4
G
2
4
6
8
1
C56
SN74ALVC244PW
A1
A2
A3
A4
G
U12B
20
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
VCC
A1
A2
A3
A4
A5
A6
A7
A8
GND
DIR
OE
B1
B2
B3
B4
B5
B6
B7
B8
VCC
U21
A1
A2
A3
A4
A5
A6
A7
A8
GND
DIR
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
U11
1
0.1uF
2
C59
U30
4
+5V
RCKIA
2
0.1uF
3
2
5
9
12
1
4
10
13
GND
1Y
2Y
3Y
4Y
VCC
RCKIB
7
J14
POWER SUPPLIES
C62
0.1uF
VIO
R15
75
C22
10uF
C69
0.1uF
C85
100uF
EXT VDD33
REG +3.3V
2
C79
10uF
REG +3.3V
3
6
8
11
14
0.1uF
C65
VOUT
C82
100uF
EXT VIO
SN74ALVC125PW
1A
2A
3A
4A
1OE
2OE
3OE
4OE
U29
VIN
U32
REG1117−3.3
SN74LVC1G04DBV
U31
4
C78
10uF
C60 VIO
R14
75
J13
SRC B EXT CLOCK
LRCKIB
BCKIB
B_IM/S
LRCKIA
BCKIA
A_IM/S
VIO
SN74LVC1G04DBV
RN13
10K
SN74ALVC245PW
19
18
17
16
15
14
13
12
11
20
SN74ALVC245PW
19
18
17
16
15
14
13
12
11
6
A1
A2
A3
A4
G
3
C80
10uF
C63
0.1uF
0.1uF
C67
27.000 MHz
PLL1705DBQ
X2
VDD3
SCKO0
SCKO1
DGND3
DGND2
MCKO2
MCKO1
VDD2
CSEL
XT2
VIN
20
19
18
17
16
15
14
13
12
11
+5V
C77
27pF
C66
0.1uF
C21
C68
0.1uF
10uF
2
4
6
8
1
A1
A2
A3
A4
G
VIO
Y1
Y2
Y3
Y4
C71
0.1uF
REG +1.8V EXT VDD18
J17
1
3
5
REG +3.3V EXT VDD33
J16
1
3
5
J15
1
3
5
VIO
2
4
6
VDD18
2
4
6
VDD33
2
4
6
SN74LVC244APW
18
16
14
12
U23A
0.1uF
C70
REG +1.8V REG +3.3V EXT VIO
REG +1.8V
2
C81
10uF
REG +3.3V
VOUT
C83
100uF
SN74LVC244APW
18
16
14
12
U33
REG1117A−1.8
VDD1
SCKO2
SCKO3
DGND1
FS1
FS2
SR
VCC
AGND
XT1
U28
C76
27pF
1
2
3
4
5
6
7
8
9
10
Y1
Y2
Y3
Y4
U13A
0.1uF
C61
EXT VDD18
C84
100uF
REG +3.3V
+5V
C64
0.1uF
2
4
6
8
1
VIO
20
VCC
GND
10
20
3
VIO
2
C55
5
GND
10
20
VCC
GND
10
1
J6
AES IN A
5
3
5
3
4
0.1uF
5
GND
1
GND
1
20
VCC
GND
10
4-4
3
A_/DIR
Schematic
Figure 4−2. SRC4194EVM Schematic Diagram, Page 2 of 2
PCB Layout
4.2 PCB Layout
The SRC4194EVM is a four-layer printed circuit board (PCB) with the following
layer structure:
- Layer 1: Top (Component Side)
- Layer 2: Ground Plane
- Layer 3: Power
- Layer 4: Bottom (Solder Side)
Figure 4−3 through Figure 4−8 show the top side silk screen, along with the
top, ground plane, power, and bottom layers of the printed circuit assembly.
Figure 4−3. Top Side Silk Screen
Schematic, PCB Layout, and Bill of Materials
4-5
PCB Layout
Figure 4−4. Bottom Side Silk Screen
4-6
PCB Layout
Figure 4−5. Top Layer (Component Side)
Schematic, PCB Layout, and Bill of Materials
4-7
PCB Layout
Figure 4−6. Ground Plane Layer
4-8
PCB Layout
Figure 4−7. Power Layer
Schematic, PCB Layout, and Bill of Materials
4-9
PCB Layout
Figure 4−8. Bottom layer (Solder Side)
4-10
0.1µF
4
Schematic, PCB Layout, and Bill of Materials
J15−J17
J18
D1−D6
R8−R15
11
12
13
14
R4, R5
J14
10
120Ω
J4, J9, J12, J13
9
15
J3, J6, J8, J11
8
75Ω
J1, J2, J5, J7, J10
C82−C85
C8−C22, C78−C81
C23−C71
C72, C73
C1−C7
C74−C77
REFERENCE
DESIGNATOR
7
100µF
0.068µF
3
6
0.01µF
2
10µF
27pF
1
5
VALUE
ITEM
2
8
6
1
3
1
4
4
5
4
19
49
2
7
4
QTY PER
BOARD
Table 4−1. SRC4194EVM Bill of Materials
Panasonic or equivalent
Panasonic or equivalent
Lumex
Samtec
Samtec
Weidmuller
Kings Electronics
CUI Stack
Samtec
Kemet
Kemet
Kemet
Kemet
Kemet
Kemet
MFG
ERJ−6ENF1200V
ERJ−6ENF75R0V
SML−LX1206GC−TR
TSW−102−07−G−S
TSW−103−07−G−D
9967720000
KC−79−274−M06
RCJ−041
TSW−105−07−G−D
T491D107K010AS
T491A106K010AS
C0603C104K4RACTU
C0603C683J4RACTU
C0603C103J5RACTU
C0603C270J5GACTU
MANUFACTURER
PART NUMBER
Resistor, 120Ω, ±1%, 1/10W, Thick Film Chip,
Size = 0805
Resistor, 75Ω, ±1%, 1/10W, Thick Film Chip,
Size = 0805
Green LED, SMT, Size = 1206
Terminal Strip, 2-pin (2x1)
Terminal Strip, 6-pin (3x2)
Terminal Block, 3.5mm PCB, 6 poles
BNC Connector, Female, PC Mount
RCA Jack, PC Mount, Black
Terminal Strip, 10-pin (5x2)
Chip Capacitor, Tantalum, 100µF ±10%, 10WV,
Size = D
Chip Capacitor, Tantalum, 10µF ±10%, 10WV,
Size = A
Chip Capacitor, X7R Ceramic, 0.1µF ±10%,
16WV, Size = 0603
Chip Capacitor, X7R Ceramic, 0.068µF ±5%,
16WV, Size = 0603
Chip Capacitor, X7R Ceramic, 0.01µF, ±5%,
50WV, Size = 0603
Chip Capacitor, NPO/C0G Ceramic, 27pF, ±5%,
50WV, Size = 0603
DESCRIPTION
The bill of materials, listing the components used in the assembly of the SRC4194EVM, is shown in Table 4−1.
4.3 Bill of Materials
Bill of Materials
4-11
4-12
5
1
6
6
SW1, SW2, SW4,
SW5
SW6, SW8
SW3, SW7, SW9
U1
U2, U3, U6, U12,
U16, U22
U4, U10, U20,
U27, U30, U31
U5, U11, U15, U21
23
24
25
26
27
28
29
4
3
2
5
RN3, RN5, RN7,
RN9, RN13
10kΩ
22
7
RN2, RN4, RN6,
RN8, RN10, RN11,
RN12
10kΩ
21
4
100Ω
20
RN16, RN17,
RN19, RN20
100Ω
19
4
4
10kΩ
18
R16−R19
2
RN1, RN14, RN15,
RN18
475Ω
17
R6, R7
QTY PER
BOARD
3
150Ω
16
REFERENCE
DESIGNATOR
R1−R3
VALUE
ITEM
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Omron
ITT C&K Switch
ITT C&K Switch
CTS
CTS
CTS
CTS
Panasonic or equivalent
Panasonic or equivalent
Panasonic or equivalent
MFG
Table 4−1. SRC4194EVM Bill of Materials (continued)
SN74ALVC245PW
SN74LVC1G04DBV
SN74ALVC244PW
SRC4194IPAG
B3S−1000
TDA08H0SK1
TDA10H0SK1
741X083103JCT−ND
741X163103JCT−ND
741X083101JCT−ND
741X163101JCT−ND
ERJ−6ENF1002V
ERJ−6ENF4750V
ERJ−6ENF1500V
MANUFACTURER
PART NUMBER
Octal Bus Transceiver with Tri−State Outputs
Single Inverter
Octal Buffer/Driver with Tri-State Outputs
4-Channel Asynchronous, Sample Rate
Converter
Momentary Tact Switch, SMT w/o Ground
Terminal
DIP Switch, 8-Position, Half Pitch
Surface-Mount, Tape-Sealed
DIP Switch, 10-Position, Half Pitch
Surface-Mount, Tape-Sealed
Thick Film Chip Resistor Array, 10kΩ,
8-terminal, 4 resistors
Thick Film Chip Resistor Array, 10kΩ,
16-terminal, 8 resistors
Thick Film Chip Resistor Array, 100Ω,
8-terminal, 4 resistors
Thick Film Chip Resistor Array, 100Ω,
16-terminal, 8 resistors
Resistor, 10kΩ, ±1%, 1/10W, Thick Film Chip,
Size = 0805
Resistor, 475Ω, ±1%, 1/10W, Thick Film Chip,
Size = 0805
Resistor, 150Ω, ±1%, 1/10W, Thick Film Chip,
Size = 0805
DESCRIPTION
Bill of Materials
U25, U28
U32
U33
X1, X2
35
36
37
38
2
1
1
2
2
4
U14, U24
34
2
40
U13, U23
33
4
4
U9, U19, U26, U29
32
2
2
QTY PER
BOARD
39
U8, U18
31
REFERENCE
DESIGNATOR
U7, U17
VALUE
30
ITEM
Samtec
3M Bumpon
Citizen
Texas Instruments
Texas Instruments
Texas Instruments
Cirrus Logic
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
MFG
Table 4−1. SRC4194EVM Bill of Materials (continued)
SNT−100−BK−G−H
SJ−5003
HCM49−27.000MABJT
REG1117A−1.8
REG1117−3.3
PLL1705DBQ
CS8414−CS
SN74LVC244APW
SN74ALVC125PW
SN74LVC1G08DBV
DIT4192IPW
MANUFACTURER
PART NUMBER
Shorting Blocks
Rubber Feet, Adhesive Backed
Quartz Crystal, SMT, 27.000MHz ±50ppm
+1.8V Linear Voltage Regulator
+3.3V Linear Voltage Regulator
Dual PLL Multiclock Generator
96kHz Digital Audio Interface Receiver
Octal Buffer/Driver with Tri−State Outputs
Quad Buffer with Tri−State Outputs
Single AND Gate
192kHz Digital Audio Transmitter
DESCRIPTION
Bill of Materials
Schematic, PCB Layout, and Bill of Materials
4-13
