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TAD5142IRGER

TAD5142IRGER

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VQFN24_4X4MM_EP

  • 描述:

    IrDA编码器/解码器 VQFN24_4X4MM_EP

  • 数据手册
  • 价格&库存
TAD5142IRGER 数据手册
TAD5142 SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 TAD5142 Hardware-control stereo audio DAC with 110dB dynamic range, and headphone/line driver 1 Features 3 Description • The TAD5142 is a 2VRMS 110dB stereo audio DAC that can be configured for either line output or headphone load and supports both single-ended and differential output options. The device integrates a phase-locked loop (PLL) and supports sample rates up to 192kHz. TAD5142 can drive upto 62.5 mW into a 16Ω headphone load. The TAD5142 supports time-division multiplexing (TDM), left-justified (LJ), or I2S audio formats in controller and target modes, and is pin or hardware controlled. These integrated highperformance features, pin control along with a single supply operation, make TAD5142 an excellent choice for space-constrained audio applications. – Stereo audio DAC performance: • DAC to differential line-out dynamic range: 110dB • DAC to pseudo-differential headphone-out dynamic range: 107dB • DAC to differential line-out THD+N: –100 dB • Output voltage: – Differential Line-out/Receiver, 2VRMS fullscale – Pseudo-differential Headphone, 1VRMS full-scale – Single-ended Line-out, 1VRMS full-scale • DAC sample rates (fs) = 8kHz to 192kHz – Key Features • Pin or Hardware Control • Audio Serial Interface – Format: TDM, LJ or I2S – Bus Controller and Target Modes – Daisy chain in TDM Mode – Word Length: Selectable 24 or 32 Bits • Pin-selectable digital interpolation filter options: – Linear-phase – Low-latency • Auto clock detection • Interrupt output on clock error • Single supply operation AVDD: 1.8V or 3.3V • I/O Supply Operation: 1.8V or 3.3V • Temperature grade 1: –40°C ≤ TA ≤ +125°C 2 Applications • • • • AV Receiver IP Network Camera Soundbar Video Conference System Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE (NOM)(2) TAD5142 VQFN (24) 4mm x 4mm with 0.5mm pitch (1) (2) For all available packages, see the orderable addendum at the end of the data sheet. The package size (length × width) is a nominal value and includes pins, where applicable. MD0 Pin or Hardware Control Interface MD1 MD2 MD3 MD4 MD5 OUT1P MD6 BCLK OUT1M Audio Serial Interface (TDM, I2S, LJ) Digital Interpolation Filters 2-Channel DAC + Driver Amp OUT2P OUT2M FSYNC DIN Regulators and Voltage Reference VREF DREG VSS PLL and Clock Generation VSSA AVDD GPO IOVDD Simplified Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 5 5.1 Absolute Maximum Ratings........................................ 5 5.2 ESD Ratings............................................................... 5 5.3 Recommended Operating Conditions.........................5 5.4 Thermal Information....................................................6 5.5 Electrical Characteristics.............................................6 5.6 Timing Requirements: TDM, I2S or LJ Interface......... 9 5.7 Switching Characteristics: TDM, I2S or LJ Interface........................................................................ 9 5.8 Timing Diagrams ...................................................... 10 5.9 Typical Characteristics.............................................. 11 6 Detailed Description......................................................14 6.1 Overview................................................................... 14 6.2 Functional Block Diagram......................................... 14 2 6.3 Feature Description...................................................14 6.4 Device Functional Modes..........................................32 7 Application and Implementation.................................. 33 7.1 Application Information............................................. 33 7.2 Typical Application.................................................... 33 7.3 Power Supply Recommendations.............................35 7.4 Layout....................................................................... 35 8 Device and Documentation Support............................37 8.1 Documentation Support............................................ 37 8.2 Receiving Notification of Documentation Updates....37 8.3 Support Resources................................................... 37 8.4 Trademarks............................................................... 37 8.5 Electrostatic Discharge Caution................................37 8.6 Glossary....................................................................37 9 Revision History............................................................ 37 10 Mechanical, Packaging, and Orderable Information.................................................................... 37 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAD5142 TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 VREF AVDD OUT2M OUT2P OUT1P OUT1M 23 22 21 20 19 A1 24 VSS 4 Pin Configuration and Functions A4 VSS DREG 1 18 VSSA BCLK 2 17 VSSA FSYNC 3 16 VSSA Thermal Pad MD6 4 15 VSSA DIN 5 14 VSSA IOVDD 6 13 MD0 8 9 10 11 12 MD2 MD3 MD4 GPO MD5 A3 VSS 7 A2 MD1 VSS Notes:Not to Scale Figure 4-1. 24-Pin QFN Package with Exposed Thermal Pad and Corner Pins, Top View Table 4-1. Pin Functions PIN NAME VSS NO. TYPE DESCRIPTION A1 Ground Ground pin. Short directly to board ground plane. DREG 1 Digital Supply Digital on-chip regulator output voltage for digital supply (1.55V, nominal) BCLK 2 Digital I/O Audio serial data interface bus bit clock FSYNC 3 Digital I/O Audio serial data interface bus frame synchronization signal MD6 4 Digital I/O TDM mode: Daisy chain output I2S/LJ mode: Mono/Stereo DAC Channels selection DIN 5 Digital Input Audio serial data interface bus input IOVDD 6 Digital Supply Digital I/O power supply (1.8V or 3.3V, nominal) VSS A2 Ground Ground pin. Short directly to board ground plane. MD1 7 Digital Input Controller mode: Frame rate and BCLK frequency selection MD2 8 Digital Input Controller mode: Frame rate and BCLK frequency selection MD3 9 Digital Input Controller mode: Controller clock input MD4 10 Digital Input DAC output configuration selection GPO 11 Digital Output Interrupt output (latched) Target mode: AVDD supply, word length, and interpolation filter type selection Target mode: AVDD supply, word length, and interpolation filter type selection Target mode: Short directly to board ground plane. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAD5142 3 TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 Table 4-1. Pin Functions (continued) PIN NAME 4 NO. TYPE DESCRIPTION MD5 12 Digital Input DAC output configuration selection VSS A3 Ground Ground pin. Short directly to board ground plane. MD0 13 Analog Input Multi-level analog input for controller/target mode and I2S/TDM/LJ mode selection VSSA 14 Ground Short directly to board ground plane VSSA 15 Ground Short directly to board ground plane VSSA 16 Ground Short directly to board ground plane VSSA 17 Ground Short directly to board ground plane VSSA 18 Ground Short directly to board ground plane VSS A4 Ground Ground pin. Short directly to board ground plane. OUT1M 19 Analog Output Analog output 1M pin OUT1P 20 Analog Output Analog output 1P pin OUT2P 21 Analog Output Analog output 2P pin OUT2M 22 Analog Output Analog output 2M pin AVDD 23 Analog Supply Analog power supply (1.8V or 3.3V, nominal) VREF 24 Analog Analog reference voltage filter output Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAD5142 TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX Supply voltage AVDD to VSS (thermal pad) –0.3 3.9 V Supply voltage IOVDD to VSS (thermal pad) –0.3 3.9 V Ground voltage differences VSSA to VSS (thermal pad) –0.3 0.3 V Digital input voltage Digital input pins voltage to VSS (thermal pad) –0.3 IOVDD + 0.3 V Functional ambient, TA –55 125 Operating ambient, TA –40 125 Junction, TJ –40 150 Storage, Tstg –65 150 Temperature (1) UNIT °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 5.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) (2) UNIT V JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. 5.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Analog supply voltage to VSS (thermal pad) - AVDD 3.3V operation 3.0 3.3 3.6 Analog supply voltage to VSS (thermal pad) - AVDD 1.8V operation 1.65 1.8 1.95 IO supply voltage to VSS (thermal pad) - IOVDD 3.3V operation 3.0 3.3 3.6 IO supply voltage to VSS (thermal pad) - IOVDD 1.8V operation 1.65 1.8 1.95 UNIT POWER AVDD(1) IOVDD V V INPUTS IO Digital input pins (MD1 to MD6) voltage to VSS (thermal pad) 0 IOVDD V MD0 MD0 pin w.r.t VSS (thermal pad) 0 AVDD V –40 125 °C TEMPERATURE TA Operating ambient temperature Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAD5142 5 TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT OTHERS CCLK CL (1) (2) MD3 controller mode clock frequency (CCLK) - IOVDD 3.3V operation 36.864(2) MD3 controller mode clock frequency (CCLK) - IOVDD 1.8V operation 24.576(2) Digital output load capacitance 20 50 MHz pF VSSA and VSS (thermal pad); all ground pins must be tied together and must not differ in voltage by more than 0.2V. CCLK input rise time (VIL to VIH) and fall time (VIH to VIL) must be less than 5ns. For better audio noise performance, CCLK input must be used with low jitter. 5.4 Thermal Information TAD5142 THERMAL METRIC(1) RGE (VQFN) UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 38.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.3 °C/W RθJB Junction-to-board thermal resistance 15.9 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 15.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 13.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 5.5 Electrical Characteristics At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, and linear phase interpolation filter, with 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω receiver differential load as applicable; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DAC Performance for Line Output/Head Phone Playback Full Scale Output Voltage SNR 6 Differential output between OUTxP and OUTxM, AVDD = 3.3V 2 Differential output between OUTxP and OUTxM, AVDD = 1.8V 1 Single-ended output, AVDD = 3.3V 1 Single-ended output, AVDD = 1.8V 0.5 Pseudo-differential output between OUTxP and OUT1M with external common-mode sense, AVDD = 3.3V 1 Pseudo-differential output between OUTxP and OUT1M with external common-mode sense, AVDD = 1.8V 0.5 Differential output, 0dBFS Signal, AVDD = 3.3V 110 Single-ended output, 0dBFS Signal, AVDD = 3.3V 107 Pseudo-differential output, 0dBFS Signal, AVDD Signal-to-noise ratio, A- = 3.3V weighted(1) (2) Differential output, 0dBFS Signal, AVDD = 1.8V 107 109 Single-ended output, 0dBFS Signal, AVDD = 1.8V 104 Pseudo-differential output, 0dBFS Signal, AVDD = 1.8V 103 Submit Document Feedback VRMS dB Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAD5142 TAD5142 www.ti.com SLASF32A – DECEMBER 2023 – REVISED OCTOBER 2024 At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, and linear phase interpolation filter, with 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω receiver differential load as applicable; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted PARAMETER DR Dynamic range, Aweighted(2) TEST CONDITIONS MIN NOM Differential output, –60dBFS Signal, AVDD = 3.3V 110 Single-ended output, –60dBFS Signal, AVDD = 3.3V 107 Pseudo-differential output, –60dBFS Signal, AVDD = 3.3V 107 Differential output, –60dBFS Signal, AVDD = 1.8V 109 Single-ended output, –60dBFS Signal, AVDD = 1.8V 104 Pseudo-differential output, –60dBFS Signal, AVDD = 1.8V 103 THD+N Total harmonic distortion(2) Differential output, –1dBFS Signal, AVDD = 3.3V THD+N Total harmonic distortion(2) Single-ended output, –1dBFS Signal, AVDD = 3.3V MAX UNIT dB –100 dB –96 dB Headphone Load Range(3) 8 16 300 Ω Headphone/Line-out Cap Load 0 100 550 pF Line-out Load Range 600 Ω DAC Channel OTHER PARAMETERS Output Offset 0 Input, Differential Line-output 0.5 mV Output Common Mode Common Mode Level for OUTxP and OUTxM, AVDD = 1.8V 0.9 V Output Common Mode Common Mode Level for OUTxP and OUTxM, AVDD = 3.3V 1.65 V Common Mode Error DC Error in Common Mode Voltage ±10 mV 20 kHz Output Signal Bandwidth Input data word length Pin-selectable 24 Interchannel isolation 32 Bits –120 dB Gain Error 0.1 dB Interchannel gain mismatch 0.1 dB 0.01 Degrees 110 dB 62.5 mW Interchannel phase mismatch 1kHz sinusoidal signal PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input, 0dB channel gain Pout Output Power Delivery Receiver/Headphone RL=16Ω, THD+N
TAD5142IRGER 价格&库存

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