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TAS2505-Q1
SLASEI9A – JULY 2017 – REVISED DECEMBER 2017
TAS2505-Q1 2.6-W Digital/Analog Input Automotive Class-D Speaker Amplifier With Audio
Processing
1 Features
3 Description
•
The TAS2505-Q1 is a mono Class-D speaker amp
that supports both Digital and Analog inputs. The
device is ideal for automotive instrument cluster,
emergency call (eCall), and telematics applications.
Direct I2S input removes the need for an external
DAC in the audio signal path, and the integrated LDO
enables single supply operation. In addition to
integration, the device features programmable audio
processing. The onboard DSP supports bass boost,
treble, and EQ (up to 6 biquads). An on-chip PLL
provides the high-speed clock needed by the DSP.
The volume level is register controlled.
2 Applications
•
•
•
Simplified Block Diagram
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
DAC Signal
Proc.
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
Mono 6
' DAC
Dig
Vol
6 dB to +24 dB
(6 dB steps)
SPKP
6
SPKM
POR
LDO
LDO_SEL
SPKVDD
AVDD
Primary I2S
Interface
PLL
Interrupt
Control
Pin Muxing / Clock Routing
Supplies
Secondary I2S
Interface
DVDD
IOVDD
SPKVSS
AVSS
MCLK
DVSS
DIN
RST
SPI/I2C
Control Block
BCLK
SPI_SEL
WCLK
•
•
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
GPIO/DOUT
•
PACKAGE
VQFN (24)
Data
Interface
•
•
PART NUMBER
TAS2505-Q1
MISO
•
•
Device Information(1)
SCLK
•
•
•
SCL/SSZ
•
AEC-Q100 Qualified With the Following Results
for Automotive Applications:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Mono Class-D BTL Speaker Amplifier
– 2.6 W at 10% THD_N (4Ω, 5.5 V)
– 1.7 W at 10% THD+N (8 Ω, 5.5 V)
Supports both Digital and Analog Input
Single Supply 2.7 V to 5.5 V
Load Diagnostic Functions:
– Output-to-GND Short
– Terminal-to-Terminal Short
– Output-to-Power Short
– Over Temperature
Supports 9-kHz to 96-kHz Sample Rates
Two Single-Ended Inputs with Output Mixing and
Level Control
Embedded Power-On-Reset
Programmable Digital Audio Processing:
– Bass Boost
– Treble
– EQ (up to 6 Biquads)
I2S, Left-Justified, Right-Justified, DSP, and TDM
Audio Interfaces
I2C and SPI Control With Auto-Increment
24-Pin, VQFN Wettable Flank (Automotive Grade)
Package
SDA/MOSI
1
Copyright © 2016, Texas Instruments Incorporated
Instrument Cluster
Automotive Emergency Call (eCall)
Telematics
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS2505-Q1
SLASEI9A – JULY 2017 – REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics.......................................... 5
I2S/LJF/RJF Timing in Master Mode......................... 8
I2S/LJF/RJF Timing in Slave Mode........................... 8
DSP Timing in Master Mode ..................................... 8
DSP Timing in Slave Mode ....................................... 8
I2C Interface Timing ................................................ 9
SPI Interface Timing ............................................... 9
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes .......................................
Register Map...........................................................
15
15
15
17
21
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ............................................... 24
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2017) to Revision A
Page
•
Added AEC classification levels ............................................................................................................................................ 1
•
Added 'Wettable Flank (Automotive Grade)' description to package feature......................................................................... 1
2
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SLASEI9A – JULY 2017 – REVISED DECEMBER 2017
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
Top View
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
SPI_SEL
I
Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
2
RST
I
Reset for logic, state machines, and digital filters; asserted LOW.
3
AINL
I
Analog single-ended line left input
4
AINR
I
Analog single-ended line right input
5
NC
O
No Connect (Leave unconnected)
6
AVSS
GND
Analog Ground, 0 V
7
AVDD
PWR
Analog Core Supply Voltage, 1.5 V to 1.95 V, tied internally to the LDO output
8
LDO_SEL
I
Select Pin for LDO; ties to either SPKVDD or SPKVSS
9
SPKM
O
Class-D speaker driver inverting output
10
SPKVDD
PWR
Class-D speaker driver power supply
11
SPKVSS
PWR
Class-D speaker driver power supply ground supply
12
SPKP
O
Class-D speaker driver noninverting output
13
DIN
I
Audio Serial Data Bus Input Data
14
WCLK
I/O
Audio Serial Data Bus Word Clock
15
BCLK
I/O
Audio Serial Data Bus Bit Clock
16
MCLK
I
Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
17
MISO
O
SPI Serial Data Output
18
GPIO/DOUT
I/O/Z
19
SCL/SSZ
I
Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
20
SDA/MOSI
I
Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
1
(1)
GPIO / Audio Serial Bus Output
I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
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Pin Functions (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
21
SCLK
I
22
IOVDD
PWR
Serial clock for SPI interface
I/O Power Supply, 1.1 V to 3.6 V
23
DVDD
PWR
Digital Power Supply, 1.65 V to 1.95 V
24
DVSS
GND
Digital Ground, 0 V
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
AVDD to AVSS
–0.3
2.2
V
DVDD to DVSS
–0.3
2.2
V
SPKVDD to SPKVSS
–0.3
6
V
IOVDD to IOVSS
–0.3
3.9
V
Digital input voltage
IOVSS – 0.3
IOVDD + 0.3
V
Analog input voltage
AVSS – 0.3
AVDD + 0.3
V
–40
105
°C
125
°C
Operating temperature
Junction temperature, TJ Max
Power dissipation for VQFN package (with thermal pad soldered to board)
(TJ Max – TA) / θJA
Storage temperature, Tstg
(1)
–55
W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
AVDD (1)
Referenced to AVSS (2)
DVDD
SPKVDD
(1)
Power-supply voltage
IOVDD
(3)
Analog audio full-scale input
voltage
AVDD = 1.8 V, single-ended
Master clock frequency
IOVDD = DVDD = 1.8 V
TA
Operating free-air temperature
(3)
4
MAX
1.8
1.95
1.65
1.8
1.95
1.1
Load applied across class-D output pins (BTL)
SCL clock frequency
NOM
1.5
2.7
Speaker impedance
SCL
(1)
(2)
Referenced to SPKVSS
(2)
Referenced to IOVSS (2)
VI
MCLK
Referenced to DVSS (2)
MIN
5.5
1.8
V
3.6
Ω
4
0.5
–40
UNIT
VRMS
50
MHz
400
kHz
105
°C
To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
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6.4 Thermal Information
TAS2505-Q1
THERMAL METRIC (1)
RGE (QFN)
UNIT
24 PINS
θJA
Junction-to-ambient thermal resistance
32.2
°C/W
θJCtop
θJB
Junction-to-case (top) thermal resistance
30
°C/W
Junction-to-board thermal resistance
9.2
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
9.2
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5
Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
8.48
MHz
DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS
See TAS2505 Application Reference Guide (SLAU472) for DAC interpolation filter characteristics.
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL)
Idle channel noise
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted (1) (2)
37
μVms
Output voltage
BTL measurement, class-D gain = 6 dB, –3-dBFS
input
1.4
Vrms
THD+N
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
–73.9
dB
PSRR
Power-supply rejection ratio
BTL measurement, ripple on SPKVDD = 200 mVPP
at 1 kHz
55
dB
Mute attenuation
Mute
103
dB
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1.1
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.4
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
1.1
ICN
PO
Maximum output power
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB
(1)
(2)
W
2
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)
ICN
THD+N
PO
6
Idle channel noise
BTL measurement, class-D gain = 6 dB, measured
as idle-channel noise, A-weighted (1) (2)
35.2
μVms
Output voltage
BTL measurement, class-D gain = 6 dB, –3-dBFS
input
1.4
Vrms
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
–73.6
SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
0.7
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.7
SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
0.5
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
1.3
Maximum output power
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W
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER
Device setup
BTL measurement, driver gain = 6 dB, load = 4 Ω
(differential), 50 pF, input signal frequency fi = 1
KHz
Voltage gain
Input common-mode = 0.9 V
Gain error
ICN
THD+N
4
V/V
–1 dBFS (446 mVrms), 1-kHz input signal
±0.7
dB
Idle channel noise
Idle channel, IN1L and IN1R ac-shorted to ground,
measured as idle-channel noise, A-weighted (1) (2)
32.6
μVms
Total harmonic distortion + noise
–1 dBFS (446 mVrms), 1-kHz input signal
–73.7
dB
SPKVDD = 2.7 V, page 1, reg 2, D5-D4 = 00, IO =
50 mA
1.79
V
SPKVDD = 3.6 V, page 1, reg 2, D5-D4 = 00, IO =
50 mA
1.79
V
SPKVDD = 5.5 V, page 1, reg 2, D5-D4 = 00, IO =
50 mA
1.79
V
LOW DROPOUT REGULATOR (AVDD)
AVDD output voltage 1.8 V
Output voltage accuracy
SPVDD = 2.7 V
Load regulation
SPVDD = 2.7 V, 0 A to 50 mA
Line regulation
Input supply range 2.7 V to 5.5 V
Decoupling capacitor
±2
%
7
mV
0.6
mV
55
uA
1.0
uF
Bias current
Noise at 0-A load
A-weighted, 20-Hz to 20-kHz bandwidth
166
uV
Noise at 50-mA load
A-weighted, 20-Hz to 20-kHz bandwidth
174
uV
I(AVDD)
1.32
µA
I(DVDD)
0.04
µA
I(IOVDD)
0.68
µA
I(SPKVDD)
2.24
µA
SHUTDOWN POWER CONSUMPTION
Device setup
Power down POR, /RST held low, AVDD = 1.8V,
IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V
DIGITAL INPUT/OUTPUT
Logic family
VIH
VIL
Logic level
CMOS
IIH = 5 μA, IOVDD ≥ 1.6 V
0.7 ×
IOVDD
IIH = 5 μA, IOVDD < 1.6 V
IOVDD
IIL = 5 μA, IOVDD ≥ 1.6 V
–0.3
V
0.3 ×
IOVDD
IIL = 5 μA, IOVDD < 1.6 V
VOH
IOH = 2 TTL loads
VOL
0.8 ×
IOVDD
V
IOL = 2 TTL loads
Capacitive load
0.25
10
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0
V
pF
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6.6 I2S/LJF/RJF Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.8 V
MIN
IOVDD = 3.3 V
MAX
MIN
UNIT
MAX
td(WS)
WCLK delay
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
ns
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
45
45
ns
ll timing specifications are measured at characterization but not tested at final test.
6.7 I2S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V (1)
IOVDD = 1.8 V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
6
ns
th(WS)
WCLK hold
8
6
ns
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
ns
All timing specifications are measured at characterization but not tested at final test.
6.8 DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V (1)
IOVDD = 1.8 V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
45
UNIT
td(WS)
WCLK delay
ts(DI)
DIN setup
8
th(DI)
DIN hold
8
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
45
MAX
6
ns
ns
6
ns
All timing specifications are measured at characterization but not tested at final test.
6.9 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V (1)
IOVDD = 1.8V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
ns
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
8
ns
All timing specifications are measured at characterization but not tested at final test.
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6.10 I2C Interface Timing
All specifications at 25°C, DVDD = 1.8 V (1)
PARAMETER
STANDARD MODE
MIN
TYP
FAST MODE
MAX
MIN
100
0
TYP
UNIT
MAX
fSCL
SCL clock frequency
0
tHD;STA
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4
0.6
μs
tSU;STA
Setup time for a repeated START
condition
4.7
0.8
μs
2
3.45
0
kHz
tHD;DAT
Data hold time for I C bus devices
tSU;DAT
Data setup time
tr
SDA and SCL rise time
1000
20 + 0.1 Cb
300
ns
tf
SDA and SCL fall time
300
20 + 0.1 Cb
300
ns
tSU;STO
Set-up time for STOP condition
tBUF
Bus free time between a STOP and
START condition
Cb
Capacitive load for each bus line
(1)
0
400
250
0.9
μs
100
ns
4
0.8
μs
4.7
1.3
μs
400
400
pF
All timing specifications are measured at characterization but not tested at final test.
6.11 SPI Interface Timing
At 25°C, DVDD = 1.8V
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN
(1)
IOVDD=3.3V
TYP MAX
MIN
TYP
UNIT
MAX
tsck
SCLK period
100
50
ns
tsckh
SCLK pulse width High
50
25
ns
tsckl
SCLK pulse width Low
50
25
ns
tlead
Enable lead time
30
20
ns
tlag
Enable lag time
30
20
ns
td
Sequential transfer delay
40
20
ta
Slave DOUT access time
tdis
Slave DOUT disable time
tsu
DIN data setup time
15
15
ns
thi
DIN data hold time
15
10
ns
tv;DOUT
DOUT data valid time
25
18
ns
tr
SCLK rise time
4
4
ns
tf
SCLK fall time
4
4
ns
(1)
40
40
ns
40
ns
40
ns
These parameters are based on characterization and are not tested in production.
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WCLK
tr
td(WS)
BCLK
tf
tS(DI)
th(DI)
DIN
T0145-10
Figure 1. I2S/LJF/RJF Timing in Master Mode
WCLK
tr
th(WS)
tS(WS)
tH(BCLK)
BCLK
tL(BCLK)
tf
tS(DI)
DIN
th(DI)
T0145-11
2
Figure 2. I S/LJF/RJF Timing in Slave Mode
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WCLK
td(WS)
td(WS)
tf
BCLK
tr
tS(DI)
DIN
th(DI)
T0146-09
Figure 3. DSP Timing in Master Mode
WCLK
tS(WS)
tS(WS)
th(WS)
th(WS)
tf
tL(BCLK)
BCLK
tH(BCLK)
tS(DI)
tr
DIN
th(DI)
T0146-10
Figure 4. DSP Timing in Slave Mode
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SDA
tBUF
tLOW
tr
tHIGH
tf
tHD;STA
SCL
tHD;STA
tSU;DAT
tSU;STO
tHD;DAT
tSU;STA
STA
STO
STA
STO
T0295-02
Figure 5. I2C Interface Timing
SS
S
t
t Lead
t Lag
t
td
sck
SCLK
tf
t sckl
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
ta
LSB OUT
t h(DIN)
t su
MOSI
BIT 6 . . . 1
MSB IN
BIT 6 . . . 1
LSB IN
Figure 6. SPI Interface Timing Diagram
6.12 Typical Characteristics
6.12.1 Class D Speaker Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude (dB)
Amlitude (dB)
20
±60
±80
±100
±80
±100
±120
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
Frequency (Hz)
16000
20000
0
4000
8000
12000
Frequency (Hz)
C001
(4-Ω Load)
Figure 7. DAC To Speaker Amplitude at 0 dBFS vs
Frequency
12
±60
16000
20000
C002
(4-Ω Load)
Figure 8. AINL To Speaker FFT Amplitude at 0 dBFS vs
Frequency
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Class D Speaker Driver Performance (continued)
100
10.00
THDN (%)
10
THDN (%)
100.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
Gain = 24 dB
1
1.00
SPKVDD=2.7V
Series1
SPKVDD=3V
Series2
0.1
SPKVDD=3.3V
Series4
0.10
SPKVDD=3.6V
Series5
SPKVDD=4.2V
Series6
0.01
SPKVDD=5.5V
Series7
0.01
0
0.5
1
1.5
2
2.5
3
Output Power (W)
0.5
1
1.5
2
2.5
Output Power (W)
C003
(SPKVDD = 5.5 V)
Figure 9. Total Harmonic Distortion + Noise vs 4-Ω
Speaker Power
100.00
0
3
C004
(Gain = 18 dB)
Figure 10. Total Harmonic Distortion + Noise + NOISE vs
4-Ω Speaker Power
100
Gain
= 6 dB
Series1
Gain
= 12 dB
Series2
Gain
= 18 dB
Series4
10.00
10
THDN (%)
THDN (%)
Gain
= 24 dB
Series5
1.00
1
SPKVDD
= 2.7 V
Series1
SPKVDD
=3V
Series2
0.10
0.1
SPKVDD
= 3.3 V
Series4
SPKVDD
= 3.6 V
Series5
SPKVDD
= 4.2 V
Series6
0.01
SPKVDD
= 5.5 V
Series7
0.01
0
0.5
1
1.5
2
2.5
Output Power (W)
0
0.5
1
2
Output Power (W)
C005
(SPKVDD = 5.5 V)
Figure 11. Total Harmonic Distortion + Noise + NOISE vs
8-Ω Speaker Power
1.5
2.5
C006
(Gain = 18 dB)
Figure 12. Total Harmonic Distortion + Noise + NOISE vs
8-Ω Speaker Power
90
80
Efficiency (%)
70
60
50
40
SPKVDD = 2.7 V
SPKVDD = 3 V
SPKVDD = 3.3 V
SPKVDD = 3.6 V
SPKVDD = 4.2 V
SPKVDD = 5.5 V
30
20
10
0
0
200
400
600
800
1000 1200 1400 1600 1800
Output Power (mWatt)
C007
(Gain = 18 dB, Load = 4 Ω)
Figure 13. Total Power Consumption vs Output Power Consumption
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6.12.2 HP Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude ( dB)
Amplitude ( dB)
20
±60
0dBFS
±80
±100
±120
±60
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
16000
20000
Frequency (Hz)
0
±20
±20
±30
±30
THDN (dB)
0
±10
±50
CM=0.75V,AVDD=1.5V
±60
CM=0.75V,AVDD=1.8V
12000
±40
CM=0.75V,
Series4
AVDD=1.95V
±70
CM=0.9V,
Series5
AVDD=1.8V
±80
CM=0.9V,
Series6
AVDD=1.95V
CM=0.9V,AVDD=1.95V
±90
C008
CM=0.75V,
Series2
AVDD=1.8V
CM=0.9V,AVDD=1.8V
±80
20000
CM=0.75V,
Series1
AVDD=1.5V
±50
±60
CM=0.75V,AVDD=1.95V
16000
(16-Ω Load)
Figure 15. AINL TO HP FFT Amplitude at 0 dBFS vs
Frequency
0
±40
8000
Frequency (Hz)
±10
±70
4000
C008
(16-Ω Load)
Figure 14. DAC TO HP FFT Amplitude at 0 dBFS vs
Frequency
THDN (%)
0dBFS
±80
±100
±90
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
Output Power (mW)
0.0
(Gain = 9 dB)
Figure 16. Total Harmonic Distortion + Noise vs HP Power
5.0
10.0
15.0
Output Power (mW)
C010
20.0
25.0
C011
(Gain = 32 dB)
Figure 17. Total Harmonic Distortion + Noise vs HP Power
7 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
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8 Detailed Description
8.1 Overview
TAS2505-Q1 is a low power analog and digital input class-D speaker amplifier. It supports 24-bit digital I2S data
for mono playback. This device is able to drive a speaker up to 4 Ω and programmable digital-signal processing
block. The programmable digital-signal processing block can support Bass boost, treble or EQ functions. The
volume level can be controlled by register control. The device can be controlled through I2C or SPI bus.
TAS2505-Q1 also includes an on-board LDO that runs off the speaker power supply to handle all internal device
analog and digital power needs. The device also includes two analog inputs for mixing in speaker path.
8.2 Functional Block Diagram
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
DAC Signal
Proc.
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
Mono 6
' DAC
Dig
Vol
6 dB to +24 dB
(6 dB steps)
SPKP
6
SPKM
Data
Interface
POR
LDO
LDO_SEL
SPKVDD
RST
SPI/I2C
Control Block
Secondary I2S
Interface
AVDD
Primary I2S
Interface
PLL
Interrupt
Control
Supplies
SPI_SEL
Pin Muxing / Clock Routing
DVDD
IOVDD
SPKVSS
AVSS
MCLK
BCLK
WCLK
DIN
GPIO/DOUT
MISO
SDA/MOSI
SCLK
SCL/SSZ
DVSS
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8.3 Feature Description
8.3.1 Audio Analog I/O
The TAS2505-Q1 features a mono audio DAC. TheTAS2505 can drive a speaker up to 4-Ω impedance.
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Feature Description (continued)
8.3.2 Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital deltasigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is between 32
and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma
modulator stays outside of the audio frequency band. Audio analog outputs include mono class-D speaker
outputs. Because the TAS2505-Q1 contains a mono DAC, it inputs the mono data from the left channel, the right
channel, or a mix of the left and right channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.3.3 DAC
The TAS2505-Q1 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the mono
DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multibit
digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced
performance at low sampling rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and observed in the signal images strongly
suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power
dissipation and performance, the TAS2505-Q1 allows the system designer to program the oversampling rates
over a wide range from 1 to 1024 by configuring page 0, register 13 and page 0 / register 14. The system
designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for
higher input data rates.
The TAS2505-Q1 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the
delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required
frequency response, group delay, and sampling rate.
The DAC path of the TAS2505-Q1 features many options for signal conditioning and signal routing:
• Digital volume control with a range of –63.5 to +24 dB
• Mute function
In addition to the standard set of DAC features the TAS2505-Q1 also offers the following special features:
• Digital auto mute
• Adaptive filter mode
8.3.4 POR
TAS2505-Q1 has a POR (Power-On-Reset) function. This function insures that all registers are automatically set
to defaults when a proper power up sequence is executed.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.3.5 CLOCK Generation and PLL
The TAS2505-Q1 supports a wide range of options for generating clocks for the DAC sections as well as
interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can be
provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference clock for the
codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits D1–D0. The
CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in Figure 2 through 7 in the
TAS2505 Application Reference Guide to generate the various clocks required for the DAC and the Digital
Effects section also found in the TAS2505 Application Reference Guide (SLAU472). In the event that the desired
audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2505-Q1 also
provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to
generate the required clocks. Starting from CODEC_CLKIN, the TAS2505-Q1 provides several programmable
clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the Digital Effects sections.
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Feature Description (continued)
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.3.6 Speaker Driver
The TAS2505-Q1 has an integrated class-D mono speaker driver (SPKP/SPKM) capable of driving an 8-Ω or 4Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the
SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolute maximum
voltage of 6 V. The speaker driver is capable of supplying 800 mW per channel with a 3.6-V power supply.
Through the use of digital mixing, the device can connect one or both digital audio playback data channels to
either speaker driver; this also allows digital channel swapping if needed. The class-D speaker driver can be
powered on by writing to page 1, register 45, bit D1. The class-D output-driver gain can be controlled by writing
to page 1, register 48, bits D6–D4, and it can be muted by writing to page 1, register 48, bit D6 - D4 = 000.
8.3.7 Automotive Diagnostics
The TAS2505-Q1 has SHORT-CIRCUIT PROTECTION /OVER CURRENT PROTECTION (OCP) feature for the
speaker drivers that is always enabled to provide protection. This protects outputs against short to ground,
short to supply and short between output terminals. The output stage shuts down on the over current
condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In case
of a short circuit, the output is disabled. A status flag for OC condition occurrence is provided as a readonly bit on page 1, register 45, bit D1. The D1 bit is cleared when any of the above short circuit condition
happens. If shutdown occurs due to an over current condition, then the device requires a reset to re-enable the
output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires
either toggling the RST pin or using the software reset. If master reset is used, it resets all of the registers.
Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The
speaker power-stage reset is done by setting page 1, register 45, bit D1 for SPKP and SPKM. If the fault
condition has been removed, then the device returns to normal operation. If the fault is still present, then another
shutdown occurs. Repeated resetting (more than three times) is not recommended, as this could lead to
overheating. To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD
voltage level.
The TAS2505 has a OVER TEMPERATURE PROTECTION (OTP) feature for the speaker driver which is always
enabled to provide protection. If the device is overheated, then the output stops switching. When the device
cools down, the output resumes switching. An over temperature status flag is provided as a read-only bit on
page 0, register 45, bit D7. The OTP feature is for self-protection of the device. If die temperature can be
controlled at the system/board level, then over temperature does not occur.
8.4 Device Functional Modes
8.4.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending on the
state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C or SPI protocol.
Other digital IO pins can be configured for various functions through register control. An overview of available
functionality is given in Multifunction Pins.
8.4.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
8.4.3 Multifunction Pins
Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
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Device Functional Modes (continued)
Table 1. Multifunction Pin Assignments
PIN FUNCTION
A
1
2
3
4
5
6
7
MCLK
BCLK
WCLK
DIN
GPIO
/DOUT
SCLK
MISO
S (1)
S (2)
PLL Input
B
Codec Clock Input
C
I2S BCLK input
S
(1)
2
I S WCLK input
F
I2S WCLK output
S (3)
E (5)
I S BCLK output
E
S
S (3)
E
(2)
S (2),D
2
D
,D
(4)
E, D
E
2
G
I S DIN
I
General-Purpose Output I
E, D
I
General-Purpose Output II
J
General-Purpose Input I
J
General-Purpose Input II
J
General-Purpose Input III
K
INT1 output
E
L
INT2 output
E
M
Secondary I2S BCLK input
E
E
N
Secondary I2S WCLK input
E
E
E
E
E
E
E
E
2
E
E
O
Secondary I S DIN
E
P
Secondary I2S BCLK OUT
E
E
Q
Secondary I2S WCLK OUT
E
E
R
Secondary I2S DOUT
S
(1)
(2)
(3)
(4)
(5)
E
Aux Clock Output
E
E
S(1):
S(2):
(3)
The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S : The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
8.4.4 Analog Signals
The TAS2505-Q1 analog signals consist of:
• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output stages
• Analog outputs class-D speaker driver providing output capability for the DAC, AINR, AINL, or a mix of the
three
8.4.4.1 Analog Inputs AINL and AINR
AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output. Also
AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for
determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be attenuated by
Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of HP driver can be
attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural differential input with
use Mixer P and Mixer M by Page1 / register 12 setting.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.5 DAC Processing Blocks — Overview
The TAS2505-Q1 implements signal-processing capabilities and interpolation filtering through processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
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The choices among these processing blocks allows the system designer to balance power conservation and
signal-processing flexibility. Table 2 gives an overview of all available processing blocks of the DAC channel and
their properties. The resource-class column gives an approximate indication of power consumption for the digital
(DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the drivers
(AVDD) may differ.
The signal-processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in
combination with various signal-processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients.
Table 2. Overview – DAC Predefined Processing Blocks
PROCESSING
BLOCK NO.
INTERPOLATION
FILTER
CHANNEL
FIRST-ORDER
IIR AVAILABLE
NUMBER OF
BIQUADS
RESOURCE
CLASS
PRB_P1
A
Mono
Yes
6
6
PRB_P2
A
Mono
No
3
4
PRB_P3
B
Mono
Yes
6
4
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.6 Digital Mixing and Routing
The TAS2505-Q1 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the
digital audio data. The first mixer or multiplexer can be used to select input data for the mono DAC from left
channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by
writing to page 0, register 63, bits D5–D4.
8.4.7 Analog Audio Routing
The TAS2505-Q1 has the capability to route the DAC output to the speaker output. If desirable, both output
drivers can be operated at the same time while playing at different volume levels. The TAS2505-Q1 provides
various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All
analog outputs other than the selected ones can be powered down for optimal power consumption.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.8 5V LDO
The TAS2505-Q1 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply
(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is 50 mA or
less, then this LDO can deliver power to both analog and digital power supplies. If the only speaker power supply
is present and LDO Select pin is enabled, the LDO can power up without requiring other supplies. This LDO
requires a minimum dropout voltage of 300 mV and can support load currents up to 50 mA. For stability reasons
the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the analog supply (AVDD) pin and the
digital supply (DVDD) pin. If use this LDO output voltage for the digital supply (DVDD) pin, the analog supply
(AVDD) pin connected to the digital supply (DVDD) externally is required.
The LDO is by default powered down for low sleep mode currents and can be enabled driving the LDO_SELECT
pin to SPKVDD (speaker power supply). When the LDO is disabled the AVDD pin is tri-stated and the device
AVDD needs to be powered using external supply. In that case the DVDD pin is also tri-stated and the device
DVDD needs to be powered using external supply. The output voltage of this LDO can be adjusted to a few
different values as given in the Table 3.
Table 3. AVDD LDO Settings
Page-1, Register 2, D(5:4)
LDO Output
00
1.8 V
01
1.6 V
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Table 3. AVDD LDO Settings (continued)
Page-1, Register 2, D(5:4)
LDO Output
10
1.7 V
00
1.5 V
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.9 Digital Audio and Control Interface
8.4.9.1 Digital Audio Interface
Audio data is transferred between the host processor and the TAS2505-Q1 via the digital audio data serial
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,
support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation,
flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The audio bus of the TAS2505-Q1 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0,
register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either
master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define
the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of
this clock corresponds to the maximum of the selected DAC sampling frequencies.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.9.2 Control Interface
The TAS2505-Q1 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. TI does not
recommend changing the state of SPI_SEL during device operation.
8.4.9.2.1 I2C Control Mode
The TAS2505-Q1 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a twowire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only
drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus
wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This
way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
8.4.9.2.2 SPI Digital Interface
In the SPI control mode, the TAS2505-Q1 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TAS2505-Q1) depend on a master to start and synchronize transmissions. A transmission begins when initiated
by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the
master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin
to the master shift register.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
8.4.9.3 Device Special Functions
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
20
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8.5 Register Map
Table 4. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2-3
0x00
0x02 - 0x03
Reserved Registers
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P and R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9 - 10
0x00
0x09 - 0x0A Reserved Registers
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15 - 24
0x00
0x0F - 0x18 Reserved Registers
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Reserved Register
0
35 - 36
0x00
0x23 - 0x24
Reserved Registers
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Registers
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Reserved Register
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Reserved Register
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Registers
0
52
0x00
0x34
GPIO/DOUT Control Register
0
53
0x00
0x35
DOUT Function Control Register
0
54
0x00
0x36
DIN Function Control Register
0
55
0x00
0x37
MISO Function Control Register
0
56
0x00
0x38
SCLK/DMDIN2 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Instruction Set
0
61 - 62
0x00
0x3D -0x3E
Reserved Registers
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
DAC Channel Digital Volume Control Register
0
66 - 80
0x00
0x42 - 0x50
Reserved Registers
0
81
0x00
0x51
Dig_Mic Control Register
0
82 - 127
0x00
0x52 - 0x7F Reserved Registers
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
REF, POR and LDO BGAP Control Register
1
2
0x01
0x02
LDO Control Register
1
3
0x01
0x03
Playback Configuration Register 1
1
4-7
0x01
0x04 - 0x07
Reserved Registers
1
8
0x01
0x08
DAC PGA Control Register
1
9
0x01
0x09
Output Drivers, AINL, AINR, Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
HP Over Current Protection Configuration Register
1
12
0x01
0x0C
HP Routing Selection Register
1
13 - 15
0x01
0x0D - 0x0F Reserved Registers
1
16
0x01
0x10
Reserved Registers
1
17 - 19
0x01
0x11 - 0x13
Reserved Registers
1
20
0x01
0x14
Reserved Registers
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
Reserved Registers
1
23
0x01
0x17
Reserved Register
1
24
0x01
0x18
AINL Volume Control Register
1
25
0x01
0x19
AINR Volume Control Register
1
26 - 44
0x01
0x1A - 0x2C Reserved Registers
1
45
0x01
0x2D
Speaker Amplifier Control 1
1
46
0x01
0x2E
Speaker Volume Control Register
1
47
0x01
0x2F
Reserved Register
1
48
0x01
0x30
Speaker Amplifier Volume Control 2
1
49 - 62
0x01
0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register
1
64 - 121
0x01
0x40 - 0x79
Reserved Registers
1
122
0x01
0x7A
Reference Power Up Delay
1
123 - 127
0x01
0x7B - 0x7F Reserved Registers
2 - 43
0 - 127
0x02 - 0x2B 0x00 - 0x7F Reserved Registers
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02 - 0x07
Reserved
44
8 - 127
0x2C
0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)
45 - 52
0
0x2D-0x34
0x00
Page Select Register
45 - 52
1-7
0x2D-0x34
0x01 - 0x07
Reserved.
45 - 52
8 - 127
0x2D-0x34
0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)
53 - 61
0 - 127
0x35 - 0x3D 0x00 - 0x7F Reserved Registers
62 - 70
0
0x3E-0x46
0x00
Page Select Register
62 - 70
1-7
0x3E-0x46
0x01 - 0x07
Reserved Registers
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Register Map (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
62 - 70
8 - 127
0x3E-0x46
0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)
71 - 255
0 - 127
0x47 - 0x7F 0x00 - 0x7F Reserved Registers
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TAS2505-Q1 is a digital or analog input Class-D audio power amplifier. This device include an internal LDO
that can be used to supply the analog and digital internal supply rails. Below are shown different setups that
show the features of the TAS2505-Q1.
9.2 Typical Applications
9.2.1 Typical Configuration
+1.8VA
SVDD
IOVDD
0.1PF
22PF
2.7k
0.1PF
22PF
2.7k
AVSS
AVDD
LDO_SEL
SPKVSS SPKVDD
GPIO/DOUT
HOST PROCESSOR
SDA/MOSI
SCL/SSZ
8-: or
4-:
Speaker
MCLK
SPKP
SPKM
TAS2505
WCLK
DIN
BCLK
Headphone jack
RST
HPOUT
0.1PF
47PF
AINL
AINR
Analog Input
0.1PF
MISO
SCLK
SPI_SEL
DVDD DVSS
+1.8VD
0.1PF
IOVDD
IOVSS
IOVDD
10PF
0.1PF
10PF
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Typical Circuit Configuration
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Typical Applications (continued)
9.2.1.1 Design Requirements
Table 5 shows the design parameters.
Table 5. Design Parameters
PARAMETER
EXAMPLE VALUE
Audio input
Digital Audio (I2S), Analog Audio AINx
Internal LDO
Not used
Speaker
8-Ω or 4-Ω
9.2.1.2 Detailed Design Procedure
In this application, the device is able to use both digital and analog inputs, working in mono output by summing
left and right analog inputs and output from DAC and routing this signal into the speaker output.
The internal LDO is not used in this application because the LDO_SEL pin is tied to GND. External 1.8-V supply
is used to power AVDD and DVDD. IOVDD can be supplied by voltages between 1.1 V and 3.6 V which lets the
system to use conventional 1.8-V or 3.3-V supplies. The SPKVDD can be connected to voltages between 2.7 V
and 5.5 V, although it is usually supplied by a 5-V voltage.
Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1-µF, 10-µF, and 22-µF
capacitors for a better system performance.
Decoupling series capacitors must be used at the analog input.
All grounds are tied together; route analog and digital paths are separated to avoid interference.
9.2.1.3 Application Curves
100
10.00
THDN (%)
10
THDN (%)
100.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
Gain = 24 dB
1
1.00
SPKVDD=2.7V
Series1
SPKVDD=3V
Series2
0.1
SPKVDD=3.3V
Series4
0.10
SPKVDD=3.6V
Series5
SPKVDD=4.2V
Series6
0.01
SPKVDD=5.5V
Series7
0.01
0
0.5
1
1.5
Output Power (W)
2
2.5
3
0
(SPKVDD = 5.5 V)
Figure 19. Total Harmonic Distortion + Noise vs 4-Ω
Speaker Power
0.5
1
1.5
2
2.5
Output Power (W)
C003
3
C004
(Gain = 18 dB)
Figure 20. Total Harmonic Distortion + Noise vs 4-Ω
Speaker Power
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0
±10
±20
THDN (%)
±30
±40
±50
CM=0.75V,AVDD=1.5V
±60
CM=0.75V,AVDD=1.8V
CM=0.75V,AVDD=1.95V
±70
CM=0.9V,AVDD=1.8V
±80
CM=0.9V,AVDD=1.95V
±90
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
Output Power (mW)
C010
(Gain = 9 dB)
Figure 21. Total Harmonic Distortion + Noise vs HP Power
9.2.2 Circuit Configuration With Internal LDO
SVDD
IOVDD
22PF
2.7k
0.1PF
10PF
0.1PF
0.1PF
22PF
2.7k
AVSS
AVDD DVSS
DVDD
LDO_SEL SPKVSS SPKVDD
GPIO/DOUT
HOST PROCESSOR
SDA/MOSI
SCL/SSZ
8-: or
4-:
Speaker
MCLK
WCLK
DIN
SPKP
SPKM
TAS2505
BCLK
Headphone jack
RST
HPOUT
0.1PF
47PF
AINL
AINR
Analog Input
0.1PF
MISO
SCLK
SPI_SEL
IOVDD
IOVSS
IOVDD
0.1PF
10PF
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Application Schematics for LDO
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9.2.2.1 Design Requirements
Table 6 shows the design parameters.
Table 6. Design Parameters
PARAMETER
EXAMPLE VALUE
Audio input
Digital Audio (I2S), Analog Audio
AINx
Internal LDO
Used
Speaker
8-Ω or 4-Ω
10 Power Supply Recommendations
The TAS2505-Q1 integrates a large amount of digital and analog functionality, and each of these blocks can be
powered separately to enable the system to select appropriate power supplies for desired performance and
power consumption. The device has separate power domains for digital IO, digital core, analog core, analog
input and speaker drivers. If desired, all of the supplies (except for the supplies for speaker drivers, which can
directly connect to the battery) can be connected together and be supplied from one source in the range of 1.65
to 1.95 V. Individually, the IOVDD voltage can be supplied in the range of 1.1 V to 3.6 V. For improved power
efficiency, the digital core power supply can range from 1.26 V to 1.95 V. The analog core supply can either be
derived from the internal LDO accepting an SPKVDD voltage in the range of 2.7 V to 5.5 V, or the AVDD pin can
directly be driven with a voltage in the range of 1.5 V to 1.95 V. The speaker driver voltages (SPKVDD) can
range from 2.7 V to 5.5 V.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
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11 Layout
11.1 Layout Guidelines
•
•
•
If the analog input, AINR and AINL, are:
– Used, analog input traces must be routed symmetrically for true differential performance.
– Used, do not run analog input traces parallel to digital lines.
– Used, they must be AC-coupled.
– Not used, they must be shorted together.
Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for
minimum ground noise.
Use supply decoupling capacitors.
11.2 Layout Example
Figure 23. Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TAS2505 Application Reference Guide (SLAU472)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RGE0024K
VQFN - 1 mm max height
SCALE 3.300
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
0.5
0.3
0.3
0.2
PIN 1 INDEX AREA
DETAIL
4.1
3.9
OPTIONAL TERMINAL
TYPICAL
0.1 MIN
(0.05)
SECTION A-A
A-A 25.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2.8
0.1
2X 2.5
EXPOSED
THERMAL PAD
A2
20X 0.5
6
(0.2) TYP
8X (0.38)
12
7
A3
13
2X
2.5
25
A
A
8X (0.2)
SYMM
SEE TERMINAL
DETAIL
1
18
24X
A1
PIN 1 ID
(OPTIONAL)
24
19
SYMM
24X
A4
0.5
0.3
0.3
0.2
0.1
0.05
C A B
4223589/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGE0024K
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.8)
4X (1.72)
SYMM
24X (0.6)
8X (0.58)
19
24
8X (0.2)
A4
A1
18
1
4X
(1.72)
24X (0.25)
25
SYMM
(3.8)
20X (0.5)
(1.15)
6
13
( 0.2) TYP
VIA
(R0.05)
TYP
A2
A3
7
12
(1.15)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223589/A 03/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGE0024K
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.72)
(0.715)
TYP
24X (0.6)
24
8X (0.58)
19
8X (0.2)
A4
A1
25
1
4X
(1.72)
18
24X (0.25)
(0.715)
TYP
SYMM
(3.8)
20X (0.5)
4X
( 1.23)
6
13
EXPOSED METAL
TYP
(R0.05) TYP
A2
A3
7
SYMM
12
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
THERMAL PAD 25:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223589/A 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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18-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TAS2505TRGERQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGE
24
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
TAS
2505Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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