TAS2505
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
TAS2505 2.6-W Digital/Analog Input Class-D Speaker Amplifier With Audio Processing
1 Features
3 Description
•
The TAS2505 is a mono Class-D speaker amp that
supports both Digital and Analog inputs. The device
is ideal for automotive instrument cluster, emergency
call (eCall), and telematics applications. Direct I2S
input removes the need for an external DAC in
the audio signal path. In addition to integration, the
device features programmable audio processing. The
onboard DSP supports bass boost, treble, and EQ
(up to 6 biquads). An on-chip PLL provides the highspeed clock needed by the DSP. The volume level is
register controlled.
(1)
VQFN (24)
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
DAC Signal Proc.
6 dB to +24 dB
(6 dB steps)
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
Dig
Vol
Mono S-D
DAC
SPKP
S
SPKM
-6 dB to +29 dB
and Mute
(1 dB steps)
S
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
HPOUT
Data
Interface
POR
SPKVDD
SPI_SEL
SPI/I2C
Control Block
Secondary I2S
Interface
PLL
Primary I2S
Interface
AVDD
Interrupt
Control
DVDD
Supplies
Instrument Cluster
Automotive Emergency Call (eCall)
Telematics
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
RST
IOVDD
SPKVSS
Pin Muxing / Clock Routing
AVSS
SDA/MOSI
MISO
SCLK
DVSS
SCL/SSZ
•
•
•
BODY SIZE (NOM)
MCLK
•
•
TAS2505
PACKAGE
DIN
•
PART NUMBER
BCLK
•
•
Device Information(1)
WCLK
•
•
GPIO/DOUT
•
•
•
Mono Class-D BTL Speaker Amplifier
– 2.6 W at 10% THD_N (4Ω, 5.5 V)
– 1.7 W at 10% THD+N (8 Ω, 5.5 V)
Supports both Digital and Analog Input
Single Supply 2.7 V to 5.5 V
Load Diagnostic Functions:
– Output-to-GND Short
– Terminal-to-Terminal Short
– Output-to-Power Short
– Over Temperature
– Input DC
Supports 9-kHz to 96-kHz Sample Rates
Two Single-Ended Inputs with Output Mixing and
Level Control
Embedded Power-On-Reset
Programmable Digital Audio Processing:
– Bass Boost
– Treble
– EQ (up to 6 Biquads)
I2S, Left-Justified, Right-Justified, DSP, and TDM
Audio Interfaces
I2C and SPI Control With Auto-Increment
24-Pin, VQFN Package
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 I2S/LJF/RJF Timing in Master Mode........................... 7
6.7 I2S/LJF/RJF Timing in Slave Mode............................. 7
6.8 DSP Timing in Master Mode....................................... 7
6.9 DSP Timing in Slave Mode......................................... 7
6.10 I2C Interface Timing.................................................. 8
6.11 SPI Interface Timing..................................................8
6.12 Typical Characteristics............................................ 11
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................16
7.5 Register Map.............................................................19
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................24
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 Receiving Notification of Documentation Updates.. 27
11.3 Community Resources............................................27
11.4 Trademarks............................................................. 27
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2016) to Revision C (September 2021)
Page
• Removed all references to LDO mode and LDO_SEL pin throughout data sheet ............................................ 1
Changes from Revision A (February 2013) to Revision B (November 2016)
Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .......... 1
Changes from Revision * (February 2013) to Revision A (February 2013)
Page
• Deleted PO (Max Output power) SPKVDD = 5.5 V, THD = 10%........................................................................ 5
• Changed PO (Max Output power) SPKVDD = 5.5 V value From: TYP = 2.1 W To: MAX = 2 W........................ 5
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
DVSS
DVDD
IOVDD
SCLK
SDA/MOSI
SCL/SSZ
5 Pin Configuration and Functions
24
23 22
21
20
19
18
GPIO/DOUT
MISO
AINL
3
16
MCLK
AINR
4
15
BCLK
HPOUT
5
14
WCLK
AVSS
6
8
9
10
11
DIN
13
12
SPKP
7
SPKVSS
17
SPKVDD
2
SPKM
RST
LDO_SEL
1
AVDD
SPI_SEL
Figure 5-1. RGE Package 24-Pin VQFN Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE(1)
DESCRIPTION
SPI_SEL
I
Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
2
RST
I
Reset for logic, state machines, and digital filters; asserted LOW.
3
AINL
I
Analog single-ended line left input
4
AINR
I
Analog single-ended line right input
5
NC
O
No Connect (Leave unconnected)
6
AVSS
GND
Analog Ground, 0 V
7
AVDD
PWR
Analog Core Supply Voltage, 1.5 V to 1.95 V
8
LDO_SEL
I
Connect to ground.
9
SPKM
O
Class-D speaker driver inverting output
10
SPKVDD
PWR
Class-D speaker driver power supply
11
SPKVSS
PWR
Class-D speaker driver power supply ground supply
12
SPKP
O
Class-D speaker driver noninverting output
13
DIN
I
Audio Serial Data Bus Input Data
14
WCLK
I/O
Audio Serial Data Bus Word Clock
15
BCLK
I/O
Audio Serial Data Bus Bit Clock
16
MCLK
I
Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
17
MISO
O
SPI Serial Data Output
18
GPIO/DOUT
I/O/Z
19
SCL/SSZ
I
Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
20
SDA/MOSI
I
Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
Serial clock for SPI interface
1
GPIO / Audio Serial Bus Output
21
SCLK
I
22
IOVDD
PWR
I/O Power Supply, 1.1 V to 3.6 V
23
DVDD
PWR
Digital Power Supply, 1.65 V to 1.95 V
24
DVSS
GND
Digital Ground, 0 V
(1)
I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
3
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
AVDD to AVSS
–0.3
2.2
V
DVDD to DVSS
–0.3
2.2
V
SPKVDD to SPKVSS
–0.3
6
V
IOVDD to IOVSS
–0.3
3.9
V
Digital input voltage
IOVSS – 0.3
IOVDD + 0.3
V
Analog input voltage
AVSS – 0.3
AVDD + 0.3
V
–40
85
°C
105
°C
Operating temperature
Junction temperature, TJ Max
Power dissipation for VQFN package (with thermal pad soldered to board)
(TJ Max – TA) / θJA
Storage temperature, Tstg
(1)
–55
W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
AVSS(1)
1.5
1.8
1.95
(1)
1.65
1.8
1.95
AVDD(2)
Referenced to
DVDD
Referenced to DVSS
SPKVDD(2)
Power-supply voltage
Referenced to SPKVSS
(1)
(1)
IOVDD
Referenced to IOVSS
Speaker impedance
Load applied across class-D output pins (BTL)
VI
Analog audio full-scale input
voltage
AVDD = 1.8 V, single-ended
MCLK(3)
Master clock frequency
IOVDD = DVDD = 1.8 V
SCL
SCL clock frequency
TA
Operating free-air temperature
(1)
(2)
(3)
2.7
1.1
5.5
1.8
UNIT
V
3.6
4
Ω
0.5
–40
VRMS
50
MHz
400
kHz
85
°C
All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
6.4 Thermal Information
TAS2505
THERMAL METRIC(1)
RGE (QFN)
UNIT
24 PINS
4
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
Submit Document Feedback
32.2
°C/W
30
°C/W
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
TAS2505
THERMAL METRIC(1)
RGE (QFN)
UNIT
24 PINS
θJB
Junction-to-board thermal resistance
9.2
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
9.2
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
8.48
MHz
DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS
See TAS2505 Application Reference Guide (SLAU472) for DAC interpolation filter characteristics.
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL)
Idle channel noise
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted(2) (1)
37
μVms
Output voltage
BTL measurement, class-D gain = 6 dB, –3-dBFS
input
1.4
Vrms
THD+N
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
–73.9
dB
PSRR
Power-supply rejection ratio
BTL measurement, ripple on SPKVDD = 200 mVPP
at 1 kHz
55
dB
Mute attenuation
Mute
103
dB
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1.1
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.4
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
1.1
ICN
PO
Maximum output power
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB
W
2
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)
ICN
THD+N
Idle channel noise
BTL measurement, class-D gain = 6 dB, measured
as idle-channel noise, A-weighted(2) (1)
35.2
μVms
Output voltage
BTL measurement, class-D gain = 6 dB, –3-dBFS
input
1.4
Vrms
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
–73.6
dB
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
5
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
PO
Maximum output power
TEST CONDITIONS
MIN
TYP
SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
0.7
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.7
SPKVDD = 3.6 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
0.5
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 5.5 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 1%
1.3
MAX
UNIT
W
ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER
Device setup
BTL measurement, driver gain = 6 dB, load = 4 Ω
(differential), 50 pF, input signal frequency fi = 1
KHz
Voltage gain
Input common-mode = 0.9 V
4
V/V
Gain error
–1 dBFS (446 mVrms), 1-kHz input signal
±0.7
dB
ICN
Idle channel noise
Idle channel, IN1L and IN1R ac-shorted to ground,
measured as idle-channel noise, A-weighted(2) (1)
32.6
μVms
THD+N
Total harmonic distortion + noise –1 dBFS (446 mVrms), 1-kHz input signal
–73.7
dB
I(AVDD)
1.32
µA
I(DVDD)
0.04
µA
I(IOVDD)
0.68
µA
I(SPKVDD)
2.24
µA
SHUTDOWN POWER CONSUMPTION
Device setup
Power down POR, /RST held low, AVDD = 1.8V,
IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V
DIGITAL INPUT/OUTPUT
Logic family
VIH
VIL
Logic level
CMOS
IIH = 5 μA, IOVDD ≥ 1.6 V
0.7 ×
IOVDD
IIH = 5 μA, IOVDD < 1.6 V
IOVDD
IIL = 5 μA, IOVDD ≥ 1.6 V
–0.3
V
0.3 ×
IOVDD
IIL = 5 μA, IOVDD < 1.6 V
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
Capacitive load
(1)
(2)
6
V
0
0.8 ×
IOVDD
V
0.25
10
V
pF
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over
a 20-Hz to 20-kHz bandwidth using an audio analyzer.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
6.6 I2S/LJF/RJF Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V(1)
PARAMETER
IOVDD = 1.8 V
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
td(WS)
WCLK delay
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
6
ns
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
45
UNIT
45
ns
ll timing specifications are measured at characterization but not tested at final test.
6.7 I2S/LJF/RJF Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V(1)
IOVDD = 1.8 V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
6
ns
th(WS)
WCLK hold
8
6
ns
ts(DI)
DIN setup
8
6
ns
th(DI)
DIN hold
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
6
ns
All timing specifications are measured at characterization but not tested at final test.
6.8 DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V(1)
IOVDD = 1.8 V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
45
UNIT
td(WS)
WCLK delay
ts(DI)
DIN setup
8
th(DI)
DIN hold
8
tr
Rise time
25
10
ns
tf
Fall time
25
10
ns
(1)
45
MAX
6
ns
ns
6
ns
All timing specifications are measured at characterization but not tested at final test.
6.9 DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V(1)
IOVDD = 1.8V
PARAMETER
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
ns
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
4
4
ns
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
7
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
All specifications at 25°C, DVDD = 1.8 V(1)
IOVDD = 1.8V
PARAMETER
tf
(1)
MIN
IOVDD = 3.3 V
MAX
Fall time
MIN
MAX
4
4
UNIT
ns
All timing specifications are measured at characterization but not tested at final test.
6.10 I2C Interface Timing
All specifications at 25°C, DVDD = 1.8 V(1)
PARAMETER
STANDARD MODE
MIN
TYP
FAST MODE
MAX
MIN
100
0
UNIT
TYP
MAX
fSCL
SCL clock frequency
0
tHD;STA
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4
0.6
μs
tSU;STA
Setup time for a repeated START condition
4.7
0.8
μs
I2C
0
3.45
0
kHz
tHD;DAT
Data hold time for
tSU;DAT
Data setup time
tr
SDA and SCL rise time
1000
20 + 0.1 Cb
300
ns
tf
SDA and SCL fall time
300
20 + 0.1 Cb
300
ns
tSU;STO
Set-up time for STOP condition
tBUF
Bus free time between a STOP and
START condition
Cb
Capacitive load for each bus line
(1)
bus devices
400
250
0.9
μs
100
ns
4
0.8
μs
4.7
1.3
μs
400
400
pF
All timing specifications are measured at characterization but not tested at final test.
6.11 SPI Interface Timing
At 25°C, DVDD = 1.8V
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN
tsck
SCLK period (1)
tsckh
tsckl
MAX
MIN
TYP
UNIT
MAX
100
50
ns
SCLK pulse width High
50
25
ns
SCLK pulse width Low
50
25
ns
tlead
Enable lead time
30
20
ns
tlag
Enable lag time
30
20
ns
td
Sequential transfer delay
40
ta
Slave DOUT access time
tdis
Slave DOUT disable time
tsu
DIN data setup time
15
thi
DIN data hold time
15
tv;DOUT
DOUT data valid time
tr
tf
(1)
8
TYP
IOVDD=3.3V
20
40
40
ns
40
ns
40
ns
15
ns
10
ns
25
18
ns
SCLK rise time
4
4
ns
SCLK fall time
4
4
ns
These parameters are based on characterization and are not tested in production.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
WCLK
tr
td(WS)
BCLK
tf
tS(DI)
th(DI)
DIN
T0145-10
Figure 6-1.
I2S/LJF/RJF
Timing in Master Mode
WCLK
tr
th(WS)
tS(WS)
tH(BCLK)
BCLK
tL(BCLK)
tf
tS(DI)
DIN
th(DI)
T0145-11
Figure 6-2. I2S/LJF/RJF Timing in Slave Mode
WCLK
td(WS)
td(WS)
tf
BCLK
tS(DI)
tr
DIN
th(DI)
T0146-09
Figure 6-3. DSP Timing in Master Mode
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
9
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
WCLK
tS(WS)
tS(WS)
th(WS)
th(WS)
tf
tL(BCLK)
BCLK
tr
tS(DI)
tH(BCLK)
DIN
th(DI)
T0146-10
Figure 6-4. DSP Timing in Slave Mode
SDA
tBUF
tLOW
tr
tHIGH
tf
tHD;STA
SCL
tHD;STA
tSU;DAT
tHD;DAT
STO
tSU;STO
tSU;STA
STA
STA
STO
T0295-02
Figure 6-5. I2C Interface Timing
SS
S
t
t Lead
t Lag
t
td
sck
SCLK
t sckl
tf
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
ta
MOSI
t su
BIT 6 . . . 1
LSB OUT
t h(DIN)
MSB IN
BIT 6 . . . 1
LSB IN
Figure 6-6. SPI Interface Timing Diagram
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
6.12 Typical Characteristics
6.12.1 Class D Speaker Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude (dB)
Amlitude (dB)
20
±60
±80
±100
±80
±100
±120
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
16000
Frequency (Hz)
20000
0
12000
16000
20000
C002
(4-Ω Load)
Figure 6-8. AINL To Speaker FFT Amplitude at 0
dBFS vs Frequency
100.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
Gain = 24 dB
10.00
THDN (%)
10
8000
Frequency (Hz)
(4-Ω Load)
100
4000
C001
Figure 6-7. DAC To Speaker Amplitude at 0 dBFS
vs Frequency
THDN (%)
±60
1
1.00
SPKVDD=2.7V
Series1
SPKVDD=3V
Series2
0.1
SPKVDD=3.3V
Series4
0.10
SPKVDD=3.6V
Series5
SPKVDD=4.2V
Series6
0.01
SPKVDD=5.5V
Series7
0.01
0
0.5
1
1.5
2
2.5
Output Power (W)
3
(SPKVDD = 5.5 V)
0.5
1
1.5
2
2.5
Output Power (W)
3
C004
(Gain = 18 dB)
Figure 6-9. Total Harmonic Distortion + Noise vs
4-Ω Speaker Power
100.00
0
C003
Figure 6-10. Total Harmonic Distortion + Noise +
NOISE vs 4-Ω Speaker Power
100
Gain
= 6 dB
Series1
Gain
= 12 dB
Series2
Gain
= 18 dB
Series4
10.00
10
THDN (%)
THDN (%)
Gain
= 24 dB
Series5
1.00
1
SPKVDD
= 2.7 V
Series1
SPKVDD
=3V
Series2
0.10
0.1
SPKVDD
= 3.3 V
Series4
SPKVDD
= 3.6 V
Series5
SPKVDD
= 4.2 V
Series6
0.01
SPKVDD
= 5.5 V
Series7
0.01
0
0.5
1
1.5
Output Power (W)
2
2.5
0
1
1.5
Output Power (W)
C005
(SPKVDD = 5.5 V)
0.5
2
2.5
C006
(Gain = 18 dB)
Figure 6-11. Total Harmonic Distortion + Noise +
NOISE vs 8-Ω Speaker Power
Figure 6-12. Total Harmonic Distortion + Noise +
NOISE vs 8-Ω Speaker Power
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
11
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
90
80
Efficiency (%)
70
60
50
40
SPKVDD = 2.7 V
SPKVDD = 3 V
SPKVDD = 3.3 V
SPKVDD = 3.6 V
SPKVDD = 4.2 V
SPKVDD = 5.5 V
30
20
10
0
0
200
400
600
800
1000 1200 1400 1600 1800
Output Power (mWatt)
C007
(Gain = 18 dB, Load = 4 Ω)
Figure 6-13. Total Power Consumption vs Output Power Consumption
6.12.2 HP Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude ( dB)
Amplitude ( dB)
20
±60
0dBFS
±80
±100
±120
±60
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
16000
20000
Frequency (Hz)
0
4000
(16-Ω Load)
8000
12000
C008
(16-Ω Load)
0
±10
±20
±20
±30
±30
THDN (dB)
0
±40
±50
CM=0.75V,AVDD=1.5V
±60
CM=0.75V,AVDD=1.8V
CM=0.9V,AVDD=1.8V
±80
±40
CM=0.75V,
Series1
AVDD=1.5V
±50
CM=0.75V,
Series2
AVDD=1.8V
±60
CM=0.75V,AVDD=1.95V
±70
CM=0.75V,
Series4
AVDD=1.95V
±70
CM=0.9V,
Series5
AVDD=1.8V
±80
CM=0.9V,
Series6
AVDD=1.95V
CM=0.9V,AVDD=1.95V
±90
±90
5.0
10.0
15.0
20.0
25.0
Output Power (mW)
30.0
35.0
40.0
0.0
(Gain = 9 dB)
5.0
10.0
15.0
Output Power (mW)
C010
20.0
25.0
C011
(Gain = 32 dB)
Figure 6-16. Total Harmonic Distortion + Noise vs
HP Power
12
20000
Figure 6-15. AINL TO HP FFT Amplitude at 0 dBFS
vs Frequency
±10
0.0
16000
Frequency (Hz)
C008
Figure 6-14. DAC TO HP FFT Amplitude at 0 dBFS
vs Frequency
THDN (%)
0dBFS
±80
±100
Figure 6-17. Total Harmonic Distortion + Noise vs
HP Power
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
Parameter Measurement Information
All parameters are measured according to the conditions described in the Section 6 section.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
13
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
7 Detailed Description
7.1 Overview
TAS2505 is a low power analog and digital input class-D speaker amplifier. It supports 24-bit digital I2S data for
mono playback. This device is able to drive a speaker up to 4 Ω and programmable digital-signal processing
block. The programmable digital-signal processing block can support Bass boost, treble or EQ functions. The
volume level can be controlled by register control. The device can be controlled through I2C or SPI bus. The
device also includes two analog inputs for mixing in speaker path.
7.2 Functional Block Diagram
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
DAC Signal Proc.
6 dB to +24 dB
(6 dB steps)
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
Dig
Vol
Mono S-D
DAC
SPKP
S
SPKM
-6 dB to +29 dB
and Mute
(1 dB steps)
S
HPOUT
POR
Data
Interface
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
SPKVDD
SPI/I2C
Control Block
Secondary I2S
Interface
PLL
Primary I2S
Interface
AVDD
Interrupt
Control
DVDD
Supplies
SPI_SEL
RST
IOVDD
SPKVSS
Pin Muxing / Clock Routing
AVSS
MCLK
BCLK
DIN
WCLK
GPIO/DOUT
SDA/MOSI
MISO
SCLK
SCL/SSZ
DVSS
7.3 Feature Description
7.3.1 Audio Analog I/O
The TAS2505 features a mono audio DAC. TheTAS2505 can drive a speaker up to 4-Ω impedance.
7.3.2 Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital deltasigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is between 32
and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma
modulator stays outside of the audio frequency band. Audio analog outputs include mono class-D speaker
outputs. Because the TAS2505 contains a mono DAC, it inputs the mono data from the left channel, the right
channel, or a mix of the left and right channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4.
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
www.ti.com
TAS2505
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.3.3 DAC
The TAS2505 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the
mono DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter,
multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and observed in the signal images
strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power
dissipation and performance, the TAS2505 allows the system designer to program the oversampling rates over a
wide range from 1 to 1024 by configuring page 0, register 13 and page 0 / register 14. The system designer can
choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data
rates.
The TAS2505 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the
delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required
frequency response, group delay, and sampling rate.
The DAC path of the TAS2505 features many options for signal conditioning and signal routing:
• Digital volume control with a range of –63.5 to +24 dB
• Mute function
In addition to the standard set of DAC features the TAS2505 also offers the following special features:
• Digital auto mute
• Adaptive filter mode
7.3.4 POR
TAS2505 has a POR (Power-On-Reset) function. This function insures that all registers are automatically set to
defaults when a proper power up sequence is executed.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.3.5 CLOCK Generation and PLL
The TAS2505 supports a wide range of options for generating clocks for the DAC sections as well as interface
and other control blocks. The clocks for the DAC require a source reference clock. This clock can be provided on
a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference clock for the codec can
be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits D1–D0. The CODEC_CLKIN
can then be routed through highly-flexible clock dividers shown in Figure 2 through 7 in the TAS2505 Application
Reference Guide to generate the various clocks required for the DAC and the Digital Effects section also found
in the TAS2505 Application Reference Guide (SLAU472). In the event that the desired audio clocks cannot be
generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2505 also provides the option of using
the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks.
Starting from CODEC_CLKIN, the TAS2505 provides several programmable clock dividers to help achieve a
variety of sampling rates for the DAC and clocks for the Digital Effects sections.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
15
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4 Device Functional Modes
7.4.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending on
the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C or SPI
protocol.
Other digital IO pins can be configured for various functions through register control. An overview of available
functionality is given in Section 7.4.3.
7.4.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks
are powered down by default. The blocks can be powered up with fine granularity according to the application
needs.
7.4.3 Multifunction Pins
Table 7-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 7-1. Multifunction Pin Assignments
PIN FUNCTION
1
2
3
4
5
6
7
MCLK
BCLK
WCLK
DIN
GPIO
/DOUT
SCLK
MISO
S(2)
S(3)
S(2),D(5)
S(3)
S(4)
A
PLL Input
E
B
Codec Clock Input
C
I2S
D
I2S BCLK output
E
I2S
F
I2S WCLK output
G
I2S
I
General-Purpose Output I
I
General-Purpose Output II
J
General-Purpose Input I
J
General-Purpose Input II
J
General-Purpose Input III
K
INT1 output
E
E
L
INT2 output
E
E
S(4)
S(3),D
BCLK input
WCLK input
E(1)
E, D
E
DIN
E, D
I2S
E
E
E
E
E
M
Secondary
BCLK input
E
E
N
Secondary I2S WCLK input
E
E
O
Secondary
I2S
E
E
P
Secondary I2S BCLK OUT
E
E
Q
Secondary
I2S
E
E
R
Secondary I2S DOUT
S
Aux Clock Output
(1)
(2)
(3)
(4)
16
DIN
WCLK OUT
E
E
E
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S(3): The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
(5)
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
D: Default Function
7.4.4 Analog Signals
The TAS2505 analog signals consist of:
• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output stages
• Analog outputs class-D speaker driver providing output capability for the DAC, AINR, AINL, or a mix of the
three
7.4.4.1 Analog Inputs AINL and AINR
AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output.
Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for
determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be attenuated by
Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of HP driver can be
attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural differential input with
use Mixer P and Mixer M by Page1 / register 12 setting.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4.5 DAC Processing Blocks — Overview
The TAS2505 implements signal-processing capabilities and interpolation filtering through processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
The choices among these processing blocks allows the system designer to balance power conservation and
signal-processing flexibility. Table 7-2 gives an overview of all available processing blocks of the DAC channel
and their properties. The resource-class column gives an approximate indication of power consumption for the
digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the
drivers (AVDD) may differ.
The signal-processing blocks available are:
•
•
First-order IIR
Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in
combination with various signal-processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients.
Table 7-2. Overview – DAC Predefined Processing Blocks
PROCESSING
BLOCK NO.
INTERPOLATION
FILTER
CHANNEL
FIRST-ORDER
IIR AVAILABLE
NUMBER OF
BIQUADS
RESOURCE
CLASS
PRB_P1
A
Mono
Yes
6
6
PRB_P2
A
Mono
No
3
4
PRB_P3
B
Mono
Yes
6
4
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4.6 Digital Mixing and Routing
The TAS2505 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital
audio data. The first mixer or multiplexer can be used to select input data for the mono DAC from left channel,
right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by writing to
page 0, register 63, bits D5–D4.
7.4.7 Analog Audio Routing
The TAS2505 has the capability to route the DAC output to the speaker output. If desirable, both output drivers
can be operated at the same time while playing at different volume levels. The TAS2505 provides various digital
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
17
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs
other than the selected ones can be powered down for optimal power consumption.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4.8 Digital Audio and Control Interface
7.4.8.1 Digital Audio Interface
Audio data is transferred between the host processor and the TAS2505 via the digital audio data serial interface,
or audio bus. The audio bus on this device is flexible, including left- or right-justified data options, support for I2S
or PCM protocols, programmable data-length options, a TDM mode for multichannel operation, flexible master or
slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
The audio bus of the TAS2505 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation,
where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0, register 27,
bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave
mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning
of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock
corresponds to the maximum of the selected DAC sampling frequencies.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4.8.2 Control Interface
The TAS2505 control interface supports SPI or I2C communication protocols, with the protocol selectable using
the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. TI does not
recommend changing the state of SPI_SEL during device operation.
7.4.8.2.1 I2C Control Mode
The TAS2505 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
7.4.8.2.2 SPI Digital Interface
In the SPI control mode, the TAS2505 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO, SDA/
MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL
= 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master)
and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing
clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TAS2505) depend on a
master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte
from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven
onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
7.4.8.3 Device Special Functions
•
•
Interrupt generation
Flexible pin multiplexing
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
7.5 Register Map
Table 7-3. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2-3
0x00
0x02 - 0x03
Reserved Registers
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P and R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9 - 10
0x00
0x09 - 0x0A Reserved Registers
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15 - 24
0x00
0x0F - 0x18 Reserved Registers
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Reserved Register
0
35 - 36
0x00
0x23 - 0x24
Reserved Registers
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Registers
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Reserved Register
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Reserved Register
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Registers
0
52
0x00
0x34
GPIO/DOUT Control Register
0
53
0x00
0x35
DOUT Function Control Register
0
54
0x00
0x36
DIN Function Control Register
0
55
0x00
0x37
MISO Function Control Register
0
56
0x00
0x38
SCLK/DMDIN2 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
19
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
Table 7-3. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
60
0x00
0x3C
DAC Instruction Set
0
61 - 62
0x00
0x3D -0x3E
Reserved Registers
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
DAC Channel Digital Volume Control Register
0
66 - 80
0x00
0x42 - 0x50
Reserved Registers
0
81
0x00
0x51
Dig_Mic Control Register
0
82 - 127
0x00
0x52 - 0x7F Reserved Registers
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
REF, POR and BGAP Control Register
1
2
0x01
0x02
Reserved Register
1
3
0x01
0x03
Playback Configuration Register 1
1
4-7
0x01
0x04 - 0x07
Reserved Registers
1
8
0x01
0x08
DAC PGA Control Register
1
9
0x01
0x09
Output Drivers, AINL, AINR, Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
HP Over Current Protection Configuration Register
1
12
0x01
0x0C
HP Routing Selection Register
1
13 - 15
0x01
0x0D - 0x0F Reserved Registers
1
16
0x01
0x10
Reserved Registers
1
17 - 19
0x01
0x11 - 0x13
Reserved Registers
1
20
0x01
0x14
Reserved Registers
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
Reserved Registers
1
23
0x01
0x17
Reserved Register
1
24
0x01
0x18
AINL Volume Control Register
1
25
0x01
0x19
AINR Volume Control Register
1
26 - 44
0x01
0x1A - 0x2C Reserved Registers
1
45
0x01
0x2D
Speaker Amplifier Control 1
1
46
0x01
0x2E
Speaker Volume Control Register
1
47
0x01
0x2F
Reserved Register
1
48
0x01
0x30
Speaker Amplifier Volume Control 2
1
49 - 62
0x01
0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register
1
64 - 121
0x01
0x40 - 0x79
Reserved Registers
1
122
0x01
0x7A
Reference Power Up Delay
1
123 - 127
0x01
0x7B - 0x7F Reserved Registers
2 - 43
0 - 127
0x02 - 0x2B 0x00 - 0x7F Reserved Registers
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02 - 0x07
Reserved
44
8 - 127
0x2C
0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)
45 - 52
0
0x2D-0x34
0x00
Page Select Register
45 - 52
1-7
0x2D-0x34
0x01 - 0x07
Reserved.
45 - 52
8 - 127
0x2D-0x34
0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
Table 7-3. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
53 - 61
0 - 127
0x35 - 0x3D 0x00 - 0x7F Reserved Registers
62 - 70
0
0x3E-0x46
0x00
Page Select Register
62 - 70
1-7
0x3E-0x46
0x01 - 0x07
Reserved Registers
62 - 70
8 - 127
0x3E-0x46
0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)
71 - 255
0 - 127
0x47 - 0x7F 0x00 - 0x7F Reserved Registers
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
21
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TAS2505 is a digital or analog input Class-D audio power amplifier. Below are shown different setups that
show the features of the TAS2505.
8.2 Typical Applications
8.2.1 Typical Configuration
+1.8VA
SVDD
IOVDD
22PF
2.7k
0.1PF
0.1PF
22PF
2.7k
AVSS
AVDD
LDO_SEL
SPKVSS SPKVDD
GPIO/DOUT
HOST PROCESSOR
SDA/MOSI
SCL/SSZ
8-: or
4-:
Speaker
MCLK
SPKP
SPKM
TAS2505
WCLK
DIN
BCLK
Headphone jack
RST
HPOUT
0.1PF
47PF
AINL
AINR
Analog Input
0.1PF
MISO
SCLK
SPI_SEL
DVDD DVSS
+1.8VD
0.1PF
IOVDD
IOVSS
IOVDD
10PF
0.1PF
10PF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Typical Circuit Configuration
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
8.2.1.1 Design Requirements
Table 8-1 shows the design parameters.
Table 8-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Audio input
Digital Audio (I2S), Analog Audio AINx
Speaker
8-Ω or 4-Ω
8.2.1.2 Detailed Design Procedure
In this application, the device is able to use both digital and analog inputs, working in mono output by summing
left and right analog inputs and output from DAC and routing this signal into the speaker output.
External 1.8-V supply is used to power AVDD and DVDD. IOVDD can be supplied by voltages between 1.1 V
and 3.6 V which lets the system to use conventional 1.8-V or 3.3-V supplies. The SPKVDD can be connected to
voltages between 2.7 V and 5.5 V, although it is usually supplied by a 5-V voltage.
Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1-µF, 10-µF, and 22-µF
capacitors for a better system performance.
Decoupling series capacitors must be used at the analog input.
All grounds are tied together; route analog and digital paths are separated to avoid interference.
8.2.1.3 Application Curves
100
10.00
THDN (%)
10
THDN (%)
100.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
Gain = 24 dB
1
1.00
SPKVDD=2.7V
Series1
SPKVDD=3V
Series2
0.1
SPKVDD=3.3V
Series4
0.10
SPKVDD=3.6V
Series5
SPKVDD=4.2V
Series6
0.01
SPKVDD=5.5V
Series7
0.01
0
0.5
1
1.5
Output Power (W)
2
2.5
3
0
1
1.5
Output Power (W)
C003
(SPKVDD = 5.5 V)
0.5
2
2.5
3
C004
(Gain = 18 dB)
Figure 8-2. Total Harmonic Distortion + Noise vs
4-Ω Speaker Power
Figure 8-3. Total Harmonic Distortion + Noise vs
4-Ω Speaker Power
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
23
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
0
±10
±20
THDN (%)
±30
±40
±50
CM=0.75V,AVDD=1.5V
±60
CM=0.75V,AVDD=1.8V
CM=0.75V,AVDD=1.95V
±70
CM=0.9V,AVDD=1.8V
±80
CM=0.9V,AVDD=1.95V
±90
0.0
5.0
10.0
15.0
20.0
25.0
30.0
Output Power (mW)
35.0
40.0
C010
(Gain = 9 dB)
Figure 8-4. Total Harmonic Distortion + Noise vs HP Power
9 Power Supply Recommendations
The TAS2505 integrates a large amount of digital and analog functionality, and each of these blocks can be
powered separately to enable the system to select appropriate power supplies for desired performance and
power consumption. The device has separate power domains for digital IO, digital core, analog core, analog
input and speaker drivers. If desired, all of the supplies (except for the supplies for speaker drivers, which can
directly connect to the battery) can be connected together and be supplied from one source in the range of 1.65
to 1.95 V. Individually, the IOVDD voltage can be supplied in the range of 1.1 V to 3.6 V. For improved power
efficiency, the digital core power supply can range from 1.26 V to 1.95 V. The AVDD pin can directly be driven
with a voltage in the range of 1.5 V to 1.95 V. The speaker driver voltages (SPKVDD) can range from 2.7 V to
5.5 V.
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
www.ti.com
TAS2505
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
25
TAS2505
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
www.ti.com
10 Layout
10.1 Layout Guidelines
•
•
•
If the analog input, AINR and AINL, are:
– Used, analog input traces must be routed symmetrically for true differential performance.
– Used, do not run analog input traces parallel to digital lines.
– Used, they must be AC-coupled.
– Not used, they must be shorted together.
Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for
minimum ground noise.
Use supply decoupling capacitors.
10.2 Layout Example
Figure 10-1. Layout Diagram
26
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
TAS2505
www.ti.com
SLAS778C – FEBRUARY 2013 – REVISED SEPTEMBER 2021
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TAS2505 Application Reference Guide (SLAU472)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
11.4 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TAS2505
27
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TAS2505IRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TAS
2505
TAS2505IRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TAS
2505
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
