TAS2521
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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Digital Input Class-D Speaker Amplifier with Embedded miniDSP and mono headphone
amplifier
Check for Samples: TAS2521
1 INTRODUCTION
1.1
Features
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Digital Input Mono Speaker Amp
Instruction-Programmable Embedded miniDSP
Supports 8-kHz to 192-kHz Sample Rates
Mono Class-D BTL Speaker Driver (2 W Into
4 Ω or 1.7 W Into 8 Ω)
Mono Headphone Driver
Two Single-Ended Inputs With Output Mixing
and Level Control
Embedded Power-on-Reset
Integrated LDO
Built-in Digital Audio Processing Blocks With
User-Programmable Biquad Filters
Integrated PLL Used for Programmable Digital
Audio Processor
I2S, Left-Justified, Right-Justified, DSP, and
TDM Audio Interfaces
I2C and SPI control with auto-increment
Full Power-Down Control
Power Supplies:
– Analog: 1.5 V–1.95 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
– Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)
24-Pin QFN Package (4mm × 4mm)
1.2
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•
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Applications
Portable Audio Devices
White goods
Portable Navigation Devices
1.3
Description
The TAS2521 is a low power digital input speaker
amp with support for 24-bit digital I2S data mono
playback.
In addition to driving a speaker amp upto 4-Ω, the
device also features a mono headphone driver and a
fully programmable miniDSP for signal processing.
The digital audio data format is programmable to
work with popular audio standard protocols (I2S,
left/right-justified) in master, slave, DSP and TDM
modes. The fully programmable miniDSP can support
several functions such equalization for audio, multiband DRC, tone generation and several other user
defined functions. An on-chip PLL provides the highspeed clock needed by the digital signal-processing
block. The volume level can be controlled by register
control. The audio functions are controlled using the
I2C™ serial bus or SPI bus. The device includes an
on-board LDO that runs off the speaker power supply
to handle all internal device analog and digital power
needs. The included POR as power-on-resetcircuit
reliably resets the device into its default state so no
external reset is required at normal usage; however,
the device does have a reset pin for more complex
system initialization needs. The device also includes
two analog inputs for mixing and muxing in both
speaker and headphone analog paths.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TAS2521
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AINR
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
AINL
DAC Signal
Proc.
Mono 6
' DAC
Dig
Vol
6 dB to +24 dB
(6 dB steps)
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
SPKP
6
SPKM
-6 dB to +29 dB
and Mute
(1 dB steps)
miniDSP
6
HPOUT
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
Data
Interface
POR
LDO
LDO_SEL
SPKVDD
RST
SPI/I2C
Control Block
Secondary I2S
Interface
AVDD
Primary I2S
Interface
PLL
Interrupt
Control
Supplies
SPI_SEL
Pin Muxing / Clock Routing
DVDD
IOVDD
SPKVSS
AVSS
MCLK
BCLK
DIN
WCLK
GPIO/DOUT
MISO
SDA/MOSI
SCLK
SCL/SSZ
DVSS
Figure 1-1. Simplified Block Diagram
NOTE
This data manual is designed using PDF document-viewing features that allow quick access
to information. For example, performing a global search on "page 0 / register 27" produces
all references to this page and register in a list. This makes is easy to traverse the list and
find all information related to a page and register. Note that the search string must be of the
indicated format. Also, this document includes document hyperlinks to allow the user to
quickly find a document reference. To come back to the original page, click the green left
arrow near the PDF page number at the bottom of the file. The hot-key for this function is altleft arrow on the keyboard. Another way to find information quickly is to use the PDF
bookmarks.
2
INTRODUCTION
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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1
Package/Ordering Information
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
TAS2521
QFN-24
RGE
–40°C to 85°C
2.2
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
TAS2521IRGET
Tape and reel, 250
TAS2521IRGER
Tape and reel, 3000
Device Information
DVSS
DVDD
IOVDD
SCLK
SDA/MOSI
SCL/SSZ
RGE PACKAGE
(TOP VIEW)
24
23 22
21
20
19
18
GPIO/DOUT
MISO
AINL
3
16
MCLK
AINR
4
15
BCLK
HPOUT
5
14
WCLK
AVSS
6
8
9
10
11
DIN
13
12
SPKP
7
SPKVSS
17
SPKVDD
2
SPKM
RST
LDO_SEL
1
AVDD
SPI_SEL
Table 2-1. RGE PIN FUNCTIONS
PIN
NAME
NO.
I/O (1)
DESCRIPTION
SPI_SEL
1
I
Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
RST
2
I
Reset for logic, state machines, and digital filters; asserted LOW.
AINL
3
I
Analog single-ended line left input
AINR
4
I
Analog single-ended line right input
HPOUT
5
O
Headphone and Lineout Driver Output
AVSS
6
GND
Analog Ground, 0V
AVDD
7
PWR
Analog Core Supply Voltage, 1.5V - 1.95V, tied internally to the LDO output
LDO_SEL
8
I
Select Pin for LDO; ties to either SPKVDD or SPKVSS
Class-D speaker driver inverting output
SPKM
9
O
SPKVDD
10
PWR
Class-D speaker driver power supply
SPKVSS
11
PWR
Class-D speaker driver power supply ground supply
SPKP
12
O
Class-D speaker driver non-inverting output
DIN
13
I
Audio Serial Data Bus Input Data
WCLK
14
I/O
Audio Serial Data Bus Word Clock
BCLK
15
I/O
Audio Serial Data Bus Bit Clock
MCLK
16
I
(1)
Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
PACKAGE AND SIGNAL DESCRIPTIONS
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Table 2-1. RGE PIN FUNCTIONS (continued)
PIN
I/O (1)
DESCRIPTION
NAME
NO.
MISO
17
O
GPIO/DOUT
18
I/O/Z
SCL/SSZ
19
I
Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
SDA/MOSI
20
I
Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
SCLK
21
I
Serial clock for SPI interface
IOVDD
22
PWR
I/O Power Supply, 1.1V - 3.6V
DVDD
23
PWR
Digital Power Supply, 1.65V - 1.95V
DVSS
24
GND
Digital Ground, 0V
SPI Serial Data Output
GPIO / Audio Serial Bus Output
3 ELECTRICAL SPECIFICATIONS
3.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
MAX
AVDD to AVSS
–0.3
2.2
V
DVDD to DVSS
–0.3
2.2
V
SPKVDD to SPKVSS
–0.3
6
V
IOVDD to IOVSS
–0.3
3.9
V
Digital input voltage
IOVSS – 0.3
IOVDD + 0.3
V
Analog input voltage
AVSS – 0.3
AVDD + 0.3
V
Operating temperature range
–40
85
°C
Storage temperature range
–55
150
°C
105
°C
(TJ Max – TA) / θJA
W
Junction temperature (TJ Max)
QFN
(1)
Power dissipation(with thermal pad soldered to board)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2
THERMAL INFORMATION
THERMAL METRIC (1)
TAS2521
RGE (24 PINS)
θJA
Junction-to-ambient thermal resistance
32.2
θJCtop
Junction-to-case (top) thermal resistance
30.0
θJB
Junction-to-board thermal resistance
9.2
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
9.2
θJCbot
Junction-to-case (bottom) thermal resistance
2.2
(1)
4
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
ELECTRICAL SPECIFICATIONS
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3.3
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
AVDD (1)
Power-supply voltage range
DVDD
SPKVDD
Referenced to AVSS (2)
Referenced to DVSS (2)
(1)
Referenced to SPKVSS
IOVDD
MIN
NOM
MAX
1.5
1.8
1.95
1.65
1.8
1.95
2.7
(2)
Referenced to IOVSS (2)
1.1
5.5
1.8
UNIT
V
3.6
4
Ω
16
Ω
Speaker impedance
Load applied across class-D output pins (BTL)
Headphone impedance
AC-coupled to RL
Analog audio full-scale input
voltage
AVDD = 1.8 V, single-ended
0.5
VRMS
Line output load impedance
(in half drive ability mode)
AC-coupled to RL
10
kΩ
MCLK (3)
Master clock frequency
IOVDD = DVDD = 1.8V
SCL
SCL clock frequency
TA
Operating free-air temperature
VI
(1)
(2)
(3)
–40
50
MHz
400
kHz
85
°C
To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
3.4
Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
8.48
MHz
0.5
Vrms
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.9V, DOSR = 128, Device Setup MCLK = 256* fs,
Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
Device Setup
Full-scale output voltage (0 dB)
(1) (2)
ICN
Idle channel noise
Measured as idle-channel noise, A-weighted
20.7
μVms
THD+N
Total harmonic distortion + noise
0-dBFS input, 1-kHz input signal
-78.2
dB
Mute attenuation
Mute
103.7
dB
Ripple on AVDD (1.8 V) = 200 mVPP at 1 kHz
47.2
dB
–60dB 1kHz input full-scale signal
88.1
0dB, 1kHz input full scale signal
±0.3
(3)
PSRR
Power-supply rejection ratio
DR
Dynamic range, A-weighted (1)
(2)
Gain error
PO
(1)
(2)
(3)
Maximum output power
RL = 32 Ω, THD+N ≤ –40 dB
11
RL = 16 Ω, THD+N ≤ –40 dB
18
dB
mW
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆VHP / ∆VAVDD).
ELECTRICAL SPECIFICATIONS
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.75V, DOSR = 128, Device Setup MCLK = 256*
fs, Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
Device Setup
Full-scale output voltage (0 dB)
0.375
Vrms
18.1
μVms
0-dBFS input, 1-kHz input signal
-78.2
dB
Mute
105.5
dB
Ripple on AVDD (1.8 V) = 200 mVPP at 1 kHz
48.4
dB
–60dB 1kHz input full-scale signal
86.8
0dB, 1kHz input full scale signal
±0.3
ICN
Idle channel noise
Measured as idle-channel noise, A-weighted (1)
THD+N
Total harmonic distortion + noise
Mute attenuation
PSRR
Power-supply rejection ratio (3)
DR
Dynamic range, A-weighted (1)
(2)
Gain error
PO
Maximum output power
(2)
RL = 32 Ω, THD+N ≤ –40 dB
8
RL = 16 Ω, THD+N ≤ –40 dB
16
dB
mW
DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS
See for DAC interpolation filter characteristics.
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL)
Idle channel noise
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted (1) (2)
37
μVms
Output voltage
BTL measurement, class-D gain = 6 dB, -3dBFS
input
1.4
Vrms
THD+N
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
PSRR
Power-supply rejection ratio
BTL measurement, ripple on SPKVDD = 200 mVPP
at 1 kHz
Mute attenuation
ICN
PO
Maximum output power
–73.9
dB
55
dB
Mute
103
dB
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1.1
SPKVDD = 4.2 V, BTL measurement, CM = 0.9 V,
class-D gain = 18 dB, THD = 10%
1.4
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
1.1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB
(1)
(2)
(3)
6
W
2
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆VHP / ∆VAVDD).
ELECTRICAL SPECIFICATIONS
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL)
ICN
THD+N
PO
Idle channel noise
BTL measurement, class-D gain = 6 dB, Measured
as idle-channel noise, A-weighted (1) (2)
Output voltage
BTL measurement, class-D gain = 6 dB, -3dBFS
input
Total harmonic distortion + noise
BTL measurement, DAC input = –6 dBFS, class-D
gain = 6 dB
–73.6
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
0.7
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 10%
1.7
SPKVDD = 3.6 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.5
SPKVDD = 4.2 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
0.8
SPKVDD = 5.5 V, BTL measurement, CM = 0.9V,
class-D gain = 18 dB, THD = 1%
1.3
Maximum output power
35.2
μVms
1.4
Vrms
dB
W
ANALOG BYPASS TO HEADPHONE AMPLIFIER
Device Setup
AC-COUPLED LOAD = 16 Ω (SINGLE-ENDED),
DRIVER GAIN = 0 dB, Input and output commonmode = 0.9 V, input signal frequency fi = 1kHz
Voltage Gain
Input common-mode = 0.9 V
1
V/V
Gain Error
-1dBFS (446mVrms), 1-kHz input signal
±0.8
dB
ICN
Idle channel noise
Idle channel, IN1L and IN1R ac-shorted to ground,
Measured as idle-channel noise, A-weighted (1) (2)
10.2
μVms
THD+N
Total harmonic distortion + noise
-1 dBFS (446mVrms), 1-kHz input signal
-80.4
dB
(1)
(2)
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
ELECTRICAL SPECIFICATIONS
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Electrical Characteristics (continued)
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS,
PLL = Off
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO CLASS-D SPEAKER AMPLIFIER
Device Setup
BTL measurement, DRIVER GAIN = 6 dB, LOAD
= 4 Ω (DIFFERENTIAL), 50 pF, input signal
frequency fi = 1 KHz
Voltage Gain
Input common-mode = 0.9 V
Gain Error
ICN
THD+N
4
V/V
-1dBFS (446mVrms), 1-kHz input signal
±0.7
dB
Idle channel noise
Idle channel, IN1L and IN1R ac-shorted to ground,
Measured as idle-channel noise, A-weighted (1) (2)
32.6
μVms
Total harmonic distortion + noise
-1 dBFS (446mVrms), 1-kHz input signal
-73.7
dB
SPKVDD = 2.7V, Page 1, Reg 2, D5-D4 = 00, IO =
50mA
1.79
V
SPKVDD = 3.6V, Page 1, Reg 2, D5-D4 = 00, IO =
50mA
1.79
V
SPKVDD = 5.5V, Page 1, Reg 2, D5-D4 = 00, IO =
50mA
1.79
V
LOW DROPOUT REGULATOR (AVDD)
AVDD Output Voltage 1.8V
Output Voltage Accuracy
SPVDD = 2.7V
Load Regulation
SPVDD = 2.7V, 0A to 50mA
Line Regulation
Input Supply Range 2.7V to 5.5V
Decoupling Capacitor
±2
%
7
mV
0.6
mV
55
uA
1.0
uF
Bias Current
Noise @0A Load
A-weighted, 20Hz to 20kHz bandwidth
166
uV
Noise @50mA Load
A-weighted, 20Hz to 20kHz bandwidth
174
uV
I(AVDD)
1.32
µA
I(DVDD)
0.04
µA
I(IOVDD)
0.68
µA
I(SPKVDD)
2.24
µA
SHUTDOWN POWER CONSUMPTION
Device Setup
Power down POR, /RST held low, AVDD = 1.8V,
IOVDD = 1.8 V, SPKVDD = 4.2 V, DVDD = 1.8 V
DIGITAL INPUT/OUTPUT
Logic family
VIH
VIL
Logic level
CMOS
IIH = 5 μA, IOVDD ≥ 1.6 V
0.7 ×
IOVDD
IIH = 5 μA, IOVDD < 1.6 V
IOVDD
IIL = 5 μA, IOVDD ≥ 1.6 V
–0.3
V
0.3 ×
IOVDD
IIL = 5 μA, IOVDD < 1.6 V
VOH
IOH = 2 TTL loads
VOL
(1)
(2)
8
0.8 ×
IOVDD
V
IOL = 2 TTL loads
Capacitive load
V
0
0.25
10
V
pF
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
ELECTRICAL SPECIFICATIONS
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3.5
3.5.1
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Timing Characteristics
I2S/LJF/RJF Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
tr
td(WS)
BCLK
tf
tS(DI)
th(DI)
DIN
T0145-10
PARAMETER
td(WS)
ts(DI)
th(DI)
tr
tf
IOVDD = 1.8 V
MIN
MAX
45
8
8
25
25
WCLK delay
DIN setup
DIN hold
Rise time
Fall time
IOVDD = 3.3 V
MIN
MAX
45
6
6
10
10
UNIT
ns
ns
ns
ns
ns
Figure 3-1. I2S/LJF/RJF Timing in Master Mode
ELECTRICAL SPECIFICATIONS
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I2S/LJF/RJF Timing in Slave Mode
3.5.2
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
tr
th(WS)
tS(WS)
tH(BCLK)
BCLK
tL(BCLK)
tf
tS(DI)
DIN
th(DI)
T0145-11
IOVDD = 1.8 V
MIN
MAX
35
35
8
8
8
8
4
4
PARAMETER
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
tf
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
DIN hold
Rise time
Fall time
IOVDD = 3.3 V
MIN
MAX
35
35
6
6
6
6
4
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Figure 3-2. I2S/LJF/RJF Timing in Slave Mode
10
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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
td(WS)
tf
BCLK
tr
tS(DI)
DIN
th(DI)
T0146-09
IOVDD = 1.8 V
MIN
MAX
45
8
8
25
25
PARAMETER
td(WS)
ts(DI)
th(DI)
tr
tf
WCLK delay
DIN setup
DIN hold
Rise time
Fall time
IOVDD = 3.3 V
MIN
MAX
45
6
6
10
10
UNIT
ns
ns
ns
ns
ns
Figure 3-3. DSP Timing in Master Mode
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DSP Timing in Slave Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
WCLK
tS(WS)
tS(WS)
th(WS)
th(WS)
tf
tL(BCLK)
BCLK
tr
tS(DI)
tH(BCLK)
DIN
th(DI)
T0146-10
IOVDD = 1.8V
MIN
MAX
35
35
8
8
8
8
4
4
PARAMETER
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
tf
BCLK high period
BCLK low period
WCLK setup
WCLK hold
DIN setup
DIN hold
Rise time
Fall time
IOVDD = 3.3 V
MIN
MAX
35
35
8
8
8
8
4
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Figure 3-4. DSP Timing in Slave Mode
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3.5.5
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I2C Interface Timing
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
SDA
tBUF
tLOW
tr
tHIGH
tf
tHD;STA
SCL
tHD;STA
tSU;DAT
tHD;DAT
STO
tSU;STO
tSU;STA
STA
STA
STO
T0295-02
PARAMETER
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Cb
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START
condition
Data hold time: For I2C bus devices
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Set-up time for STOP condition
Bus free time between a STOP and
START condition
Capacitive load for each bus line
Standard-Mode
MIN
TYP
0
MAX
100
Fast-Mode
MIN
TYP
0
UNITS
MAX
400
kHz
4
0.8
μs
4.7
4
1.3
0.6
μs
μs
4.7
0.8
μs
0
250
3.45
4
0
100
20 + 0.1 Cb
20 + 0.1 Cb
0.8
4.7
1.3
1000
300
400
0.9
300
300
μs
ns
ns
ns
μs
μs
400
pF
Figure 3-5. I2C Interface Timing
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SPI Interface Timing
SS
S
t
t Lead
t
t Lag
td
sck
SCLK
t sckl
tf
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
BIT 6 . . . 1
LSB OUT
ta
t hi
t su
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 3-6. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVDD = 1.8V
Table 3-1. SPI Interface Timing
PARAMETER
TEST CONDITION
IOVDD=1.8V
MIN
(1)
IOVDD=3.3V
TYP MAX
MIN
TYP
UNITS
MAX
tsck
SCLK Period
100
50
ns
tsckh
SCLK Pulse width High
50
25
ns
tsckl
SCLK Pulse width Low
50
25
ns
tlead
Enable Lead Time
30
20
ns
tlag
Enable Lag Time
30
20
ns
td
Sequential Transfer Delay
40
20
ta
Slave DOUT access time
tdis
Slave DOUT disable time
tsu
DIN data setup time
15
15
ns
thi
DIN data hold time
15
10
ns
tv;DOUT
DOUT data valid time
25
18
ns
tr
SCLK Rise Time
4
4
ns
tf
SCLK Fall Time
4
4
ns
(1)
14
40
40
ns
40
ns
40
ns
These parameters are based on characterization and are not tested in production.
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4 Typical Performance
4.1
Class D Speaker Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude (dB)
Amlitude (dB)
20
±60
±80
±100
±80
±100
±120
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
16000
Frequency (Hz)
20000
100
0
8000
12000
16000
20000
Frequency (Hz)
C002
Figure 4-2. AINL To Speaker FFT Amplitude at 0 dBFS vs
Frequency (4 Ω Load)
100.00
Gain = 6 dB
Gain = 12 dB
Gain = 18 dB
Gain = 24 dB
10.00
THDN (%)
10
4000
C001
Figure 4-1. DAC To Speaker Amplitude at 0 dBFS vs Frequency (4
Ω Load)
THDN (%)
±60
1
1.00
SPKVDD=2.7V
Series1
SPKVDD=3V
Series2
0.1
SPKVDD=3.3V
Series4
0.10
SPKVDD=3.6V
Series5
SPKVDD=4.2V
Series6
0.01
SPKVDD=5.5V
Series7
0.01
0
0.5
1
1.5
2
2.5
Output Power (W)
3
Figure 4-3. Total Harmonic Distortion + Noise vs 4 Ω Speaker
Power (SPKVDD = 5.5 V)
100.00
0
0.5
1
1.5
2
2.5
Output Power (W)
C003
3
C004
Figure 4-4. Total Harmonic Distortion + Noise + NOISE vs 4 Ω
Speaker Power (Gain = 18 dB)
100
Gain
= 6 dB
Series1
Gain
= 12 dB
Series2
Gain
= 18 dB
Series4
10.00
10
THDN (%)
THDN (%)
Gain
= 24 dB
Series5
1.00
1
SPKVDD
= 2.7 V
Series1
SPKVDD
=3V
Series2
0.10
0.1
SPKVDD
= 3.3 V
Series4
SPKVDD
= 3.6 V
Series5
SPKVDD
= 4.2 V
Series6
0.01
SPKVDD
= 5.5 V
Series7
0.01
0
0.5
1
1.5
Output Power (W)
2
2.5
0
1
1.5
2
Output Power (W)
C005
Figure 4-5. Total Harmonic Distortion + Noise + NOISE vs 8 Ω
Speaker Power (SPKVDD = 5.5 V)
0.5
2.5
C006
Figure 4-6. Total Harmonic Distortion + Noise + NOISE vs 8 Ω
Speaker Power (Gain = 18 dB)
Typical Performance
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90
80
Efficiency (%)
70
60
50
40
SPKVDD = 2.7 V
SPKVDD = 3 V
SPKVDD = 3.3 V
SPKVDD = 3.6 V
SPKVDD = 4.2 V
SPKVDD = 5.5 V
30
20
10
0
0
200
400
600
800
1000 1200 1400 1600 1800
Output Power (mWatt)
C007
Figure 4-7. Total Power Consumption vs Output Power Consumption (Gain = 18 dB, Load = 4 Ω)
16
Typical Performance
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4.2
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
HP Driver Performance
20
0
0
±20
±20
±40
±40
Amplitude ( dB)
Amplitude ( dB)
20
±60
0dBFS
±80
±100
±120
±60
±100
±120
±140
±140
±160
±160
±180
±180
0
4000
8000
12000
16000
20000
Frequency (Hz)
0
±10
±20
±20
±30
±30
THDN (dB)
±10
±50
CM=0.75V,AVDD=1.5V
±60
CM=0.75V,AVDD=1.8V
12000
±40
CM=0.75V,
Series4
AVDD=1.95V
±70
CM=0.9V,
Series5
AVDD=1.8V
±80
CM=0.9V,
Series6
AVDD=1.95V
CM=0.9V,AVDD=1.95V
±90
C008
CM=0.75V,
Series2
AVDD=1.8V
CM=0.9V,AVDD=1.8V
±80
20000
CM=0.75V,
Series1
AVDD=1.5V
±50
±60
CM=0.75V,AVDD=1.95V
16000
Figure 4-9. AINL TO HP FFT Amplitude at 0 dBFS vs Frequency
(16 Ω Load)
0
±40
8000
Frequency (Hz)
0
±70
4000
C008
Figure 4-8. DAC TO HP FFT Amplitude at 0 dBFS vs Frequency
(16 Ω Load)
THDN (%)
0dBFS
±80
±90
0.0
5.0
10.0
15.0
20.0
25.0
Output Power (mW)
30.0
35.0
40.0
0.0
Figure 4-10. Total Harmonic Distortion + Noise vs HP Power
(Gain = 9 dB)
5.0
10.0
15.0
20.0
Output Power (mW)
C010
25.0
C011
Figure 4-11. Total Harmonic Distortion + Noise vs HP Power
(Gain = 32 dB)
Typical Performance
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5 Application Overview
The TAS2521 offers a wide range of configuration options. Figure 1-1 shows the simplified functional
blocks of the device.
5.1
Typical Circuit Configuration
+1.8VA
SVDD
IOVDD
22PF
2.7k
0.1PF
0.1PF
22PF
2.7k
AVSS
AVDD
LDO_SEL
SPKVSS SPKVDD
GPIO/DOUT
HOST PROCESSOR
SDA/MOSI
SCL/SSZ
8-: or
4-:
Speaker
MCLK
SPKP
SPKM
TAS2521
WCLK
DIN
BCLK
Headphone jack
RST
HPOUT
0.1PF
47PF
AINL
AINR
Analog Input
0.1PF
MISO
SCLK
SPI_SEL
DVDD DVSS
+1.8VD
0.1PF
IOVDD
IOVSS
IOVDD
10PF
0.1PF
10PF
Figure 5-1. Typical Circuit Configuration
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5.2
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Circuit Configuration with Internal LDO
SVDD
IOVDD
22PF
2.7k
0.1PF
10PF
0.1PF
0.1PF
22PF
2.7k
AVSS
AVDD DVSS
DVDD
LDO_SEL SPKVSS SPKVDD
GPIO/DOUT
HOST PROCESSOR
SDA/MOSI
SCL/SSZ
8-: or
4-:
Speaker
MCLK
WCLK
DIN
SPKP
SPKM
TAS2521
BCLK
RST
HPOUT
0.1PF
47PF
AINL
AINR
Analog Input
0.1PF
MISO
SCLK
SPI_SEL
IOVDD
IOVSS
IOVDD
0.1PF
10PF
Figure 5-2. Application Schematics for LDO
5.3
5.3.1
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending
on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C
or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 5.3.3.
5.3.2
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
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Multifunction Pins
Table 5-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 5-1. Multifunction Pin Assignments
Pin Function
A
PLL Input
B
Codec Clock Input
C
2
3
4
5
6
7
BCLK
WCLK
DIN
GPIO
/DOUT
SCLK
MISO
S (1)
S (2)
(1)
S ,D
(4)
S
S ,D
2
E (5)
I S BCLK output
2
E
I S WCLK input
F
I2S WCLK output
G
I2S DIN
S (3)
E
(2)
2
I S BCLK input
D
1
MCLK
S (3)
(2)
E, D
E
E, D
2
H
I S DOUT
E
I
General Purpose Output I
E
I
General Purpose Output II
J
General Purpose Input I
J
General Purpose Input II
J
General Purpose Input III
K
INT1 output
E
L
INT2 output
E
M
Secondary I2S BCLK input
E
E
N
Secondary I2S WCLK input
E
E
E
E
E
E
E
2
E
E
O
Secondary I S DIN
E
P
Secondary I2S BCLK OUT
E
E
Q
Secondary I2S WCLK OUT
E
E
2
R
Secondary I S DOUT
S
Aux Clock Output
(1)
(2)
(3)
(4)
(5)
5.4
E
E
E
S(1):
S(2):
(3)
The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S : The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
Audio Analog I/O
The TAS2521 features a mono audio DAC. It supports a wide range of analog interfaces to support
different headsets such as 16-Ω to 200-Ω impedance and analog line outputs. TheTAS2521 can drive a
speaker upto 4-Ω impedance.
5.5
Analog Signals
The TAS2521 analog signals consist of:
• Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output
stages
• Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the
DAC, AINR, AINL, or a mix of the three
20
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5.5.1
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Analog Inputs AINL and AINR
AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output.
Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for
determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be
attenuated by Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of
HP driver can be attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural
differential input with use Mixer P and Mixer M by Page1 / register 12 setting.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6
Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is
between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated
within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include
mono headphone and lineout and mono class-D speaker outputs. Because the TAS2521 contains a mono
DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right
channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.1
DAC
The TAS2521 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the
mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP,
a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The
DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and
observed in the signal images strongly suppressed within the audio band to beyond 20 kHz. To handle
multiple input rates and optimize power dissipation and performance, the TAS2521 allows the system
designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0,
register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower
input data rates and lower oversampling ratios for higher input data rates.
The TAS2521 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on
required frequency response, group delay, and sampling rate.
The DAC path of the TAS2521 features many options for signal conditioning and signal routing:
• Digital volume control with a range of -63.5 to +24dB
• Mute function
In addition to the standard set of DAC features the TAS2521 also offers the following special features:
• Digital auto mute
• Adaptive filter mode
5.6.1.1
DAC Processing Blocks — Overview
The TAS2521 implements signal-processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they
may use and which interpolation filter is applied.
The choices among these processing blocks allows the system designer to balance power conservation
and signal-processing flexibility. Table 5-2 gives an overview of all available processing blocks of the DAC
channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (AVDD) may differ.
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The signal-processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.
Table 5-2. Overview – DAC Predefined Processing Blocks
Processing
Block No.
Interpolation Filter
Channel
First-Order
IIR Available
Number of
Biquads
Resource
Class
PRB_P1
A
Mono
Yes
6
6
PRB_P2
A
Mono
No
3
4
PRB_P3
B
Mono
Yes
6
4
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.2
Digital Mixing and Routing
The TAS2521 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the
digital audio data. The first mixer/multiplexer can be used to select input data for the mono DAC from left
channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by
writing to page 0, register 63, bits D5–D4.
5.6.3
Analog Audio Routing
The TAS2521 has the capability to route the DAC output to either the headphone or the speaker output. If
desirable, both output drivers can be operated at the same time while playing at different volume levels.
The TAS2521 provides various digital routing capabilities, allowing digital mixing or even channel
swapping in the digital domain. All analog outputs other than the selected ones can be powered down for
optimal power consumption.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.4
5V LDO
The TAS2521 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply
(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is
50 mA or less, then this LDO can deliver power to both analog and digital power supplies. If the only
speaker power supply is present and LDO Select pin is enabled, the LDO can power up without requiring
other supplies. This LDO requires a minimum dropout voltage of 300 mV and can support load currents up
to 50 mA. For stability reasons the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the
analog supply (AVDD) pin and the digital supply (DVDD) pin. If use this LDO output voltage for the digital
supply (DVDD) pin, the analog supply (AVDD) pin connected to the digital supply (DVDD) externally is
required.
The LDO is by default powered down for low sleep mode currents and can be enabled driving the
LDO_SELECT pin to SPKVDD (Speaker power supply). When the LDO is disabled the AVDD pin is tristated and the device AVDD needs to be powered using external supply. In that case the DVDD pin is
also tri-stated and the device DVDD needs to be powered using external supply. The output voltage of this
LDO can be adjusted to a few different values as given in the Table 5-3.
22
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Table 5-3. AVDD LDO Settings
Page-1, Register 2, D(5:4)
LDO Output
00
1.8 V
01
1.6 V
10
1.7 V
00
1.5 V
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.5
POR
TAS2521 has a POR (Power On Reset) function. This function insures that all registers are automatically
set to defaults when a proper power up sequence is executed.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.6
CLOCK Generation and PLL
The TAS2521 supports a wide range of options for generating clocks for the DAC sections as well as
interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can
be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference
clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits
D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in to
generate the various clocks required for the DAC and the miniDSP section. In the event that the desired
audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2521 also
provides the option of using the on-chip PLL which supports a wide range of fractional multiplication
values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2521 provides several
programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the
miniDSP sections.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7
Digital Audio and Control Interface
5.6.7.1
Digital Audio Interface
Audio data is transferred between the host processor and the TAS2521 via the digital audio data serial
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data
options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for
multichannel operation, flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TAS2521 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently
configured in either master or slave mode for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC
sampling frequencies.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.2
Control Interface
The TAS2521 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. It is
not recommended to change the state of SPI_SEL during device operation.
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5.6.7.2.1 I2C Control Mode
The TAS2521 supports the I2C control protocol, and will respond to the I2C address of 0011 000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is
driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously,
there is no driver contention.
5.6.7.2.2 SPI Digital Interface
In the SPI control mode,the TAS2521 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI
control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host
processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor)
generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices
(such as the TAS2521) depend on a master to start and synchronize transmissions. A transmission begins
when initiated by an SPI master.The byte from the SPI master begins shifting in on the slave MOSI pin
under the control of the master serial clock(driven onto SCLK). As the byte shifts in on the MOSI pin, a
byte shifts out on the MISO pin to the master shif tregister.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.3
Power Supply
The TAS2521 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance
and power consumption. The device has separate power domains for digital IO, digital core, analog core,
analog input, headphone driver, and speaker drivers. If desired, all of the supplies (except for the supplies
for speaker drivers, which can directly connect to the battery) can be connected together and be supplied
from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied in the
range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core supply can either be derived from the internal LDO accepting an SPKVDD
voltage in the range of 2.7V to 5.5V, or the AVDD pin can directly be driven with a voltage in the range of
1.5V to 1.95V. The speaker driver voltages (SPKVDD) can range from 2.7V to 5.5V.
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.4
•
•
Device Special Functions
Interrupt generation
Flexible pin multiplexing
For more detailed information see the TAS2521 Application Reference Guide (SLAU456).
5.6.7.5
miniDSP
The TAS2521 features a miniDSP core which is tightly coupled to the DAC. The fully programmable
algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access
to the digital audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The
miniDSP has 512 programmable instructions, 896 data memory locations, and 512 programmable
coefficients (in the adaptive mode, each bank has 256 programmable coefficients).
24
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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
5.6.7.5.1 Software
Software development for the TAS2521 is supported through TI's comprehensive PurePath™ Studio
software development environment, a powerful, easy-to-use tool designed specifically to simplify software
development on Texas Instruments miniDSP audio platforms. The graphical development environment
consists of a library of common audio functions that can be dragged and dropped into an audio signal flow
and graphically connected together. The DSP code can then be assembled from the graphical signal flow
with the click of a mouse. See the TAS2521 product folder on www.ti.com to learn more about PurePath
Studio and the latest status on available, ready-to-use DSP algorithms.
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6 Register Map
6.1
Register Map Summary
Table 6-1. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2-3
0x00
0x02 - 0x03
Reserved Registers
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P and R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9 - 10
0x00
0x09 - 0x0A Reserved Registers
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15
0x00
0x0F
miniDSP_D Instruction Control Register 1
0
16
0x00
0x10
miniDSP_D Instruction Control Register 2
0
17
0x00
0x11
miniDSP_D Interpolation Factor Setting Register
0
18 - 24
0x00
0x12 - 0x18
Reserved Registers
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Reserved Register
0
35 - 36
0x00
0x23 - 0x24
Reserved Registers
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Registers
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Reserved Register
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Reserved Register
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Registers
0
52
0x00
0x34
GPIO/DOUT Control Register
0
53
0x00
0x35
DOUT Function Control Register
26
Register Map
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SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Table 6-1. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
54
0x00
0x36
DIN Function Control Register
0
55
0x00
0x37
MISO Function Control Register
0
56
0x00
0x38
SCLK/DMDIN2 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Instruction Set
0
61
0x00
0x3D
Reserved Registers
0
62
0x00
0x3E
miniDSP_D Configuration Register
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
DAC Channel Digital Volume Control Register
0
66 - 80
0x00
0x42 - 0x50
Reserved Registers
0
81
0x00
0x51
Dig_Mic Control Register
0
82 - 127
0x00
0x52 - 0x7F Reserved Registers
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
REF, POR and LDO BGAP Control Register
1
2
0x01
0x02
LDO Control Register
1
3
0x01
0x03
Playback Configuration Register 1
1
4-7
0x01
0x04 - 0x07
Reserved Registers
1
8
0x01
0x08
DAC PGA Control Register
1
9
0x01
0x09
Output Drivers, AINL, AINR, Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
HP Over Current Protection Configuration Register
1
12
0x01
0x0C
HP Routing Selection Register
1
13 - 15
0x01
0x0D - 0x0F Reserved Registers
1
16
0x01
0x10
HP Driver Gain Setting Register
1
17 - 19
0x01
0x11 - 0x13
HPR Driver Gain Setting Register
1
20
0x01
0x14
Headphone Driver Startup Control Register
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
HP Volume Control Register
1
23
0x01
0x17
Reserved Register
1
24
0x01
0x18
AINL Volume Control Register
1
25
0x01
0x19
AINR Volume Control Register
1
26 - 44
0x01
0x1A - 0x2C Reserved Registers
1
45
0x01
0x2D
Speaker Amplifier Control 1
1
46
0x01
0x2E
Speaker Volume Control Register
1
47
0x01
0x2F
Reserved Register
1
48
0x01
0x30
Speaker Amplifier Volume Control 2
1
49 - 62
0x01
0x31 - 0x3E Right MICPGA Positive Terminal Input Routing Configuration Register
1
64 - 121
0x01
0x40 - 0x79
Reserved Registers
1
122
0x01
0x7A
Reference Power Up Delay
1
123 - 127
0x01
0x7B - 0x7F Reserved Registers
2 - 43
0 - 127
0x02 - 0x2B 0x00 - 0x7F Reserved Registers
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02 - 0x07
Reserved
44
8 - 127
0x2C
0x08 - 0x7F DAC Coefficients Buffer-A C(0:29)
Register Map
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Table 6-1. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
45 - 52
0
0x2D-0x34
0x00
Page Select Register
45 - 52
1-7
0x2D-0x34
0x01 - 0x07
Reserved.
45 - 52
8 - 127
0x2D-0x34
0x08 - 0x7F DAC Coefficients Buffer-A C(30:255)
53 - 61
0 - 127
0x35 - 0x3D 0x00 - 0x7F Reserved Registers
62 - 70
0
0x3E-0x46
0x00
Page Select Register
62 - 70
1-7
0x3E-0x46
0x01 - 0x07
Reserved Registers
62 - 70
8 - 127
0x3E-0x46
0x08 - 0x7F DAC Coefficients Buffer-B C(0:255)
71 - 151
0 - 127
0x47 - 0x97
0x00 - 0x7F Reserved Registers
152 - 169
0
0x98-0xA9
0x00
Page Select Register
152 - 169
1-7
0x98-0xA9
0x01 - 0x07
Reserved Registers
152 - 169
8 - 127
0x98-0xA9
0x08 - 0x7F miniDSP_D Instructions
170 - 255
0 - 127
0xAA - 0x7F 0x00 - 0x7F Reserved Registers
spacer
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2013) to Revision A
•
•
28
Page
Deleted PO (Max Output power) SPKVDD = 5.5 V, THD = 10% .............................................................. 6
Changed PO (Max Output power) SPKVDD = 5.5 V value From: TYP = 2.1 W To: MAX = 2 W ......................... 6
Register Map
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TAS2521IRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TAS
2521
TAS2521IRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TAS
2521
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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