TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
www.ti.com
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
1 Introduction
1.1 Features
•
•
•
•
•
•
•
•
•
•
•
•
8 channel Programmable Audio Digital Signal
Processor (DSP)
135-MHz Maximum Speed, >2800 Processing
Cycles Per Sample at 48 kHz
Sample Rates of 32 kHz to 192 kHz
48-Bit Data Path and 28-Bit Coefficients
Single-Cycle, 76-Bit Multiply Accumulate
Five Simultaneous Operations Per Clock Cycle
1022 Words of 48-Bit Data Memory
1022 Words of 28-Bit Coefficient Memory
3K Words of 54-Bit Program RAM
5.88K Words of 24-Bit Delay Memory
(122.5 ms at 48 kHz)
15 Stereo/TDM Data Formats
Independent Input/Output Data Formats
•
•
•
•
•
•
•
•
•
16-, 20-, 24-, and 32-Bit Word Sizes
64-fS, 128-fS, 192-fS, and 256-fS SCLK to
Support Discrete 4 channel TDM, 6 channel
TDM, and 8 channel TDM Data-Transfer
Formats
Two I2C Ports for Slave or Master Download
Soft Volume Controller
Dither Generator
Efficient log2/2x Estimator
Single 3.3-V Power Supply
38-Pin Thin Shrink Small-Outline Package
(TSSOP) (DCP)
AEC-Q100 (Grade 2: –40°C to 105°C)
Compliant for Automotive Applications
(TAS3108IA)
1.2 Applications
•
•
•
•
Automotive Sound Systems
Digital Televisions
Home Theater Systems
Mini-Component Audio
TAS3108/TAS3108IA
SDIN1
SDIN2
SDIN3
SDIN4
MCLK
LRCLK
SCLKIN
SCLKOUT1
SCLKOUT2
Serial
Audio
Input
Port
PLL
and
Clock
Control
Audio DSP Core
8
8
48-Bit Data Path
28-Bit Coefficients
76-Bit MAC
Serial
Audio
Output
Port
SDOUT1
SDOUT2
SDOUT3
SDOUT4
3K Code RAM
1K Data RAM
1K Coeff. RAM
5.8K Delay RAM
Boot ROM
Volume
Update
8051 MCU
I2C Port #1
I2C Port #2
I2C
Interface
8-Bit Microprocessor
256 IRAM
2K ERAM
12K Code RAM
B0074-01
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
www.ti.com
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
Contents
1
2
3
Introduction ............................................... 1
Features .............................................. 1
7.1
Clock Control Register (0x00)
1.2
Applications ........................................... 1
7.2
7.3
Status Register (0x02) .............................. 41
I2C Memory Load Control and Data Registers (0x04
and 0x05) ............................................ 42
7.4
Memory Access Registers (0x06 and 0x07)
Functional Description
3
Device Description .................................... 3
2.2
Power Supply ......................................... 4
2.3
Clock Control ......................................... 4
2.4
Serial Audio Ports (SAPs) ............................ 4
2.5
M8051Warp Microprocessor.......................... 4
2.6
I2C Control Interface .................................. 4
2.7
Audio DSP Core ...................................... 5
...............................
Terminal Assignments ................................
Terminal Descriptions ................................
Reset (RESET) .......................................
Power-On Reset (RESET)............................
Power Down (PDN) ...................................
I2C Bus Control (CS0) ................................
Programmable General Purpose I/O (GPIO) .........
Input and Output Serial Audio Ports ..................
8
......................
........
38
43
Electrical Specifications .............................. 44
8.1
8.2
8.3
Absolute Maximum Ratings Over Operating
Temperature Range (unless otherwise noted) ...... 44
Package Dissipation Ratings
(TAS3108/TAS3108IA) .............................. 44
Recommended Operating Conditions
(TAS3108/TAS3108IA) .............................. 44
Physical Characteristics
6
3.1
6
8.4
Electrical Characteristics (TAS3108/TAS3108IA) ... 45
7
8.5
Timing Characteristics............................... 46
7
8.5.1
8.5.2
9
Master Clock Signals (TAS3108/TAS3108IA) .....
Serial Audio Port Slave Mode Signals
(TAS3108/TAS3108IA) ..............................
8.5.3 Serial Audio Port Master Mode Signals
(TAS3108/TAS3108IA) ..............................
8.5.4 Pin-Related Characteristics of the SDA and SCL
I/O Stages for F/S-Mode I 2C-Bus Devices ..........
Algorithm and Software Development Tools for
TAS3108/TAS3108IA ................................... 18
Clock Controls .......................................... 19
Microprocessor Controller .......................... 27
..............
Application Information ...............................
9.1
Schematics ..........................................
9.2
Recommended Oscillator Circuit ....................
3.4
3.5
3.6
3.7
3.8
6.1
6.2
6.3
2
.................................
2.1
3.3
5
6
I2C Register Map ........................................ 37
1.1
3.2
4
7
.............................
2
Detailed I C Operation ..............................
I2C Master-Mode Device Initialization ..............
General I2C Operations
Contents
8
8
8
8
28
29
8.5.6 Reset Timing (TAS3108/TAS3108IA)
9
9.3
46
47
48
49
51
53
53
55
Recommended PCB Design for TAS3108IA
Applications ......................................... 55
31
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2 Functional Description
2.1 Device Description
The TAS3108 and TAS3108IA are fully programmable high-performance audio processors. The devices
use an efficient, custom, multi-instruction programming environment optimized for digital audio processing
algorithms. The TAS3108/TAS3108IA architecture provides high-quality audio processing by using a 48-bit
data path, 28-bit filter coefficients, and a single-cycle 28 × 48-bit multiplier with a 76-bit accumulator. An
embedded 8051 microprocessor provides algorithm and data control for the TAS3108/TAS3108IA. The
TAS3108 is the commercial version intended for home audio and other commercial applications. The
TAS3108IA is the automotive version that is qualified for use in automotive applications.
Audio DSP Core
28
8 Channels
SDIN1
Coef.
RAM
(1022 y 28)
SDIN2
SDIN3
SDIN4
Serial
Audio
Port
Data
Path
48
SDOUT1
Data
RAM
(1022 y 48)
SDOUT2
SDOUT3
8 Channels
SDOUT4
48
MCLK
Memory
Interface
LRCLK
SCLKIN
Clock
Control
Controller
Code
RAM
(3K y 54)
54
SCLKOUT1
SCLKOUT2
Microprocessor Core
Internal
Data RAM
(256 y 8)
External
Data RAM
(2048 y 8)
Code
RAM
(12K y 8)
Delay
Memory
(5.8K y 24)
8
8-Bit
MCU
(8051)
8
Control
Registers
Volume
Update
2ySDA
8
I2C
Control
Interface
2ySCL
CSO
GPIO
Code
ROM
Power Supply
AVDD
DVDD
B0075-01
Figure 2-1. Expanded TAS3108/TAS3108IA Functional Block Diagram
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2.2 Power Supply
The power supply contains supply regulators that provide analog and digital regulated power for various
sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are
generated on-chip from the external 3.3-V supply.
2.3 Clock Control
The TAS3108/TAS3108IA can be an audio data clock-master or clock-slave device. In clock-master mode,
it generates MCLK, SCLK, and LRCLK. In clock-slave mode, it accepts MCLK, SCLK, and LRCLK. It can
generate or accept master clocks from 6 MHz to 24.576 MHz. Master or slave operation is set via I2C
register 0x00. The TAS3108/TAS3108IA can use a 6-MHz to 20-MHz crystal or a 6-MHz to 24.576-MHz,
3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave
mode, the master clock frequency does not need to be an integer multiple of the sample rate.
The TAS3108/TAS3108IA does not support clock error detection. If a clock error occurs, the
TAS3108/TAS3108IA does not prevent invalid data or clocks from being output. This means that the
application system must be designed to handle clock errors.
2.4 Serial Audio Ports (SAPs)
Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins
SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-,
96-, 176.4-, or 192-kHz serial data as 16-, 20-, 24-, or 32-bit data in left justified, right justified, or I2S serial
data formats. All four ports accommodate these three 2 channel data formats.
In addition to supporting the 2 channel formats, SDIN1 and SDOUT1 also provide support for time-division
multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I2C register 0x00.
All input channels must use the same data format. All output channels must use the same data format.
However, the input and output formats can be different.
2.5 M8051Warp Microprocessor
The M8051Warp (8051) microprocessor controls I2C reads and writes and participates in some audio
processing tasks requiring multiframe (fS period) processing cycles. The 8051 processor performs some
control calculations and exchanges data between the audio DSP core and the I2C interface. It also
provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin
for post-boot-up operation to be an input or an output. For more information, see the TAS3108/TAS3108IA
Firmware Programmer's Guide (SLEU067).
2.6 I2C Control Interface
The TAS3108/TAS3108IA has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and
providing status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to
download programs and data from external memory such as an EEPROM. See Section 6 for more
information.
4
Functional Description
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2.7 Audio DSP Core
The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit
and data and coefficient memory blocks. The primary features of the audio DSP core are:
• 48-bit data path with 76-bit accumulator
• Hardware multiplier (28 bit × 48bit)
• Read/write single-cycle memory access
• Input is 48-bit 2s-complement data multiplexed in from the SAP immediately following an LRCLK pulse.
• Output is 32-bit 2s-complement data on four buses.
• Separate control for writing to delay memory
• Separate coefficient memory (28 bit) and data memory (48 bit)
• Linear feedback shift register (LFSR) is a random-number generator that can be used to dither the
audio.
• Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into
the same 5.88K memory space for convenient addressing by the microprocessor.
• Memory interface block contains four pointers – two for data memory and two for coefficient memory.
The audio DSP core is used to implement all audio processing functions.
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3 Physical Characteristics
3.1 Terminal Assignments
DCP PACKAGE
(TOP VIEW)
AVSS
VR_PLL
XTALI
XTALO
MCLKI
MICROCLK_DIV
CS0
GPIO
DVDD
DVSS
SDIN1
SDIN2
SDIN3
SDIN4
SDA1
SCL1
SDA2
SCL2
LRCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
AVDD
RESERVED
PLL2
PLL1
PLL0
RESERVED
RESET
PDN
DVDD
DVSS
VR_DIG
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SCLKOUT2
SCLKOUT1
MCLKO
SCLKIN
P0033-01
6
Physical Characteristics
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3.2 Terminal Descriptions
TERMINAL
NAME
NO.
INPUT/
OUTPUT (1)
AVDD
38
I
AVSS
1
CS0
7
I
DVDD
9, 30
I
DVSS
10, 29
PULLUP/
PULLDOWN (2)
DESCRIPTION
Analog power supply (3.3 V)
Analog ground
Pulldown
Chip select
Digital power supply input (3.3 V)
Digital ground
GPIO
8
I/O
Pullup
LRCLK
19
I/O
Pulldown
MCLKIN
5
I
GPIO control (user programmable)
Sample rate clock (fS)
Master clock input (connect to ground when not in use)
MCLKO
21
O
MICROCLK_DIV
6
I
Pulldown
PDN
31
I
Pullup
Power down. Powers down all logic and stops all clocks, active low.
Coefficient memory remains stable through the power-down cycle.
PLL0
34
I
Pullup
PLL control 0
PLL1
35
I
Pulldown
PLL control 1
PLL2
36
I
Pullup
PLL control 2
RESERVED
33, 37
RESET
32
I
Pullup
Reset, active low
SCL1
16
I/O
I2C port 1 clock (always a slave)
SCL2
18
I/O
I2C port 2 clock (always a master)
SCLKIN
20
I
SCLKOUT1
22
O
Bit clock 1 out. Used to receive input serial data.
(1)
(2)
Master clock output
Internal microprocessor clock divide control
Reserved. Connect to ground
Pulldown
Bit clock input
SCLKOUT2
23
O
Bit clock 2 out. Used to clock output serial data.
SDA1
15
I/O
I2C port 1 data (always a slave)
SDA2
17
I/O
I2C port 2 data (always a master)
SDIN1
11
I
Pulldown
Serial data input 1
SDIN2
12
I
Pulldown
Serial data input 2
SDIN3
13
I
Pulldown
Serial data input 3
SDIN4
14
I
Pulldown
Serial data input 4
SDOUT1
27
O
Serial data output 1
SDOUT2
26
O
Serial data output 2
SDOUT3
25
O
Serial data output 3
SDOUT4
24
O
Serial data output 4
VR_PLL
2
XTALI
3
O
Oscillator input (connect to ground when not in use)
XTALO
4
O
Oscillator output
VR_DIG
28
Internal regulator. This pin must not be used to power external devices.
Internal regulator. This pin must not be used to power external devices.
I = input, O = output
All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
3.3 Reset (RESET)
The RESET pin is an asynchronous control signal that restores all TAS3108/TAS3108IA components to
the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051
starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a
device reset. A reset can be initiated by applying a logic 0 on RESET. A reset can also be issued at power
turnon by the three internal power supplies.
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As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus
operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain
in that state until device initialization has completed.
The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and
setting the default register values. Once these are complete, the TAS3108/TAS3108IA enables its master
I2C interface and disables its slave I2C interface.
Then the TAS3108/TAS3108IA looks for an EEPROM as described in Section 2.6, I 2C Control Interface.
3.4 Power-On Reset (RESET)
On power up, it is recommended that the TAS3108/TAS3108IA RESET be held LOW until DVDD has
reached 3.3 V. This can be done by programming the system controller or by using an external RC delay
circuit. The 1-kΩ and 1-µF values provide a delay of approximately 200 µs. The values of R and C can be
adjusted to provide other delay values as necessary.
3.5 Power Down (PDN)
PDN is a user-firmware-definable pin that is programmed in the default TAS3108 and TAS3108IA
configuration to stop all clocks in the TAS3108/TAS3108IA, while preserving the state of the device. For
more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
3.6
I2C Bus Control (CS0)
The TAS3108/TAS3108IA has a control to specify the slave and master I2C address. This control permits
up to two TAS3108/TAS3108IA devices to be placed in a system without external logic.
See Section 6.2 for a complete description of this pin.
3.7
Programmable General Purpose I/O (GPIO)
The TAS3108/TAS3108IA has one GPIO pin that is 8051 firmware programmable.
On power up or following a reset, the GPIO pin becomes an input. Afterwards, the microprocessor can
program the GPIO as an input or an output.
For more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
3.7.1
No EEPROM is Present or a Memory Error Occurs
Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the
TAS3108/TAS3108IA is in one of two modes, depending on the setting of the GPIO pin.
• GPIO pin is logic HIGH (through a 20-kΩ resistor)
With the GPIO pin held HIGH during initialization, the TAS3108/TAS3108IA comes up in the default
configuration with the serial data outputs not active. Once the TAS3108/TAS3108IA has completed
the default initialization procedure and after the status register is updated and the I2C slave
interface is enabled, the GPIO pin is an output and is driven LOW. Following the HIGH-to-LOW
transition of the GPIO pin, the system controller can access the TAS3108/TAS3108IA through the
I2C interface and read the status register to determine the load status.
If a memory-read error occurs, the TAS3108/TAS3108IA reports the error in the status register (I2C
subaddress 0x02).
• GPIO pin is logic LOW (through a 20-kΩ resistor)
With GPIO pin held LOW during initialization, the TAS3108/TAS3108IA comes up in an I/O test
configuration. In this case, once the TAS3108/TAS3108IA completes its default test initialization
procedure, the status register is updated, the I2C slave interface is enabled, and the
TAS3108/TAS3108IA streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to
SDOUT2, etc.
In this configuration, the GPIO pin is an output signal that is driven LOW. If the external logic is no
8
Physical Characteristics
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longer driving the GPIO pin low after the load has completed (~100 ms following a reset if no EEPROM
is present), the state of the GPIO pin can be observed.
Then the system controller can access the TAS3108/TAS3108IA through the I2C interface and read the
status register to determine the load status.
If the GPIO pin state is not observed, the only indication that the device has completed its initialization
procedure is that the TAS3108/TAS3108IA streams audio and the I2C slave interface has been enabled.
3.7.2
GPIO Pin Function After Device Is Programmed
Once the TAS3108/TAS3108IA has been programmed, either through a successful boot load or via slave
I2C download, the operation of GPIO can be programmed to be an input and/or output.
3.8 Input and Output Serial Audio Ports
The TAS3108/TAS3108IA supports system architectures that require data format conversions between
TDM and non-TDM of the same format type without the need for additional glue logic. In addition, the
TAS3108/TAS3108IA supports data format conversions between right justified and I2S and between left
justified and I2S. All the supported conversions are listed in Table 3-1. If the input port is configured for a
TDM format, only SDIN1 is active. If a TDM format is selected for the output port, only SDOUT1 is active.
Table 3-1. Supported Conversions
INPUT SAP
(SDIN1, SDIN2, SDIN3, SDIN4)
OUTPUT SAP
(SDOUT1, SDOUT2, SDOUT3, SDOUT4)
2 channel left justified
TDM left justified
2 channel left justified
2 channel I2S
TDM left justified
2 channel left justified
2 channel I2S
TDM I2S
2
2 channel I2S
TDM I S
2
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2 channel I S
2 channel leftjustified
2 channel I2S
2 channel right justified
2 channel right justified
2 channel I2S
Physical Characteristics
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Table 3-2. Serial Data Input and Output Formats
MODE
INPUT
CONTROL
IM[3:0]
0000
2 channel
0001
0010
Time-division
multiplexed (4,
6, or 8
channel)
OUTPUT
CONTROL
OM[3:0]
SERIAL FORMAT
WORD
LENGTHS
0000
Left justified
16, 20, 24, 32
0001
Right justified
16, 20, 24, 32
0010
I2S
16, 20, 24
0011
0011
8 channel left justified
16, 20, 24, 32
0110
0110
8 channel I2S
16, 20, 24
0100
0100
6 channel left justified
16, 20, 24, 32
2
0111
0111
6 channel I S
16, 20, 24
0101
0101
4 channel left justified
16, 20, 24, 32
1000
1000
4 channel I2S
16, 20, 24
DATA RATES
(kHz)
MAX
SCLK
32–192
12.288
32–96 MCLK
32–48 crystal
24.576 MCLK
12.288 crystal
32–96
18.432
32–192 MCLK
32–96 crystal
24.576 MCLK
12.288 crystal
Output Port
Word Size
Input Port
Word Size
Î
ÎÎ
Î
15
0x00
31
S
Slave Addr
Ack
Subaddr
Ack
24
xxxxxxxx
23
Ack
14 13
XX
16
xxxxxxxx
11 10
15
Ack
8
IW[2:0] OW[2:0] DWFMT (Data Word Format)
7
8
DWFMT
Ack
7
4
0
IOM
Ack
3
0
IM[3:0]
OM[3:0]
Input Port
Format
Output Port
Format
R0003-01
Figure 3-1. Serial Data Controls
Table 3-3. Serial Data Input and Output Data Word
Sizes
10
Physical Characteristics
IW1, OW1
IW0, OW0
FORMAT
0
0
32-bit data
0
1
16-bit data
1
0
20-bit data
1
1
24-bit data
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Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3108/TAS3108IA should not be commanded to unmute
until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration
change while a volume or bass or treble update is taking place can cause the update not to be completed
properly.
When the TAS3108/TAS3108IA is transmitting serial data, it uses the negative edge of SCLK to output a
new data bit. The TAS3108/TAS3108IA samples incoming serial data on the rising edge of SCLK. The
TAS3108/TAS3108IA only supports TDM, left justified, right justified, and I2S formats.
2 channel I 2S Timing
3.8.1
In 2 channel I2S timing, LRCLK is LOW when left channel data is transmitted and HIGH when right
channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the data.
There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on
the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3108/TAS3108IA masks unused trailing data-bit positions.
2-Channel I2S (Philips Format) Stereo Input/Output
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-04
Figure 3-2. I2S 64-fS Format
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3.8.2
2 Channel Left Justified Timing
In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when
right channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the
data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written
MSB first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing
data-bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
Figure 3-3. Left justified 64-fS Format
12
Physical Characteristics
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3.8.3
2 Channel Right Justified Timing
In 2-channel right-justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when
right channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the
data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK
toggles. In the right-justified mode, the last bit clock before LRCLK transitions always clocks the LSB of
data. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3108/TAS3108IA masks unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 3-4. Right justified 64-fS Format
3.8.4
TDM Modes
The TDM modes on the TAS3108/TAS3108IA provide left justified and I2S formats. Each word in the TDM
data stream adheres to the bit placement shown in Figure 3-5 and Figure 3-6. Two cases are
illustrated—an I2S data format and a left-justified data format.
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128 Clks
128 Clks
Left Channels
Right Channels
LRCLK
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
32-Bit Word (DAC7)
32-Bit Word (DAC2)
32-Bit Word (DAC4)
96 Clks
96 Clks
Left Channels
Right Channels
32-Bit Word (DAC6)
32-Bit Word (DAC8)
LRCLK
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC5)
64 Clks
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
64 Clks
LRCLK
LRCLK
Right Channels
Left Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
32-Bit Word (DAC2)
1-Chip, 8-, 6-, 4-Channel
and Multiplexed 6-Channel Operation
32-Bit Word (DAC4)
Left-Justified Format
SCLK
LRCLK
MSB
32-Bit Mode
31 30 29
LSB
17 16
13 12
9
8
24-Bit Mode
23 22 21
1
0
SCLK
9
8
5
4
1
3
2
1
0
31 30 29 28
32 Bit
23 22 21 20
(Example)
0
24 Bit
20-Bit Mode
19 18 17
5
4
1
0
1
0
16-Bit Mode
15 14 13
T0085-01
Figure 3-5. Left-Justified TDM Formats
14
Physical Characteristics
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128 Clks
128 Clks
LRCLK
Left Channels
32-Bit Word (DAC1)
32-Bit Word (DAC3)
Right Channels
32-Bit Word (DAC5)
32-Bit Word (DAC7)
96 Clks
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
32-Bit Word (DAC8)
96 Clks
LRCLK
Left Channels
32-Bit Word (DAC1)
Right Channels
32-Bit Word (DAC3)
32-Bit Word (DAC5)
64 Clks
32-Bit Word (DAC2)
32-Bit Word (DAC4)
32-Bit Word (DAC6)
64 Clks
LRCLK
LRCLK
Left Channels
32-Bit Word (DAC1)
Right Channels
32-Bit Word (DAC3)
32-Bit Word (DAC2)
1-Chip, 8-, 6-, 4-Channel
and Multiplexed 6-Channel Operation
32-Bit Word (DAC4)
I2S Format
SCLK
LRCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
1
SCLK
0
20-Bit Mode
19 18
5
4
1
0
1
23 22 21
24 Bit
(Example)
0
16-Bit Mode
15 14
T0085-02
2
Figure 3-6. I S TDM Formats
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3.8.5
SAP Input to SAP Output—Processing Flow
All SAP data format options other than I2S result in a two-sample delay from input to output, as shown in
Figure 3-7. If I2S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK in
Figure 3-7 must be inverted. However, if I2S format conversions are performed between input and output,
the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock frequency
selected for the audio DSP core relative to the sample rate of the incoming data.
The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use
the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core
operate on sample windows that are 180° out of phase, with respect to the sample window used by the
output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the audio DSP core to process the data. If the processing cycle completes
all processing tasks before the midpoint of the processing sample period, the output SAP outputs this
processed data. However, if the processing time extends past the midpoint of the processing sample
period, the output SAP outputs the data processed during the previous processing sample period. In the
former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output
is 2.5 samples.
Therefore, delay from input to output can be either 1.5 or 2.5 sample times when data format conversions
are performed that involve the I2S format. However, which delay time is obtained for a particular
application is determinable and fixed for that application, providing care is taken in the selection of
MCLKI/XTALI with respect to the incoming sample clock, LRCLK.
16
Physical Characteristics
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SDIN4
SDIN3
SDIN2
SDIN1
SDIN4
SDIN3
SDIN2
SDIN1
G
E
C
A
Serial
Input
Rx
Holding
Regs
Regs
H
F
D
B
Input
Holding
Regs
H
F
D
B
Input
Holding
Regs
Sample Time N
G
E
C
A
Serial
Input
Rx
Holding
Regs
Regs
Sample Time N
SDOUT1
SDIN1
SDIN4
SDIN3
Sample Time N
G
E
C
A
H
F
D
B
Input
Mux
Channel 3
Channel 2
Channel 1
Output
Mux
Input
Mux
Channel 3
Channel 2
Channel 1
Output
Mux
Z
Y
X
W
V
SDOUT3
SDOUT2
SDIN4
SDIN3
SDIN2
G
E
C
A
Serial Input
Rx Holding
Regs
Regs
H
F
D
B
Input
Holding
Regs
Input
Mux
Channel 3
Channel 2
Channel 1
Output
Mux
Sample Time N + 1
Sample Time N + 2
SDOUT3
SDIN2
SDIN1
Input
Holding
Regs
Sample Time N + 1
Sample Time N + 2
U
Z
Y
X
SDOUT2
SDOUT1
Serial Input
Rx Holding
Regs
Regs
Sample Time N
Sample Time N + 1
Channel 3
Output
Mux
W
V
U
Sample Time N + 2
2nd Half − Sample Time N
Sample Time N + 1
Input
Mux
Channel 2
Channel 1
Sample Time N + 1
1st Half − Sample Time N
Z
Y
X
W
V
U
Z
Y
X
W
V
U
Sample Time N + 2
Sample Time N + 2
B0076-01
SDOUT3
SDOUT2
SDOUT1
SDOUT3
SDOUT2
SDOUT1
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Figure 3-7. SAP Input-to-Output Latency
Physical Characteristics
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4 Algorithm and Software Development Tools for TAS3108/TAS3108IA
The TAS3108/TAS3108IA algorithm and software development tool set is a combination of classical
development tools and graphical development tools. The tool set is used to build, debug, and execute
programs in both the audio DSP and 8051 sections of the TAS3108/TAS3108IA.
Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level
debuggers. The 8051 can be programmed exclusively in ANSI C.
The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051
tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator.
The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete
environment with an IDE, context-sensitive editor, assembler, and simulator/debugger.
Graphical development tooling provides a means of programming the audio DSP core and 8051 through a
graphical drag-and-drop interface using modular audio software components from a component library.
The graphical tooling produces audio DSP assembly and 8051 ANSI C code, as well as coefficients and
data. The classical tools can also be used to produce the executable code.
In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051
code on both simulators and EVM hardware.
18
Algorithm and Software Development Tools for TAS3108/TAS3108IA
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5 Clock Controls
Clock management for the TAS3108/TAS3108IA consists of two control structures:
• Master clock management
– Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and
the audio DSP core
– The master clock (MCLKI or XTALI) is the source for these clocks.
– In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the
DPLL output drives the microprocessor and audio DSP clocks.
– Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the
microprocessor and audio DSP clocks.
• Serial audio port (SAP) clock management
– Oversees SAP master/slave mode
– Controls output of SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode
Figure 5-2 shows the clock circuitry in the TAS3108/TAS3108IA. Input pin MCLKI or XTALI provides the
master clock for the TAS3108/TAS3108IA. Within the TAS3108/TAS3108IA, these two inputs are
combined by an OR gate and, thus, only one of these two sources can be active at any one time. The
source that is not active must be logic 0.
In normal operation, 1, 2, or 4 (as determined by the logic levels set at input pins PLL0 and PLL1) divides
the master clock. The DPLL then multiplies this signal by 11 in frequency (PLL2 = LOW). The multiplier
ratio is always 11 (pin PLL2 = LOW). The DPLL output is the processing clock used by the audio DSP
core.
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Table 5-1. PLL2, PLL1, and PLL0 Pin Configuration Controls
PLL2
PLL1
PLL0
AUDIO DSP CLOCK
0
0
0
11 × MCLK/1
0
0
1
11 × MCLK/2
0
1
0
11 × MCLK/4
0
1
1
Reserved
1
X
X
Reserved
Audio DSP clock or audio DSP clock/4 is used to clock the on-chip microprocessor. The input pin
MICROCLK_DIV makes this clock choice. A logic-1 input level on this pin selects the audio DSP clock for
the microprocessor clock; a logic-0 input level on this pin selects the audio DSP clock/4 for the
microprocessor clock. The microprocessor clock must be ≤ 34 MHz.
Table 5-2. MICROCLK_DIV Pin Configuration Control
MICROCLK_DIV
MICROPROCESSOR CLOCK
0
Audio DSP clock/4
1
Audio DSP clock
NOTE
The state of PLL0, PLL1, PLL2, and MICROCLK_DIV can only be changed while the
TAS3108 or TAS3108IA RESET pin is held low.
The TAS3108/TAS3108IA only supports dynamic sample-rate changes between any of the supported
sample frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate
changes, the TAS3108/TAS3108IA remains in normal operation and the register contents are preserved.
To avoid producing audio artifacts during the sample-rate changes, a volume or mute control can be
included in the application firmware that mutes the output signal during the sample-rate change. The
fixed-frequency clock can be provided by a crystal, attached to XTLI and XTLO, or an external 3.3-V
fixed-frequency TTL source attached to MCLKI.
When the TAS3108/TAS3108IA is used in a system in which the master clock frequency (fMCLK) can
change, the TAS3108/TAS3108IA must be reset during the frequency change. In these cases, the
procedure shown in Figure 5-1 should be used.
20
Clock Controls
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Enable Mute and
Wait for Completion
RESET Pin = Low
Change fMCLK
No
Are
Clocks
Stable?
Yes
RESET Pin = High
After
TAS3108/TAS3108IA
Initializes,
Re-initialize
I2C Registers
F0007-01
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure
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SCLKIN
MCLKI
XTALI
XTALO
MCLKO
÷2
PLL2
PLL1 PLL0
PLL
M
U
X
÷2
MCLK
÷ Z = 2DEFAULT
MICROCLK_DIV SCLKOUT2
M
U
X
OSC
÷2
SCLKOUT1 LRCLK
M
U
X
÷2
M
U
X
× 11
÷4
M
U
X
M
U
X
÷ X = 1DEFAULT
M
U
X
÷Y = 64DEFAULT
PLL and Clock Management
Input
SAP
Audio DSP Core
Output
SAP
Microprocessor
and
I2C Bus Controller
N = 0 (Default)
Oversample Clock
I2 C
Master/Slave
Controller
Master
SCL
÷10
1/2N
1/(M+1)
8-Bit
WARP
8051 Microprocessor
M = 8 (Default)
2xSDA
2xSCL
B0078-01
Figure 5-2. DPLL and Clock Management Block Diagram
22
Clock Controls
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PLL2
CRYSTAL
MCLKO
PLL1 PLL0
0
1
x 11
PLL
3
MUX
MICROPROCESSOR
CLOCK
1
÷2
2
÷4
Word Size Code
IW2/OW2 IW1/OW1 IW0/OW0
0
0
X
1
0
X
0
1
X
1
1
X
÷4
Word Size
32-bit
16-bit
20-bit
24-bit
MUX
÷2N
2
÷4
AB
MUX
N[2:0]
M[3:0]
IW[2:0] OW[2:0]
NOTE: Input and output word sizes are
independent.
0x00
S Slave Addr
22 21
23
31 29 28 27 26 24
0
32
6
8
11 10
15 14 13
0
IC
MODULE
0x01
2
Data Word Format (DWMFT)
2
1/(M+1)
÷2
1
I C SAMPLING
CLOCK N = 0
÷10
1
3
0
2
OSC
0
PLL [1:0]
DIGITAL AUDIO
PROCESSOR
CLOCK
XTALO
XTALI
MUX
SCL SDA
AB assigns TDM time slots for those
TDM outputs involving two TAS3108s. For
these output formats, one of the TAS3108
chips must be defined as AB = ‘0’. The
other TAS3108 chip must be defined as
AB = ‘1’.
MCLKI
1918 16
0
7
8
15
Ack Sub-Addr Ack 000 w[1:0] y[2:0] Ack ICS IMS x[2:0] z[2:0] Ack DWMFT Ack IOM Ack
2
I C MASTER
SCL M = 8
S Slave Addr Ack Sub-Addr Ack 00000000 Ack 00000000 Ack 00000000 Ack 0xxxxxxx Ack
0
÷32
0
1
÷64
1
÷2
2
÷128
2
÷3
3
÷192
3
÷4
4
÷256
4
÷6
5
÷384
6
÷512
7
÷32
MUX
0
1
MUX
SCLKOUT2
1
0
MUX
SCLKOUT1
5
1
0
÷8
6
÷16
7
÷32
MUX
OM[3:0]
IM[3:0]
1
÷2
2
÷3
3
÷4
4
÷6
5
÷8
6
÷16
7
÷32
MUX
MUX
SCLKIN
0
3
4
7
0
0 1000 010
Serial Audio Port (AP) Mode Code
Mode
IM3/OM3 IM2/OM2 IM1/OM1 IM0/OM0
Discrete, left justified
0
0
0
0
Discrete, right justified
1
0
0
0
0
0
0
Discrete, I2S
0
0
1
1
TDM_LJ_8
0
1
0
0
0
1
0
1
TDM_LJ_4
0
1
1
0
TDM_I2S_8
0
1
1
1
TDM_I2S_6
1
0
0
0
TDM_I2S_4
1
0
0
1
Discrete, I2S
1
0
1
0
Discrete, I2S
1
0
1
1
Discrete, I2S
1
1
0
0
Discrete, I2S
1
1
0
1
Discrete, I2S
1
1
1
0
Discrete, I2S
1
1
1
1
Discrete, I2S
1
TDM_LJ_6
Figure 5-3. Serial Data Format, Clock Management, and I2C M&N Assignments
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When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock
to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode,
LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 5-2,
SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct
clocks are required to support TDM-to-discrete and discrete-to-TDM data-format conversions. Such format
conversions also require that SCLKIN be the higher-valued bit-clock frequency. For TDM-in/discrete-out
format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/TDM-out format
conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1,
SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are
all controlled by I2C commands. Table 5-3 lists the default settings at power turnon or after a received
reset.
Table 5-3. TAS3108/TAS3108IA Clock Default Settings
CLOCK
DEFAULT SETTING
SCLKOUT1
SCLKIN
SCLKOUT2
SCLKIN
MCLKO
MCLKI or XTALI
LRCLK
Input
Audio DSP clock
Set by pins PLL0 and PLL1
Microprocessor clock
Set by pin MICROCLK_DIV
PLL multiply ratio
11
I2C sampling clock
N=0
I2C master SCL
M=8
The selections provided by the dedicated TAS3108/TAS3108IA input pins and the programmable settings
provided by I2C subaddress commands give the TAS3108/TAS3108IA a variety of clocking options.
However, the following clocking restrictions must be adhered to:
• MCLKI or XTALI ≥128 fS
NOTE
For some TDM modes, MCLKI or XTALI must be ≥256 fS
•
•
•
•
•
•
Audio DSP clock
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