TAS3204EVM

TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 AUDIO DSP WITH ANALOG INTERFACE Check for Samples: TAS3204 1 Introduction 1.1 Features • Digital Audio Processor – Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio™ Software Development Environment – 135-MHz Operation – 48-Bit Data Path With 76-Bit Accumulator – Hardware Single-Cycle Multiplier (28 × 48) – Five Simultaneous Operations Per Clock Cycle – Usable 768 Words Data RAM (48 Bit), Usable 1k Coefficient RAM (28 Bit) – Usable 2.5K Program RAM – 122 ms at 48 kHz, 5.8k Words 24-Bit Delay Memory – Slave Mode Fs is 44.1 kHz and 48 kHz – Master Mode Fs is 48 kHz • Analog Audio Input/Output – Two 3:1 Stereo Analog Input MUXes – Four Differential ADCs (102 dB DNR, Typical) – Four Differential DACs (105 dB DNR, Typical) • Digital Audio Input/Output – Two Synchronous Serial Audio Inputs (Four Channels) – Two Synchronous Serial Audio Outputs (Four Channels) – Input and Output Data Formats: 16-, 20-, or 24-Bit Data Left, Right, and I2S • System Control Processor – Embedded 8051 WARP Microprocessor – Programmable Using Standard 8051 C Compilers – Up to Four Programmable GPIO Pins • General Features – Two I2C Ports for Slave or Master Download – Single 3.3-V Power Supply – Integrated Regulators 12 1.2 • • • • • • Applications MP3 Player/Music Phone Docks Speaker Bars Mini/Micro-Component Systems Musical Instruments Speaker Equalization Studio Monitors 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Studio is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 1.3 www.ti.com Description The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio™ suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: 1. Clocking System 2. Digital Audio Interface 3. Analog Audio Interface 4. Power supply 5. Clocks, digital PLL 6. I2C control interface 7. 8051 MCUcontroller 8. Audio DSP – digital audio processing 2 Introduction Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 Expanded Functional Block Diagram 512Fs XTAL DPLL Oscillator 8051 Microprocessor Core Master Master/Slave External RAM 2K MCLK_IN 512Fs Internal RAM 256 Slave Control Registers Interface 8-Bit MCU SCL2/SDA2 GPIO1/2 Volume Update Code RAM 16K Clock SCL1/SDA1 I2C Control Divider LRCLK_IN Clock SCLK_IN Generation DSP Control LRCLK_OUT SCLK_OUT Data RAM Output Cross Bar Mixer Data Path 1K Upper Mem 768 Lower Mem Code RAM 3K 256Fs SDOUT1/2 DSP Core Coefficient RAM 1.2K Serial Audio Port Input Cross Bar Mixer SDIN1/2 Memory Interface 128Fs Two Stereo DAC Three Differential Stereo Legend Clocks Digital Data Analog Data (1) (2) Stereo Analog Outputs Two Stereo ADC Power Supply Analog Inputs 1.4 Two Differential AVDD DVDD Internal Connection External Connection Ordering Information TA PLASTIC 64-PIN PQFP (PN) (1) (2) 0°C to 70°C TAS3204PAG Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Introduction Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 3 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 1 2 3 4 5 6 7 8 9 www.ti.com .............................................. 1 1.1 Features .............................................. 1 1.2 Applications .......................................... 1 1.3 Description ........................................... 2 1.4 Ordering Information ................................. 3 Physical Characteristics ............................... 5 2.1 Terminal Assignments ............................... 5 2.2 Terminal Descriptions ................................ 6 TAS3204 Clocking System ............................ 8 3.1 Core Clock Management ............................ 8 3.2 SAP Clock Management ............................. 9 Digital Audio Interface ................................ 11 4.1 Serial Audio Port (SAP) ............................ 11 Analog Audio Interface ............................... 17 5.1 Analog to Digital Converters ADCs ................. 17 5.2 Digital to Analog Converters DACs ................. 17 5.3 Analog Reference System .......................... 17 Embedded MCUcontroller ........................... 18 6.1 MCU Addressing Modes ............................ 18 6.2 Boot Up Sequence ................................. 19 Digital Audio Processor .............................. 20 7.1 Audio Digital Signal Processor Core ............... 22 7.2 DAP Instructions Set ............................... 22 7.3 DAP Data Word Structure .......................... 23 I2C Control Interface .................................. 25 8.1 General I2C Operations ............................. 25 8.2 I2C Master Interface ................................ 26 8.3 I2C Slave Mode Operation .......................... 31 TAS3204 Control Pins ................................ 35 9.1 Reset (RESET) - Power-Up Sequence ............. 35 9.2 Voltage Regulator Enable (VREG_EN) ............ 35 9.3 Power Down (PDN) ................................. 35 9.4 I2C Bus Control (CS0) .............................. 36 9.5 Programmable I/O (GPIO) .......................... 36 Introduction 10 Algorithm and Software Development Tools for TAS3204 ................................................. 38 11 Electrical Specifications ............................. 39 Absolute Maximum Ratings 39 11.2 Package Dissipation Ratings 39 11.3 11.4 11.5 11.6 11.7 11.8 11.9 39 40 40 43 43 44 Serial Audio Port Master Mode Signals (TAS3204) ...................................................... 45 11.10 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices ......... 46 11.11 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices ......... 46 ...................................... ....................................... Clock Control Register (0x00) ...................... MCUcontroller Clock Control Register .............. Status Register (0x02) .............................. 11.12 Reset Timing 12 I2C Register Map 12.1 12.2 12.3 12.4 48 49 50 50 51 I2C Memory Load Control and Data Registers (0x04 and 0x05) ........................................... 52 ........ .............................. Analog Power Down Control (0x10 and 0x11) ..... Analog Input Control (0x12) ........................ Dynamic Element Matching (0x13) ................. 12.5 Memory Access Registers (0x06 and 0x07) 53 12.6 Device Version (0x08) 54 12.7 12.8 12.9 12.10 Current Control Select (0x14, 0x15, 0x17, 0x18) 12.11 12.12 12.13 12.14 ...................................................... DAC Control (0x1A, 0x1B, 0x1D) ................. ADC and DAC Reset (0x1E) ...................... ADC Input Gain Control (0x1F) ................... MCLK_OUT Divider (0x21 and 0x22) ............. Digital Cross Bar (0x30 to 0x3F) .................. 54 55 55 56 60 62 62 63 12.15 63 12.16 Extended Special Function Registers (ESFR) Map ...................................................... 65 .............................. Schematics ......................................... Recommended Oscillator Circuit ................... 13 Application Information 13.1 13.2 4 ........................ ....................... Recommended Operating Conditions .............. Electrical Characteristics ........................... Audio Specifications ................................ Timing Characteristics .............................. Master Clock ........................................ Serial Audio Port, Slave Mode ..................... 11.1 Contents 70 70 71 Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 2 Physical Characteristics TAS3204 SDIN1 SDIN2 Input SAP 4 2 Differential Analog In 2 Stereo 2 ADC 2 2 2 Stereo 2 ADC MCLK_IN LRCLK_IN SCLK_IN MCLK_OUTx LRCLK_OUT SCLK_OUT 3 I2C Port #1 I2C Port #2 2.1 PLL and Clock Control I2C Interface Digital Audio Processor Core 48-Bit Data Path 28-Bit Coefficients 76-Bit MAC 4 Output SAP 2 3K Code RAM 2 1K Upper Data RAM 768 Lower Data RAM 1.2K Coeff. RAM Boot ROM SDOUT1 SDOUT2 Stereo DAC 2 Stereo DAC 2 Differential Analog Out Volume Update 8051 MCU 8-Bit Microprocessor 256 IRAM 2K ERAM 16K Code RAM 10K Code ROM Terminal Assignments 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 I2C2_SCL I2C2_SDA RESET SDIN1/GPIO3 SDIN2/GPIO4 SCLK_IN LRCLK_IN DVDD3 DVSS3 VR_DIG SDO1 SDO2 SCLK_OUT LRCLK_OUT RESERVED VREG_EN PAG PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MCLK_OUT1 MCLK_OUT2 MCLK_OUT3 DVDD2 DVSS2 MCLK_IN XTAL_OUT XTAL_IN AVDD3 VR_ANA AVSS_ESD AVSSO AOUT1RP AOUT1RM AOUT1LP AOUT1LM AIN2LM AIN2RP AIN2RM AIN3LP AIN3LM AIN3RP AIN3RM AVDD1 VMID VREF REXT AVDD2 AOUT2LM AOUT2LP AOUT2RM AOUT2RP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I2C1_SCL I2C1_SDA GPIO2 GPIO1 MUTE CS0 PDN DVSS1 DVDD1 VR_PLL AVSSI AIN1LP AIN1LM AIN1RP AIN1RM AIN2LP Physical Characteristics Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 5 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 2.2 Terminal Descriptions TERMINAL (1) (2) (3) 6 www.ti.com NAME NO. INPUT/ OUTPUT (1) PULLUP/ PULLDOWN (2) AIN1LM 13 Analog Input Pull to VMID (3) AIN1LP 12 Analog Input AIN1RM 15 Analog Input AIN1RP 14 Analog Input AIN2LM 17 Analog Input AIN2LP 16 Analog Input AIN2RM 19 Analog Input AIN2RP 18 Analog Input AIN3LM 21 Analog Input DESCRIPTION Analog channel 1 left negative input Analog channel 1 left positive input Pull to VMID (3) Analog channel 1right negative input Analog channel 1 right positive input Pull to VMID (3) Analog channel 2 left negative input Analog channel 2 left positive input Pull to VMID (3) Analog channel 2 right negative input Analog channel 2 right positive input Pull to VMID (3) Analog channel 3 left negative input AIN3LP 20 Analog Input AIN3RM 23 Analog Input Analog channel 3 left positive input AIN3RP 22 Analog Input Analog channel 3 right positive input AOUT1LM 33 Analog Output Analog channel 1 left negative output Pull to VMID (3) Analog channel 3 right negative input AOUT1LP 34 Analog Output Analog channel 1 left positive output AOUT1RM 35 Analog Output Analog channel 1 right negative output AOUT1RP 36 Analog Output Analog channel 1 right positive output AOUT2LM 29 Analog Output Analog channel 2 left negative output AOUT2LP 30 Analog Output Analog channel 2 left positive output AOUT2RM 31 Analog Output Analog channel 2 right negative output AOUT2RP 32 Analog Output Analog channel 2 right positive output AVDBit 1 24 Power 3.3-V analog power. This pin must be decoupled according to good design practices. AVSS1 11 Power Analog ground AVDBit 2 28 Power 3.3-V analog power. This pin must be decoupled according to good design practices. AVSS2 37 Power Analog ground AVDBit 3 40 Power 3.3-V analog power supply. This pin must be decoupled according to good design practices. AVSS3 38 Power Analog ground CS0 6 Digital Input I2C chip select DVDBit 1 9 Power 3.3-V digital power. This pin must be decoupled according to good design practices. DVSS1 8 Power Digital ground DVDBit 2 45 Power 3.3-V digital power. This pin must be decoupled according to good design practices. DVSS2 44 Power Digital ground DVDBit 3 57 Power 3.3-V digital power. This pin must be decoupled according to good design practices. DVSS3 56 Power Digital ground GPIO1 4 Digital IO General purpose input/output pin #1. General purpose input/output pin #2 GPIO2 3 Digital IO I2C1_SCL 1 Digital Input I2C1_SDA 2 Digital I/O I2C2_SCL 64 Digital Input Slave I2C serial control data interface input/output. Slave I2C serial clock input. Master I2C serial control data interface input/output. I = input; O = output All pullups are 20-μA weak pullups, and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive inputs with pullups must be able to sink 20 μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 20 μA while maintaining a logic-1 drive level. Pull to VMID when analog input is in single-ended mode. Physical Characteristics Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 TERMINAL NAME NO. INPUT/ OUTPUT (1) I2C2_SDA 63 Digital I/O LRCLK_IN 58 Digital Input LRCLK_OUT 51 Digital Output MCLK_IN 43 Digital Input MCLK_OUT1 48 Digital Output Master clock output for I2S interface Frequency = 256 x Fs MCLK_OUT2 47 Digital Output Programmable master clock output divider MCLK_OUT3 46 Digital Output Programmable master clock output divider MUTE 5 Digital Input PDN 7 Digital Input RESERVED 50 N/A Pulldown RESET 62 Digital Input Pullup REXT 27 Analog Output SCLK_IN 59 Digital Input SCLK_OUT 52 Digital Output SDIN1/GPIO3 61 Digital I/O Pullup Serial data input #1 for I2S interface / general purpose input/output #3 SDIN2/GPIO4 60 Digital I/O Pullup Serial data input #2 for I2S interface / general purpose input/output #4 SDOUT1 54 Digital Output Serial data output #1 for I2S interface SDOUT2 53 Digital Output Serial data output #2 for I2S interface VMID 25 Analog Output Analog mid supply reference. This pin must be decoupled with a 0.1-μF low-ESR capacitor and an external 10-μF filter cap. (4) VR_ANA VR_DIG (4) 39 55 PULLUP/ PULLDOWN (2) DESCRIPTION Master I2C serial clock input. Pulldown Left/right (frame) clock input for I2S interface Left/right (frame) clock output for I2S interface Pulldown Pulldown Master clock input for I2S interface. Frequency = 512 x Fs This pin needs to be programmed as mute pin in the application code. In has no function in default after reset. Powerdown active LOW. After successful boot, its function is defined by the boot code. Pin must be connected to ground Device reset. This pin is active low. This pin must be connected to a 22 kΩ (1% tolerance) external resistor to ground to set analog currents. Trace capacitance must be kept low. Serial (bit) clock input for I2S interface Serial (bit) clock output for I2S interface Power Voltage reference for analog supply. A pin-out of the internally regulated 1.8 V power. A 0.1-μF low ESR capacitor and a 4.7-μF filter capacitor must be connected between this terminal and AVSS. This terminal must not be used to power external devices. (4) Power Voltage reference for digital supply. A pin-out of the internally regulated 1.8 V power. A 0.1-μF low ESR capacitor and a 4.7-μF filter capacitor must be connected between this terminal and DVSS. This terminal must not be used to power external devices. (4) VR_PLL 10 Power Voltage reference for DPLL supply. A pin-out of internally regulated 1.8-V power supply. A 0.1-μF low-ESR capacitor and a 4.7-μF filter capacitor must be connected between this terminal and DVSS. This terminal must not be used to power external devices. (4) VREF 26 Analog Output Band gap output. A 0.1-μF low ESR capacitor should be connected between this terminal and AVSS. This terminal must not be used to power external devices. (4) VREG_EN 49 Digital Input Voltage regulator enable active low. XTAL_IN 41 Digital Input Crystal input. Frequency = 512 x Fs XTAL_OUT 42 Digital Output Crystal output. Frequency = 512 x Fs If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provide an extended high frequency supply decoupling. Physical Characteristics Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 7 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 3 TAS3204 Clocking System Clock management for the TAS3204 consists of two control structures: • Core Clock management – Oversees the selection of the clock frequencies for the 8051 MCU, the I2C controller, and the audio DSP core – The master clock (MCLK_IN or XTAL_IN) is the source for these clocks. – In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the DPLL output drives the MCU and audio DSP clocks. – DPLL bypass mode is also available, in which the high-speed master clock directly drives the MCU and audio DSP clocks. • Serial Audio Port (SAP) clock management – Oversees SAP master/slave mode – Controls output of SCLKOUT, and LRCLK in the SAP master mode Figure 3-1 shows a block diagram of the TAS3204 clocking scheme. DPLL ×5.5 135-MHz DCLK Microprocessor Clock ÷4 MCLK_OUT ÷2 Programmable Divider MCLK_OUT2 Programmable Divider MCLK_OUT3 From DAP Parallel Data 24.576 MHz 512Fs Crystal MCLKI SDIN Oscillator ÷2 24.576 MHz 256Fs ÷2 128Fs ÷2 64Fs ÷64 LRCLK Re-Creation Serial Audio Port Transmitter Serial Audio Port Receiver SDOUT To DAP Parallel Data LRCLK_OUT SCLK_OUT Master/ Slave Figure 3-1. Clock Generation 3.1 Core Clock Management The TAS3204 DSP, MCU, and I2C Controller core clocks are derived from the on chip oscillator provided that an external crystal and associated circutry are provided. . • DSP clock operates at a fixed frequency of 2816 x Fs • MCU clock operates at a fixed frequency of 704 x Fs. • I2controller core operates at a fixed frequency of (256 x Fs). 8 TAS3204 Clocking System Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 3.2 SLES197C – APRIL 2007 – REVISED MARCH 2011 SAP Clock Management The Serial Audio Port in the TAS3204 can be clocked in two modes of operation: Master and Slave. By default, the TAS3204 is configured in master mode. Clock Master operation: In Clock Master operation, the onboard oscillator provides the reference for the SAP clock outputs provided an external crystal is present. • • • • LRCLK_OUT fixed at a frequency of 48 kHz (Fs). SCLK_OUT is fixed at a frequency of (64 x Fs). MCLK_OUT is fixed at a frequency of (256 x Fs). In master mode, the external ASRC converts incoming serial audio data to 48-kHz sample rate synchronous to the internally generated serial audio data clocks. Clock Slave operation: In Clock Slave operation, the SAP clock inputs are provided externally (that is, by a system controller) and passed through to the SAP Outputs.The MCLK_IN signal is internally divided down and sent directly to the ADC and DAC blocks, therefore analog audio performace is dependant on the quality of the MCLK_IN signal. As a result, degradation in analog performance is to be expected if the quality of MCLK_IN (that is, jitter, phase noise, etc) is not robust. DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends upon the quality of the MCLK_IN. The TAS3204 is not robust with respect to MCLK_IN errors (glitches, etc.); if the MCLK_IN frequency changes under operation, the device must be reset. • MCLK_IN (512 × Fs), • SCLK_IN (64 × Fs), and • LRCLK_IN (Fs) are supplied externally by an clocking device. • When the TAS3204 is used in a system in which the master clock frequency (fMCLK ) can change, the TAS3204 must be reset during the frequency change. In these cases, the procedure shown in Figure 3-2 should be used. In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz or 48 kHz. The TAS3204 only supports dynamic sample-rate changes between any of the supported sample frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the TAS3204 remains in normal operation and the register contents are preserved. To avoid producing audio artifacts during the sample-rate changes, a volume or mute control can be included in the application firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL source attached to MCLK_IN. Changing the sample rate on the fly in slave mode should be handled by a host system controller. The TAS3204 does not include any internal clock error or click/pop detection managment. Customer specific DAP filter coefficients must be uploaded by a host system controller when changing the sample rate. TAS3204 Clocking System Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 9 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Enable Mute and Wait for Completion RESET Pin = Low Change fMCLK Are Clocks Stable? No Yes RESET Pin = High After TAS3204 Initializes, Re-initialize 2 I C Registers Figure 3-2. Master Clock Frequency (fMCLK) Change Procedure Table 3-1. TAS3204 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz) MCLK/ LRCLK Ratio (× fS) MCLK Freq (MHz) SCLKIN Rate (× fS) FS Sample Rate (kHz) Ch Per SDIN 44.1 2 512 22.579 64 48 2 256 24.576 64 SCLK_IN Freq (MHz) SCLK_OUT Rate (× fS) Ch Per SDOUT LRCLK (FS) PLL Multiplier FDSPCLK (MHz) fDSPCLK/fS 2.822 64 2 64 5.5 124.2 2816 3.072 64 2 64 5.5 135.2 2816 N/A 64 2 64 5.5 135.2 2816 Slave Mode, 2 Channels In, 2 Channels Out Master Mode, 2 Channels In, 2 Channels Out 48 10 2 256 24.576 N/A TAS3204 Clocking System Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 4 Digital Audio Interface 4.1 Serial Audio Port (SAP) The TAS3204 can accept four channels of 16, 20, or 24 bit digial serial audio in the I2S, discrete left justified, or discrete right justified formats. The TAS3204 can provide four channels of 16, 20, or 24 bit digital serial audio in I2S, discrete left justified, or discrete right justified format. Output data rate is the same data rate as the input. The SDOUT output uses the SCLK_OUT and LRCLK_OUT signals to provide synchronization. The TAS3204 supported data formats are listed in Table 4-1. Table 4-1. Supported Data Formats Input SAP (SDIN1, SDIN2) Output SAP (SDOUT1, SDOUT2) 2-channel I2S 2-channel I2S 2-channel left-justified 2-channel left-justified 2-channel right-justified 2-channel right-justified Table 4-2. Serial Data Input and Output Formats Mode 2-channel Input Control IM[3:0] Output Control OM[3:0] 0000 0001 0010 Serial Format Word Lengths 0000 Left-justified 16, 20, 24 0001 Right-justified 16, 20, 24 0010 2 16, 20, 24 I S Data Rates (kHz) MAX SCLK (MHz) 32–48 3.072 Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 11 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Output Port Word Size Input Port Word Size Î Î Î Î 15 0x00 31 S Slave Addr Ack Subaddr Ack 24 xxxxxxxx 23 Ack 14 13 XX 16 xxxxxxxx 11 10 8 IW[2:0] OW[2:0] DWFMT (Data Word Format) 15 Ack 8 7 DWFMT Ack 7 4 0 IOM Ack 3 0 IM[3:0] OM[3:0] Input Port Format Output Port Format R0003-01 Figure 4-1. Serial Data Controls Table 4-3. Serial Data Input and Output Data Word Sizes IW1, OW1 IW0, OW0 FORMAT 0 0 Reserved 0 1 16-bit data 1 0 20-bit data 1 1 24-bit data Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass updates. Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet operation. However, care must be taken to ensure that the mute command has completed before the SAP is commanded to reconfigure. Similarly, the TAS3204 should not be commanded to unmute until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a volume or bass or treble update is taking place can cause the update not to be completed properly. When the TAS3204 is transmitting serial data, it uses the negative edge of SCLK to output a new data bit. The TAS3204 samples incoming serial data on the rising edge of SCLK. 12 Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 4.1.1 SLES197C – APRIL 2007 – REVISED MARCH 2011 2-Channel I 2S Timing In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused trailing data-bit positions. 2-Channel I2S (Philips Format) Stereo Input/Output 32 Clks LRCLK (Note Reversed Phase) 32 Clks Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-04 2 Figure 4-2. I S 64fS Format Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 13 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 4.1.2 www.ti.com 2-Channel Left-Justified Timing In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused trailing data-bit positions. 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 Figure 4-3. Left-Justified 64fS Format 14 Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 4.1.3 SLES197C – APRIL 2007 – REVISED MARCH 2011 2-Channel Right-Justified Timing In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused leading data-bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 MSB LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 20-Bit Mode 16-Bit Mode T0034-03 Figure 4-4. Right-Justified 64fS Format 4.1.4 SAP Input to SAP Output—Processing Flow All SAP data format options other than I2S result in a two-sample delay from input to output. If I2S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK must be inverted. However, if I2S format conversions are performed between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core relative to the sample rate of the incoming data. The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core operate on sample windows that are 180° out of phase with respect to the sample window used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint of the sample period used by the audio DSP core to process the data. If the processing cycle completes all processing tasks before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the processing time extends past the midpoint of the processing sample period, the output SAP outputs the data processed during the previous processing sample period. In the former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output is 2.5 samples. Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 15 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions are performed that involve the I2S format. However, which delay time is obtained for a particular application is determinable and fixed for that application, providing care is taken in the selection of MCLK_IN/XTAL_IN with respect to the incoming sample clock, LRCLK. 16 Digital Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 5 Analog Audio Interface 5.1 Analog to Digital Converters ADCs The TAS3204 has three differential analog stereo inputs that can be sent to either of two ADCs to be converted to digital data. The input multiplexers include a preamplifier. This amplifier is driving the ADCs, and it is digitally controlled with changes synchronized with the sample clock of the ADC. Minimal crosstalk between selected channels and unselected channels is maintained. When inputs are not needed they are configured for minimal noise. Also included in this module are two fully differential over sampled stereo ADCs. The ADCs are sigma-delta modulators with 256 times over-sampling ratio. Because of the over-sampling nature of the audio ADCs and integrated digital decimation filters, requirements for analog anti-aliasing filtering are relaxed. Filter performance for the ADCs are specified under physical characteristics. 5.2 Digital to Analog Converters DACs The TAS3204 has two stereo audio DACs, each of which consists of a digital interpolation filter, digital sigma-delta modulator and an analog reconstruction filter. Each DAC can operate a maximum sampling frequency of 48 kHz. Each DAC upsamples the incoming data by 128 and performs interpolation filtering and processing on this data before conversion to a stereo analog output signal. The sigma-delta modulator always operates at a rate of 128x xFs, which ensures that quantization noise generated within the modulator stays low within the frequency band below Fs/2.4 at all sample rates. The digital interpolation filters for interpolation from Fs to 8×Fs are included in the audio DSP upper memory (reserved for analog processing), while interpolation from 8×Fs to 128 x Fs is done in a dedicated hardware sample and hold filter. The TAS3204 includes two stereo line driver outputs. All line drivers are capable of driving up to a 10-kΩ load. Each stereo output can be in power-down mode when not used. Popless operation is achieved by conforming to start and stop sequences in the device controller code. 5.3 Analog Reference System This module provides all internal references needed by the analog modules. It also provides bias currents for all analog blocks. External decoupling capacitors are needed along with an external 1% tolerance resistor to set the internal bias currents. It includes a band-gap reference and several voltage buffers and a tracking current reference. The TAS3204 also uses an internally generated mid supply that is used to rereference all analog inputs and is present on all analog outputs. VMID is the analog mid supply and can be used when buffered externally to rereference the analog inputs and outputs. The voltage reference REXT requires a 22-kΩ 1% resistor to ground. The reference system can be powered down separately. Analog Audio Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 17 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 6 Embedded MCUcontroller The 8051 MCUcontroller receives and distributes I2C data, and participates in most processing tasks requiring multiframe processing cycles. The MCU has its own data RAM for storing intermediate values and queuing I2C commands, a fixed boot-program ROM, and a program RAM. The MCU boot program cannot be altered. The MCU controller has specialized hardware for master and slave interface operation, volume updates, and a programmable interval timer interrupt. For more information see the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). Once the MCUcontroller program memory has been loaded, it cannot be updated until the TAS3204 has been reset. 6.1 MCU Addressing Modes The 256 bytes of internal data memory address space is accessible using indirect addressing instructions (including stack operations). However, only the lower 128 bytes are accessible using direct addressing. The upper 128 bytes of direct address Data Memory space are used to access Extended Special Function Registers (ESFRs). 6.1.1 Register Banks There are four directly addressable register banks, only one of which may be selected at one time. The register banks occupy Internal Data Memory addresses from 00 hex to 1F hex. 6.1.2 Bit Addressing The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit addressable. SFRs that have addresses of the form 1XXXX000 binary are also bit addressable. 6.1.3 External Data Memory External data memory occupies a 2K × 8 address space. This space contains the External Special Function Data Registers (ESFRs). The ESFR permit access and control of the hardware features and internal interfaces of the TAS3204. 6.1.4 Extended Special Function Registers ESFRs provide signals needed for the M8051 to control the different blocks in the device. ESFR is an extension to the M8051. Figure 6-1 shows how these registers are arranged. 8051 MCU Internal Data Memory Bus DESTIN_DO DESTIN_A SFRWE Address Decoder D D WE Control Out WE CCLK CCLK SFRWA ESFRDI Control In CCLK Figure 6-1. Extended Special Function Registers 18 Embedded MCUcontroller Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 6.1.5 SLES197C – APRIL 2007 – REVISED MARCH 2011 Memory Mapped Registers for DAP Data Memory The following memory mapped registers are used for communication with the digital audio processor. Table 6-1. Memory Mapped Registers Address Register Comment 0x0300 Dither Seed Sets the dither seed value 0x0301 PC Start Sets the starting address of the DAP 0x0302 Reserved Reserved Note that TAS3204 has the same memory mapped registers distinction of upper and lower memory for these registers. 6.2 Boot Up Sequence On power up of the TAS3204 or immediatly following a reset, the slave interface is disabled and the master interface is enabled. Using the master interface, the TAS3204 automatically tests to see if an I2C EEPROM is at address 1010x. The value x can be chip select, other information, or don’t cares, depending on the EEPROM selected. If an EEPROM is present and it contains the correct header information and one or more blocks of program/memory data, the TAS3204 loads the program, coefficient, and/or data memories from the EEPROM. If a EEPROM is present, the download is complete when a header is read that has a zero-length data segment. At this point, the TAS3204 disables the master I2C interface, enables the slave I2C interface, and starts normal operation. If no EEPROM is present or if an error occurred during the EEPROM read, TAS3204 disables the master I2C interface, enables the slave I2C interface, and loads the default configuration stored in the ROM. In this default configuration, the TAS3204 streams audio from input to output if the GPIO pin is LOW. The master and slave interfaces do not operate simultaneously. Embedded MCUcontroller Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 19 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 7 Digital Audio Processor The DAP arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary features of the DAP are: • Two pipe parallel processing architecture – 48-bit data path with 76-bit accumulator – Hardware single cycle multiplier (28×48) – Three 48-bit general-purpose data registers and one 28-bit coefficient register – Four simultaneous operations per machine cycle – Shift right, shift left and bi-modal clip – Log2/Alog2 – Magnitude Truncation • Hardware acceleration units – Soft volume controller – Delay memory – Dither generator – log2/2× estimator • 1024 + 768 dual port ports words of data (24 and 48 bits, respectively) • 1228 words of coefficient memory (28 bits) • 3K word of program RAM (55 bits) • 5.88K words of 24-bits delay memory (1.22 ms) • Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into the same memory space for convenient addressing by the MCUcontroller. • Memory interface block contains four pointers, two for data memory and two for coefficient memory. 20 Digital Audio Processor Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 28 28 Micro Mem IF 28 48 28 DATA RAM COEF RAM 1022 × 48 1022 × 28 28 48 48 28 VOL (5 lsbs) (EREG4) 48 DI (3 lsbs) (EREG3) 48 48 LFS (LFSR) 2 28 48 48 48 28 48 28 48 48 48 48 B (BREG) 48 L (CREG) 48 MD (AREG) 48 48 28 MC (RREG) 28 Barrel Shift, NEG, ABS, or THRU DLYO (EREG1) 48 76 ACC LOG, ALOG, NEG, ABS, or THRU BR (PREG1) Multiply 48 76 LR (PREG2) MR PREG3 (PREG3) “ZERO” 76 48 48 Operand A 76 Legend 76 Register Operand B 28 ADD 32 76 48 CLIP Delay RAM 5.8K × 24 DLYI (DREG9) 76 28-bit data 32-bit data 48-bit data 76-bit data 48 Output Register File (DO1 – DO8) (DREG1 – DREG8) 32 To Output SAP Figure 7-1. DSP Core Block Diagram Digital Audio Processor Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 21 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 7.1 www.ti.com Audio Digital Signal Processor Core The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or third-party algorithms, is running in the DAP. The 8051 MCUcontroller has access to DAP resources such as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The primary blocks of the audio DSP core are: • 48-bit data path with 76-bit accumulator • DSP controller • Memory interface • Coefficient RAM (1K×28) • Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48) • Program RAM (3K×55) The DAP is discussed in detail in the following sections. 7.2 DAP Instructions Set Please see this information in the TAS3xxx Audio DSP Instruction Set Reference Guide 22 Digital Audio Processor Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 7.3 SLES197C – APRIL 2007 – REVISED MARCH 2011 DAP Data Word Structure Figure 7-2 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits are provided at the upper end of the 48-bit DAP word, and 16 bits of computational precision or noise bits are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed data samples The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve 48-bit DAP words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products is to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain precision in the intermediate computational stages. 40 39 47 32 31 24 23 22 21 20 19 16 15 8 7 0 16-Bit Audio 18-Bit Audio 20-Bit Audio Overhead/ Guard Bits Precision/Noise Bits 24-Bit Audio Figure 7-2. Arithmetic Unit Data Word Structure To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow correct the overflow condition (see Figure 7-3). The DAP memory banks include a dual port data RAM for storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user. + + Rollover + 1 0 1 1 0 1 1 1 (-73) 1 1 0 0 1 1 0 1 (-51) 1 0 0 0 0 1 0 0 (-124) -124 1 1 0 1 0 0 1 1 (-45) + -45 0 1 0 1 0 1 1 1 (57) 57 0 0 1 1 1 0 1 1 (59) 1 0 0 1 0 0 1 0 (-110) -73 + + -51 59 -110 Figure 7-3. DSP ALU Operation With Intermediate Overflow Digital Audio Processor Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 23 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com D23 D22 - - - - - D1 D0 Input 24-Bit Data 8-Bit Headroom and 16-Bit Noise 0...0 D23 D22 - - - - - D1 D0 0...0 47–40 39 - - - - - - 16 15–0 27–23 Coefficient Representation Scaling Headroom Multiplier Output 75–71 70–63 5 8 22 - - - - - - - - - - - - - - - 0 Data (24 bits) 62 – Fractional Noise 39 12 38–31 12 8 30 – 0 31 48-Bit Clipping POS48 – NEG48 – 0x7F_F 0x80_0 POS40 – NEG40 – 0xXX_ 0xXX_ FFF_FFFF 000_0000 _FF _00 32-Bit Clipping 7FFF_FFFF 8000_0000 _XX _XX 28-Bit Clipping POS20 – NEG20 – 0xXXXXX_ 0xXXXXX_ 7FFF_FFFF 8000_0000 Figure 7-4. DAP Data-Path Data Representation 24 Digital Audio Processor Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 8 I2C Control Interface The TAS3204 also two I2C interfaces that is compatible with the I2C bus protocol. The Master I2C supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes). The master I2C interface is used to load program and data from an external I2C EEPROM. The slave I2C interface supports both 100 kbps and 400 kbps data transfer rates for multiply 4 byte write and read operations (maximum 20 bytes). The slave I2C interface is used to program the registers of the device or to read the device status registers. Additionally, the slave I2C can be used to replace the information loaded by the I2C master interface. 8.1 General I2C Operations The I2C bus employs two signals, SDA (serial data) and SCL (serial clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The slave holds SDA LOW during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (one byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 8-1 shows the TAS3204 read and write operation sequences. As shown in Figure 8-1, an I2C read transaction requires that the master device first issue a write transaction to give the TAS3204 the subaddress to be used in the read transaction that follows. This subaddress assignment write transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be written. For I2C write transactions, the subaddress must always be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If a subaddress-assignment-only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3204 as another subaddress replacing the one previously written. I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 25 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com TAS3204 Subaddress (By Master) Data (By TAS3204) TAS3204 Address Data (By TAS3204) TAS3204 Address Acknowledge (By TAS3204) Acknowledge (By TAS3204) Acknowledge (By TAS3204) TAS3204 Subaddress (By Master) TAS3204 Address Acknowledge (By TAS3204) Acknowledge (By TAS3204) Acknowledge (By TAS3204) Acknowledge (By TAS3204) Acknowledge (By TAS3204) Figure 8-1. I2C Subaddress Access Protocol 8.2 I2C Master Interface IIn the master mode, the I2C bus is used to:. • Load the program and coefficient data – MCU program memory – MCU extended memory – Audio DSP core program memory – Audio DSP core coefficient memory – Audio DSP core data memory The TAS3204, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3204 operates as an I2C master, the TAS3204 generates a repeated start without an intervening stop command while downloading program and memory data from EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to transfer large blocks of data quickly. The first action of the TAS3204 as master is to transmit a start condition along with the device address of the I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address byte, and the TAS3204 sends a subaddress byte, which the EEPROM acknowledges. Most EEPROMs have at least 2-byte addresses and acknowledge as many as are appropriate. At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3204 acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. The memory load information starts with reading the header and data information that starts at subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header locations. 26 I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 The TAS3204 memory data can be stored and loaded in (almost) any order. Additionally, this addressing scheme permits portions of the TAS3204 internal memories to be loaded. I2C EEPROM Memory Map Block Header 1 Data Block 1 Block Header 2 Data Block 2 w w w Block Header N Data Block N M0040−01 Figure 8-2. EEPROM Address Map The TAS3204 sequentially reads EEPROM memory and loads its internal memory unless it does not find a valid memory header block, is not able to read the next memory location because the end of memory was reached, detects a checksum error, or reads an end-of-program header block. When it encounters an invalid header or read error, the TAS3204 attempts to read the header or memory location three times before it determines that it has an error. If the TAS3204 encounters a checksum error it attempts to reread the entire block of memory two more times before it determines that it has an error. Once the MCU program memory has been loaded, it cannot be reloaded until the TAS3204 has been reset. If an error is encountered, TAS3204 terminates its memory-load operation, loads the default configuration, and disables further master I2C bus operations. If an end-of-program data block is read, the TAS3204 has completed the initial program load. The I2C master mode uses the starting and ending I2C checksums to verify a proper EEPROM download. The first 16-bit data word received from the EEPROM, the I2C checksum at subaddress 0x00, is stored and compared against the 16-bit data word received for the last subaddress, the ending I2C checksum, and the checksum that is computed during the download. These three values must be equal. If the read and computed values do not match, the TAS3204 sets the memory read error bits in the status register and repeats the download from the EEPROM two more times. If the comparison check fails the third time, the TAS3204 sets the MCU program to the default value. Table 8-1 shows the format of the EEPROM or other external memory load file. Each line of the file is a byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four bytes of the checksum. Example: I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 27 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Given the following example MCU data or program block (must be a multiple of 4 bytes for these blocks): 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 The checksum = 0x10 + 0x20 + 0x30 + 0x30 + 0x40 + 0x50 + 0x60 + 0x70 + 0x80 = 0x240, so the values put in the checksum fields are MS byte = 0x02 and LS byte = 0x40. If the checksum is >FFFFh, then the 2-byte checksum field is the least-significant 2 bytes. For example, if the checksum is 0x1D 45B6, the checksum field is MS byte = 0x45 and LS byte = 0xB6. Table 8-1. TAS3204 Master I2C Memory Block Structures STARTING BYTE DATA BLOCK FORMAT SIZE NOTES 12-Byte Header Block Checksum code Most Significant Byte 0 2 Bytes Checksum of bytes 2 through N + 12. If this is a termination header, this value is 00 00 2 Bytes Must be 0x001F for the TAS3204 to load as part of initialization. Any other value terminates the initialization memory load sequence. Memory to be loaded 1 Byte 0x00 – MCU program memory - or - termination header 0x01 – MCU external data memory 0x02 – Audio DSP core program memory 0x03 – Audio DSP core coefficient memory 0x04 – Audio DSP core data memory 0x05–06 – Audio DSP upper program memory 0x07 – Audio DSP Upper Coefficient Memory 0x08–FF – Reserved for future expansion 0x00 1 Byte Reserved 2 Bytes If this is a termination header, this value is 0000. 2 Bytes 12 + data bytes + last checksum bytes. If this is a termination header, this value is 0000. Checksum code Least Significant Byte Header ID byte 1 = 0x00 2 Header ID byte 2 = 0x1F 4 5 Start TAS3204 memory address Most Significant Byte 6 Start TAS3204 memory address Least Significant Byte Total number of bytes transferred Most Significant Byte 8 Total number of bytes transferred Least Significant Byte 10 0x00 1 Byte Unused 11 0x00 1 Byte Unused Data Block for MCU Program or Data Memory (Following 12-Byte Header) Data Byte 1 (LSB) Data Byte 2 12 Data Byte 3 4 Bytes MCU Bytes 1-4 4 Bytes MCU Bytes 5-8 4 Bytes MCU Bytes N-N+4 Data byte 4 (MSB) Data byte 5 Data byte 6 16 Data byte 7 Data byte 8 ⋮ Data byte 4×(Z – 1) + 1 N+8 Data byte 4×(Z – 1) + 2 Data byte 4×(Z – 1) + 3 Data byte 4×(Z – 1) + 4 = N 28 I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 Table 8-1. TAS3204 Master I2C Memory Block Structures (continued) STARTING BYTE DATA BLOCK FORMAT SIZE NOTES 0x00 N + 12 0x00 Checksum code MS Byte 4 Bytes Repeated checksum bytes 2 through N + 11 Checksum code LS Byte Data Block for Audio DSP Core Coefficient Memory (Following 12-Byte Header) Data byte 1 (LS byte) 12 Data byte 2 Data byte 3 Coefficient word 1 (valid data in Bit 27–Bit 0) Bit 7–Bit 0 4 bytes Data byte 4 (MS byte) Bit 15–Bit 8 Bit 23–Bit 16 Bit 31–Bit 24 Data byte 5 16 Data byte 6 Data byte 7 4 bytes Coefficient word 2 4 bytes Coefficient word Z 4 bytes Repeated checksum bytes 2 through N + 11 Data byte 8 ⋮ Data byte 4×(Z – 1) + 1 N+8 Data byte 4×(Z – 1) + 2 Data byte 4×(Z – 1) + 3 Data byte 4×(Z – 1) + 4 = N 0x00 N + 12 0x00 Checksum code MS byte Checksum code LS byte Data Block for Audio DSP Core Data Memory (Following 12-Byte Header) Data byte 1 (LS byte) Data word 1 Bit 7–Bit 0 Data byte 2 12 Data byte 3 Data byte 4 Bit 15–Bit 8 6 bytes Bit 23–Bit 16 Bit 31–Bit 24 Data byte 5 Bit 39–Bit 32 Data byte 6 (MS byte) Bit 47–Bit 40 Data byte 7 Data byte 8 18 Data byte 9 Data byte 10 6 bytes Data 2 6 bytes Data Z Data byte 11 Data byte 12 ⋮ Data byte 6×(Z – 1) + 1 Data byte 6×(Z – 1) + 2 N+6 Data byte 6×(Z – 1) + 3 Data byte 6×(Z – 1) + 4 Data byte 6×(Z – 1) + 5 Data byte 6×(Z – 1) + 6 = N I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 29 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Table 8-1. TAS3204 Master I2C Memory Block Structures (continued) STARTING BYTE DATA BLOCK FORMAT SIZE NOTES 0x00 0x00 0x00 N + 12 6 bytes 0x00 Repeated checksum bytes 2 through N + 11 Checksum code MS byte Checksum code LS byte Data Block for Audio DSP Core Program Memory (Following 12-Byte Header) Program byte 1 (LS byte) 12 Program word 1 (valid data in Bit 53–Bit 0) Bit 7–Bit 0 Program byte 2 Bit 15–D8 Program byte 3 Bit 23–Bit 16 Program byte 4 7 bytes Bit 31–Bit 24 Program byte 5 Bit 39–Bit 32 Program byte 6 Bit 47–Bit 40 Program byte 7 (MS byte) Bit 55–Bit 48 Program byte 8 Program byte 9 Program byte 10 19 Program byte 11 7 bytes Program word 2 7 bytes Program word Z 7 bytes Repeated checksum bytes 2 through N + 11 2 bytes First 2 bytes of termination block are always 0x0000. 2 bytes Second 2 bytes are always 0x001F. Program byte 12 Program byte 14 Program byte 15 ⋮ Program byte 7×(Z – 1) + 1 Program byte 7×(Z – 1) + 2 Program byte 7×(Z – 1) + 3 N+5 Program byte 7×(Z – 1) + 4 Program byte 7×(Z – 1) + 5 Program byte 7×(Z – 1) + 6 Program byte 7×(Z – 1) + 7 = N 0x00 0x00 0x00 N + 12 0x00 0x00 Checksum code MS byte Checksum code LS byte 20-Byte Termination Block (Last Block of Entire Load Block) BLAST – 19 BLAST – 17 0x00 0x00 0x00 0x1F BLAST – 15 0x00 1 byte BLAST – 14 0x00 1 byte ⋮ BLAST 30 0x00 Last 16 bytes must each be 0x00. 1 byte I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 8.3 SLES197C – APRIL 2007 – REVISED MARCH 2011 I2C Slave Mode Operation In the slave mode, the I2C bus is used to: • Load the program and coefficient data – MCU program memory – MCU extended memory – Audio DSP core program memory – Audio DSP core coefficient memory – Audio DSP core data memory • Update coefficient and other control values • Read status flags The coefficient download operation in slave mode can be used to replace the I2C master-mode EEPROM download. The TAS3204 supports both random and sequential I2C transactions. The TAS3204 I2C slave address is 0b011010xy, where the first six bits are the TAS3204 device address and bit x is CS0, which is set by the TAS3204 internal MCU at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00 address when no connection is made to the pin. Table 6-1 and Table 8-3 show all the legal addresses for I2C slave and master modes. Once the MCU program memory has been loaded, it cannot be updated until the TAS3204 has been reset. The master and slave modes do not operate simultaneously. When acting as an I2C slave, the data transfer rate is determined by the master device on the bus. The I2C communication protocol for the I2C slave mode is shown in Figure 8-3. The I2C communication protocol for the I2C slave mode is shown in Figure 8-3. Start (By Master) Read or Write (By Master) Stop (By Master) Slave Address (By Master) S 0 1 1 0 1 Data Byte (By Transmitter) C S 0 0 R / W A C K M S B Data Byte (By Transmitter) L S B A C K M S B L S B A C K S (1) Acknowledge (By TAS3204) MSB SDA Acknowledge (By Receiver) MSB-1 MSB-2 Acknowledge (By Receiver) LSB SCL Start Condition SDA ↓While SCL = 1 Stop Condition SDA ↑While SCL = 1 Figure 8-3. I2C Slave-Mode Communication Protocol The number of data bytes plus the two bytes checksum must be evenly divisible by the word size. The size field is equal to (header + payload + end checksum). I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 31 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com The checksum is contained in the last two data transfer bytes. These are bytes 7 and 8. On single word transfers (DAP data, DAP instruction), the checksum is always contained in a 8 byte frame that follows the last data word, last two bytes. For multiword data register transfers data (MCU Program RAM, MCU External Data RAM, and DAP Coefficient RAM), the checksum is included in the same byte transfer as data. To meet the requirement above, the number of words that are transferred contain modulo 8 + 6 in the case of MCU program and data memory, and modulo 2 + 1 in the case of coefficient memory. When the slave I2C download is used to replace or update sections of MCU program, MCU data, or DAP coefficient memory, it is necessary to take these transfer size restrictions into consideration when determining program, data, and coefficient placements. The multi word transfers always store first word on the bus at a lower RAM address and increment such that the last word in the transfer is stored with the highest target RAM address. Consecutive I2C frame transfers increment target address such that the data in the last transfer is last in target memory address space. When the first I2C slave download register is written by the system controller, the TAS3204 updates the status register by setting a error bit to indicate an error for the memory type that is being loaded. This error bit is reset when the operation complete and a valid checksum has been received. For example when the MCU program memory is being loaded, the TAS3204 sets a MCU program memory error indication in the status register at the start of the sequence. When the last byte of the MCU program memory and checksum is received, the TAS3204 clears the MCU program memory error indication. This enables the TAS3204 to preserve any error status indications that occur as a result of incomplete transfers of data/ checksum error during a series of data and program memory load operations. The checksum is always contained in the last two bytes of the data block. The I2C slave download is terminated when a termination header with a zero-length byte-count file is received. The status register always reflects status of EEPROM boot attempts, unless the user writes to the slave control register. A write to the slave boot control register causes the EEPROM status register to reflect slave boot attempt status. NOTE Once the MCU program memory has been loaded, further updates to this memory are prohibited until the device is reset. The TAS3204 I2C block does respond to the broadcast address (0x00). Figure x.x shows the block format of the I2C slave Interface. or other external memory load file. Each line of the file is a byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four bytes of the checksum Table 8-2. Slave Addresses 32 Base Address CS0 R/W Slave Address 0110 10 0 0 0x68 0110 10 0 1 0x69 0110 10 1 0 0x6A 0110 10 1 1 0x6B I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 Table 8-3. Master Addresses Base Address CS0 R/W Master Address 1010 00 0 0 0xA0 1010 00 0 1 0xA1 1010 00 1 0 0xA2 1010 00 1 1 0xA3 The following is an example use of the I2C master address to access an external EEPROM. The TAS3204 can address up to two EEPROMs depending on the state of CS0. Initially, the TAS3204 comes up in I2C master mode. If it finds a memory such as the 24C512 EEPROM, it reads the headers and data as previously described. In this I2C master mode, the TAS3204 addresses the EEPROMs as shown in Table 8-4 and Table 8-5. Table 8-4. EEPROM Address I2C TAS3204 Master Mode = 0xA1/A0 MSB 1 0 1 0 A0 (EEPROM) CS0 R/W 0 0 1/0 0 Table 8-5. EEPROM Address I2C TAS3204 Master Mode = 0xA3/A2 MSB 1 8.3.1 0 1 0 A0 (EEPROM) CS0 R/W 0 1 1/0 0 Multiple-Byte Write Multiple data bytes are transmitted by the master device to slave as shown in Figure 8-4. After receiving each data byte, the TAS3204 responds with an acknowledge bit. Start Condition Acknowledge A6 A5 A1 A6 A0 R/W ACK A7 A5 2 A4 A3 A1 Acknowledge Acknowledge Acknowledge A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK Other Data Bytes First Data Byte Subaddress I C Device Address and Read/Write Bit Acknowledge Last Data Byte Stop Condition T0036-02 Figure 8-4. Multiple-Byte Write Transfer 8.3.2 Multiple-Byte Read Multiple data bytes are transmitted by the TAS3204 to the master device as shown in Figure 8-5. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge A6 2 A0 R/W ACK A7 I C Device Address and Read/Write Bit Acknowledge A6 A6 A0 ACK A5 Subaddress 2 Acknowledge Acknowledge Acknowledge Not Acknowledge A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-04 Figure 8-5. Multiple-Byte Read Transfer I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 33 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Random I2C Transactions Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For random I2C read commands, the TAS3204 responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in accordance with the data assignment for that address space. If a write command is received for a mixer subaddress, for example, the TAS3204 expects to see five 32-bit words. If fewer than five data words have been received when a stop command (or another start command) is received, the data received is discarded. Sequential I2C Transactions The TAS3204 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS3204. For I2C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written to. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data is discarded. Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master does not issue enough data-received acknowledges to receive all the data for a given subaddress, the master device simply does not receive all the data. If the master device issues more data-received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both sequential and random, can impose wait states. 34 I2C Control Interface Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 9 TAS3204 Control Pins 9.1 Reset (RESET) - Power-Up Sequence The RESET pin is an asynchronous control signal that restores all TAS3204 components to the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A reset can be initiated by applying a logic 0 on RESET. As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain in that state until device initialization has completed. The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and setting the default register values. Once these are complete, the TAS3204 enables its master I2C interface and disables its slave I2C interface and startes the boot sequence. Using the master interface, the TAS3204 automatically tests to see if an external I2C EEPROM is at address "1010x". The value x can be chip selects, other information, or don't care, depending on the EEPROM selected. If a memory is present and it contains the correct header information and one or more blocks of program/memory data, the TAS3204 begins to load the program, coefficient and/or data memories from the external EEPROM. The download is considered complete when an end of program header is read by the TAS3204. At this point, the TAS3204 disables the master I2C interface, enable the slave I2C interface, and start normal operation. After a successful download, the MCU program counter is reset, and the downloaded MCU and DAP application firmware controls execution. If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3204 disables the master I2C interface and enables the slave I2C interface initialization to load the slave default configuration. In this default configuration, the TAS3204 streams audio from input to output if GPIO1 is asserted LOW; if the GPIO1 pin is asserted HIGH, the ADC and the DAC are muted. On power up, it is recommended that the TAS3204 RESET be held LOW until DVDD has reached 3.3 V. This can be done by programming the system controller or by using an external RC delay circuit. The 1-kΩ and 1-μF values provide a delay of approximately 200 μs. The values of R and C can be adjusted to provide other delay values as necessary. Note: The master and slave interfaces do not operate simultaneously. 9.2 Voltage Regulator Enable (VREG_EN) Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are lost in this power down mode. A full power-up/reset/program-load sequence must be completed before the device is operational. 9.3 Power Down (PDN) The TAS3204 supports a number of power-down modes. PDN can be used to put the device into power saving standby mode. PDN is user-firmware definable. Its default configuration is to stop all clocks, power down all analog circuitry, and ramp down volume for all digital inputs. This mode is used to minimize power consumption while preserving register settings. If there is no EEPROM or if the EEPROM has an invalid image–i.e., an unsuccessful boot from the EEPROM–and PDN is pulled low, the TAS3204 is in powerdown mode. After a successful boot, PDN is defined by the boot code. Individual power down DAC and ADC – Each stereo DAC and ADC can be powered down individually. To avoid audible artifacts at the outputs, the sequences defined in the TI document TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) must be followed. The control signals for these operations are defined as ESFR. The feature is made available to the board controller via the I2C interface. TAS3204 Control Pins Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 35 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Power down of analog reference – The analog reference can be powered down if all DAC and ADC are powered down. This operation is handled by the device controller through the ESFRs, and is made available to the board controller via the I2C interface. 9.4 I2C Bus Control (CS0) The TAS3204 has a control to specify the slave and master I2C address. This control permits up to two TAS3204 devices to be placed in a system without external logic. GPIO pins are level sensitive. They are not edge triggered. See Section 8.3 for a complete description of this pin. 9.5 Programmable I/O (GPIO) The TAS3204 has four GPIO pins and two general purpose input pins that are 8051 firmware programmable. GPIO1 and GPIO2 pins are single function I/O pins. Upon power up, GPIO1 is an input. If there is an unsuccessful boot and GPIO1 is pulled high externally, the DAC output is disabled. If there is an unsuccessful boot and the GPIO1 is pulled low externally, the DAC output is enabled. If there is a successful boot, GPIO1 is pulled low by the internal MCU, and its function is defined by the boot code in the EEPROM. GPIO3 and GPIO4 pins are dual function I/O pins. These pins can be used as SDIN1 and SDIN2 respectively. Mute and power down functions have to be programmed in the EEPROM boot code. These are general-purpose input pins and can be programmed for functions other than mute and power down. 9.5.1 No EEPROM is Present or a Memory Error Occurs Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the TAS3204 is in one of two modes, depending on the setting of GPIO1. • GPIO1 is logic HIGH With GPIO1 held HIGH during initialization, the TAS3204 comes up in the default configuration with the serial data outputs not active. Once the TAS3204 has completed the default initialization procedure, after the status register is updated and the I2C slave interface is enabled, then GPIO1 is an output and is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can access the TAS3204 through the I2C interface and read the status register to determine the load status. If a memory-read error occurs, the TAS3204 reports the error in the status register (I2C subaddress 0x02). • GPIO1 is logic LOW With GPIO1 held LOW during initialization, the TAS3204 comes up in an I/O test configuration. In this case, once the TAS3204 completes its default test initialization procedure, the status register is updated, the I2C slave interface is enabled, and the TAS3204 streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc. In this configuration, GPIO1 is an output signal that is driven LOW. If the external logic is no longer driving GPIO1 low after the load has completed (~100 ms following a reset if no EEPROM is present), the state of GPIO1 can be observed. Then the system controller can access the TAS3204 through the I2C interface and read the status register to determine the load status. If the GPIO1 state is not observed, the only indication that the device has completed its initialization procedure is the fact that the TAS3204 streams audio and the I2C slave interface has been enabled. 36 TAS3204 Control Pins Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 9.5.2 SLES197C – APRIL 2007 – REVISED MARCH 2011 GPIO Pin Function After Device Is Programmed Once the TAS3204 has been programmed, either through a successful boot load or via slave I2C download, the operation of GPIO can be programmed to be an input and/or output. TAS3204 Control Pins Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 37 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 10 Algorithm and Software Development Tools for TAS3204 The TAS3204 algorithm and software development tool set is a combination of classical development tools and graphical development tools. The tool set is used to build, debug, and execute programs in both the audio DSP and 8051 sections of the TAS3204. Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level debuggers. The 8051 can be programmed exclusively in ANSI C. The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051 tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator. The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete environment with an IDE, context-sensitive editor, assembler, and simulator/debugger. Graphical development tooling provides a means of programming the audio DSP core and 8051 through a graphical drag-and-drop interface using modular audio software components from a component library. The graphical tooling produces audio DSP assembly and 8051 ANSI C code as well as coefficients and data. The classical tools can also be used to produce the executable code. In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051 code on both simulators and EVM hardware. 38 Algorithm and Software Development Tools for TAS3204 Submit Documentation Feedback Product Folder Link(s): TAS3204 Copyright © 2007–2011, Texas Instruments Incorporated TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 11 Electrical Specifications 11.1 Absolute Maximum Ratings (1) over operating temperature range (unless otherwise noted) DVDD Digital supply voltage range AVDD Analog supply voltage range –0.5 V to 3.8 V –0.5 V to 3.8 V 3.3-V TTL –0.5 V to DVDD + 0.5 V VI Input voltage range VO Output voltage range IIK Input clamp current (VI < 0 or VI > DVDD) IOK Output clamp current (VO < 0 or VO > DVDD) TA Operating free-air temperature range Tstg Storage temperature range (1) 1.8 V LVCMOS (XTLI) –0.5 V to 2.3 V 3.3 V TTL –0.5 V to DVDD + 0.5 V –0.5 V to 2.3 V (2) 1.8 V LVCMOS (XTLO) ±20 μA ±20 μA 0°C to 70°C –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Pin XTAL_OUT is the only TAS3204 output that is derived from the internal 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTAL_OUT. Note: • VR_ANA is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices. • VR_DIG is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices. • VR_PLL is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices. (2) 11.2 Package Dissipation Ratings Package Description Package Type Pin Count Package Designator TQFP 64 PAG TA ≤ 25°C Power Rating (mW) Derating Factor Above TA = 25°C (mW/°C) TA = 70°C Power Rating (mW) 1869 23.36 818 11.3 Recommended Operating Conditions MIN NOM MAX DVDD Digital supply voltage 3 3.3 3.6 V AVDD Analog supply voltage 3 3.3 3.6 V 3.3 V TTL 2 VIH High-level input voltage VIL Low-level input voltage TA Operating ambient air temperature 0 TJ Operating junction temperature 0 1.8 V LVCMOS (XTL_IN) Analog output load V 1.2 3.3 V TTL 0.8 1.8 V LVCMOS (XTL_IN) 0.5 Analog differential input Resistance Capacitance 25 Submit Documentation Feedback Product Folder Link(s): TAS3204 V 70 °C 105 °C 2 VRMS 10 kΩ 100 pF Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated UNIT 39 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 11.4 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT 3.3-V TTL IOH = –4 mA 1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 3.3-V TTL IOL = 4 mA 0.5 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.4 3.3-V TTL VI = VIL ±20 3.3-V TTL VI = VIL ±20 1.8-V LVCMOS (XTL_IN) VI = VIL ±20 3.3-V TTL VI = VIH ±20 1.8-V LVCMOS (XTL_IN) VI = VIH ±20 Digital supply current Normal operation MCLK_IN = 24.576 MHz, LRCLK = 48 kHz 130 mA Analog supply current Normal operation MCLK_IN = 24.576 MHz, LRCLK = 48 kHz 60 mA Normal operation MCLK_IN = 24.576 MHz, LRCLK = 48 kHz 627 mW With voltage regulators on 23 mW With voltage regulators off 825 μW 20 mW VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance output current IIL Low-level input current IIH High-level input current IDVDD IAVDD Power Dissipation (Total) TEST CONDITIONS Digital and analog supply current Standby mode 2.4 V 1.44 Reset mode V μA μA μA VR_ANA Internal voltage regulator – analog 1.6 1.8 1.98 V VR_PLL Internal voltage regulator – PLL 1.6 1.8 1.98 V VR_DIG Internal voltage regulator – digital 1.6 1.8 1.98 V 11.5 Audio Specifications TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range (unless otherwise noted) PARAMETER Overall performance: input ADC – DAP – DAC – line out ADC section TEST CONDITIONS MAX UNIT Evaluation module. A-weighted, –60 dB with respect to full scale 100 dB THD+N Evaluation module. –3 dB with respect to full scale 101 dB Dynamic range A-weighted, –60 dB with respect to full scale. 102 dB THD+N –4 dB with respect to full scale. 93 dB Crosstalk One channel = –3 dB; Other channel = 0 V 84 dB Power supply rejection ratio 1 kHz, 100 mVpp on AVDD 57 dB 20 kΩ Input capacitance 10 pF Pass band edge 0.45Fs Hz Pass band ripple ±0.01 dB Stop band edge 0.55Fs Hz Stop band attenuation Group delay 40 TYP Dynamic range Input resistance ADC decimation filter MIN Electrical Specifications 100 dB 37÷Fs Sec Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 Audio Specifications (continued) TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Differential full scale output voltage TYP MAX 2 Dynamic range A-weighted, –60 dB with respect to full scale THD+N UNIT VRMS 105 dB –1-dBFS input, 0-dB gain 95 dB DAC to ADC One channel –3 dBFS; Other channel 0 V 84 dB ADC to DAC One channel –3 dB; Other channel 0 V 84 dB DAC to DAC One channel –3 dBFS; Other channel 0 V 84 dB Power supply rejection ratio 1 kHz, 100 mVpp on AVDD 56 dB DC offset With respect to VREF DAC section Crosstalk DAC interpolation filter MIN mV Pass band edge 0.45Fs Hz Pass band ripple ±0.06 dB Transition band 1.45 Fs to 0.55Fs Hz Stop band edge 7.4Fs Hz -65 dB 21÷Fs Sec Stop band attenuation Filter group delay Figure 11-1. Frequency Response (ADC-DAC) Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 41 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com Figure 11-2. THD+N (ADC-DAC) 42 Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 11.6 Timing Characteristics The following sections describe the timing characteristics of the TAS3204. 11.7 Master Clock over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER f(XTAL_IN) Frequency, XTAL_IN (1/ tc(1)) tc(1) Cycle time, XTAL_IN f(MCLK_IN) Frequency, MCLK_IN (1/ tc(2)) tw(MCLK_IN) Pulse duration, MCLK_IN high See MIN (1) TYP (2) 0.4 tc(2) 512Fs Hz Sec 0.5 tc(2) Crystal frequency deviation tr(MCLKO) Rise time, MCLKO CL = 30 pF tf(MCLKO) Fall time, MCLKO CL = 30 pF tw(MCLK_IN) Pulse duration, MCLKO high See td(MI-MO) (1) (2) (3) (4) (5) (6) 256Fs (3) XTAL_IN master clock source Delay time, MCLK_IN rising edge to MCLKO rising edge Hz 0.6 tc(2) 50 Frequency, MCLKO (1/ tc(3)) UNIT 1÷512Fs 512Fs See f(MCLKO) MCLKO jitter MAX ns ppm Hz 15 ns 15 ns HMCLKO ns 80 ps MCLK_IN master clock source See MCLKO = MCLK_IN See (5) 20 ns See (5) (6) 20 ns MCLKO < MCLK_IN (4) ps Duty cycle is 50/50. Period of MCLK_IN = TMCLK_IN = 1/fMCLK_IN HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLK_IN when MCLKO = MCLK_IN. When MCLKO = 0.5 MCLK_IN or 0.25 MCLK_IN, the duty cycle of MCLKO is typically 50%. When MCLKO is derived from MCLK_IN, MCLKO jitter = MCLK_IN jitter Only applies when MCLK_IN is selected as master source clock Also applies to MCLKO falling edge when MCLKO = MCLK_IN/2 or MCLK_IN/4 XTALI tc(1) tw(MCLKI) MCLKI tc(2) td(MI-MO) tw(MCLKO) tf(MCLKO) tr(MCLKO) MCLKO tc(3) T0088-01 Figure 11-3. Master Clock Signal Timing Waveforms Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 43 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 11.8 www.ti.com Serial Audio Port, Slave Mode over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER fLRCLK Frequency, LRCLK (fS) tw(SCLKIN) Pulse duration, SCLKIN high See (1) fSCLKIN Frequency, SCLKIN See (2) tpBit Propagation delay, SCLKIN falling edge to SDOUT 1 tsu1 Setup time, LRCLK to SCLKIN rising edge th1 Hold time, LRCLK from SCLKIN rising edge tsu2 Setup time, SDIN to SCLKIN rising edge th2 Hold time, SDIN from SCLKIN rising edge tpBit Propagation delay, SCLKIN falling edge to SCLKOUT2 falling edge (1) (2) 2 MIN TYP MAX UNIT 48 kHz 0.4 tc(SCLKIN) 0.5 tc(SCLKIN) 0.6 tc(SCLKIN) 64 FS ns MHz 16 ns 10 ns 5 ns 10 ns 5 ns 15 ns Period of SCLKIN = TSCLKIN = 1/fSCLKIN Duty cycle is 50/50. tw(SCLKIN) tc(SCLKIN) SCLKIN th1 tsu1 LRCLK (Input) tpd1 SDOUT1 SDOUT2 SDOUT3 SDOUT4 th2 tsu2 SDIN1 SDIN2 SDIN3 SDIN4 tpd2 SCLKOUT2 T0090-01 Figure 11-4. Serial Audio Port Slave Mode Timing Waveforms 44 Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com 11.9 SLES197C – APRIL 2007 – REVISED MARCH 2011 Serial Audio Port Master Mode Signals (TAS3204) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN CL = 30 pF TYP MAX f(LRCLK) Frequency LRCLK tr(LRCLK) Rise time, LRCLK tf(LRCLK) Fall time, LRCLK f(SCLKOUT) Frequency, SCLKOUT CL = 30 pF tr(SCLKOUT) Rise time, SCLKOUT CL = 30 pF 12 ns tf(SCLKOUT) Fall time, SCLKOUT CL = 30 pF 12 ns tpBit Propagation delay, SCLKOUT falling edge to LRCLK edge 5 ns 5 ns (1) (1) 48 UNIT kHz CL = 30 pF 12 Duty cycle is 50/50 12 64FS ns ns MHz 1(SCLKOUT) tpBit 2 Propagation delay, SCLKOUT falling edge to SDOUT1-2 tsu Setup time, SDIN to SCLKOUT rising edge 25 ns th Hold time, SDIN from SCLKOUT rising edge 30 ns (1) Rise time and fall time measured from 20% to 80% of maximum height of waveform. tr(SCLKOUT) tf(SCLKOUT) SCLKOUT2 tr(SCLKOUT) tf(SCLKOUT) tsk SCLKOUT1 tpd1(SCLKOUT2) tpd1(SCLKOUT1) LRCLK (Output) tf(LRCLK), tr(LRCLK) tpd2 SDOUT1 SDOUT2 SDOUT3 SDOUT4 th tsu SDIN1 SDIN2 SDIN3 SDIN4 T0091-01 Figure 11-5. Serial Audio Port Master Mode Timing Waveforms Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 45 TAS3204 SLES197C – APRIL 2007 – REVISED MARCH 2011 www.ti.com 11.10 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices PARAMETER STANDARD MODE TEST CONDITIONS UNIT MIN MAX MIN MAX 0.8 –0.5 0.8 VIL LOW-level input voltage –0.5 VIH HIGH-level input voltage 2 Vhys Hysteresis of inputs VOL1 LOW-level output voltage (open drain or open collector) 3-mA sink current tof Output fall time from VIHmin to VILmax Bus capacitance from 10 pF to 400 pF II Input current, each I/O pin tSP(SCL) SCL pulse duration of spikes that must be suppressed by the input filter tSP(SDA) SDA pulse duration of spikes that must be suppressed by the input filter CI Capacitance, each I/O pin (1) (2) (3) FAST MODE N/A N/A V 2 V 0.05 VDD V 0 0.4 V 250 7 + 0.1 Cb (1) 250 ns 10 –10 (2) 10 (2) μA N/A N/A 14 (3) ns N/A N/A 22 (3) ns –10 10 10 pF 2 Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I C specification. The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off. These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles. 11.11 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices all values are referred to VIHmin and VILmax (see Section 11.10) STANDARD MODE PARAMETER MIN MAX FAST MODE MIN MAX SCL clock frequency 0 tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 0.6 μs tLOW LOW period of the SCL clock 4.7 1.3 μs tHIGH HIGH period of the SCL clock 4 0.6 μs tSU-STA Setup time for repeated START 4.7 0.6 μs tSU-DAT Data setup time 250 tHD-DAT Data hold time tr Rise time of both SDA and SCL signals 0 0 400 (1) fSCL (2) (3) 100 UNIT μs 100 0 0.9 μs 20 + 0.1 Cb (4) 300 ns 20 + 0.1 Cb (4) 300 3.45 1000 tf Fall time of both SDA and SCL tSU-STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Cb Capacitive load for each bus line VnL Noise margin at the LOW level for each connected device (including hysteresis) 0.1VDVDD 0.1VDVDD V VnH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2VDVDD 0.2VDVDD V (1) (2) (3) (4) 46 300 kHz 4 4.7 μs 1.3 400 ns μs 0.6 400 pF In master mode, the maximum speed is 375 kHz. Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges of SCL. TI recommends that a 2-kΩ pullup resistor be used to avoid potential timing issues. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. Cb = total capacitance of one bus line in pF Electrical Specifications Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3204 TAS3204 www.ti.com SLES197C – APRIL 2007 – REVISED MARCH 2011 NOTE SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges of SCL. SDA tf tSU-DAT tHD-STA tLOW tr tSP tr tBUF tf SCL tHD-DAT tSU-STA tHD-STA tSU-STO tHIGH S Sr P S T0114-01 Figure 11-6. Start and Stop Conditions Timing Waveforms 11.11.1 Recommended I2C Pullup Resistors It is recommended that the I2C pullup resistors RP be 4.7 kΩ (see Figure 11-7). If a series resistor is in the circuit (see Figure 11-8), then the series resistor RS should be less than or equal to 300 Ω. DVDD TAS3204 External Microcontroller IP RP SDA SCL IP RP VI(SDA) VI(SCL) Figure 11-7. I2C Pullup Circuit (With No Series Resistor) DVDD TAS3204 External Microcontroller RP SDA or SCL VI RS VS (1) (2) IP (2) RS (2) (1) VS = DVDD × RS/(RS – RP). When driven low, VS