TAS3208PZP

TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE Check for Samples: TAS3208 FEATURES 1 • • 2 • • • • • • • • • • Digital Audio Processor Fully Programmable With Graphical, Drag-and-Drop PurePath Studio™ Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48) Five Simultaneous Operations Per Clock Cycle Usable 768 Words Data RAM (48 Bit), Usable 1K Coefficient RAM (28 Bit) Usable 2.5K Program RAM 360 ms at 48 kHz, 17K Words 24-Bit Delay Memory Slave Mode Fs is 44.1 kHz and 48 kHz Master Mode Fs is 48 kHz Analog Audio Input/Output – 10:1 Stereo Analog Input MUX – Stereo Analog Pass-Through Channel – Stereo, Single-Ended ADC (93 dB DNR Typical) – Six Single-Ended DACs (97 dB DNR Typical) – Stereo Headphone Amplifier, 24-mW Power Output into 16 Ω, 100 pF • • • Digital Audio Input/Output – Three Synchronous Serial Audio Inputs (Six Channels) – Two Synchronous Serial Audio Outputs (Four Channels) – Input and Output Data Formats: 16-, 20-, or 24-Bit Data Left, Right, and I2S – SPDIF Transmitter System Control Processor – Embedded 8051 WARP Microprocessor – Programmable Using Standard 8051 C Compilers – Four Programmable GPIO Pins General Features – Two I2C Ports for Slave or Master Download – Single 3.3-V Power Supply – Integrated Regulators APPLICATIONS • • • • • • Flat-Screen TVs MP3 Players/Music Phone Docks Speaker Bars Mini/Micro Component Systems Automotive Head Units Musical Instruments DESCRIPTION The TAS3208 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable 48-bit digital audio processor, 10:1 stereo analog input MUX, stereo ADC, six DACs, and other analog functionality. The TAS3208 is programmable with the graphical PurePath Studio™ suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop development environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3208’s digital audio processing core. TAS3208 processing capability includes speaker equalization and cross over, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third party or TI royalty-free algorithms. The TAS3208 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. A stereo, 93-dB DNR ADC and six 97-dB DNR DACs ensure that high-quality audio is maintained through the whole signal chain. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Studio, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com The TAS3208 is composed of seven functional blocks: • Clock and serial data interface • Analog input and output • M8051 WARP controller, serial control interface, and device control • Audio DSP – digital audio processing • Power supply • Internal references Figure 1 shows the functional structure of the TAS3208. 10 pf 512 Fs AVSS AVSS TBD Rbias Rbia s TBD 512Fs OSC 10 pf MCLKIN MCLKOUT Clock Control SCLKIN LRCLKIN SCLKOUT SCLKI LRCLKI SDIN 1 SDIN 2 SDIN 3 SAP IN MUTEZ Audio processing LRCLKOUT Control SDA 1 I 2C SPDIF OUT / SDOUT 2 3:1 MUX SPDIF SCL 1 SDA 2 SDOUT 1 SAP OUT 2 SPDIF IN 8051 SCL 2 DAC Mod CS GPIO 1-4 HP AMP 2 HP OUT L / R 10 ch stereo Analog Inputs 33K 2.8 VRMS 0.8 uF 1VRMS A -MUX 10 :1 6 CH DAC 2CH ADC 2 DACOUT 2L/ R 2 DACOUT 1 L/ R 2 LINEOUT 1L/R 2 A- MUX 11:1 10 ch stereo 16 Ohm 10 K ohm 2 10 ch stereo Analog line Input 47 220 uF Apply to all Line and DAC outputs 2.2 uF 10K ohm Line outputs 1V DAC outputs 0.9 V RMS( MAX ) RMS( MAX ) Figure 1. Block Diagram 2 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com The TAS3208 may be used with an external asynchronous sample rate converter (ASRC) to accommodate asynchronous serial inputs at different sampling rates (see Figure 2). 512 Fs Rbi as Rbias TBD 10pf 512Fs OSC AVSSAVSS TBD 10pf MCLKIN MCLKOUT Clock Control SCLKIN LRCLKIN SCLKOUT External ASRC SDIN1A SDIN2B SCLKI MUX SDI1 LRCLKI SDO 1 SDIN3B SDIN4B SDI2 SDO 2 SDIN 2 SDI3 SDO 3 SDIN 3 SCLKA LRCLKA SCLKI MCLKA SCLKB LRCLKB MUX SDIN 1 LRCLKI MCLKI SAP IN Audio processing MUTEZ Control MCLKOUT SDA2 SPDIF 2 I C SPDIF OUT / SDOUT 2 3:1 MUX SCL1 SCLKOUT LRCLKOUT LRCLKOUT SCLKO LRCLKO MCLKO SDA1 MCLKB SDOUT 1 SAP OUT 2 SPDIF IN 8051 SCL 2 DAC Mod CS GPIO 1-4 HP AMP 2 HP OUT L / R 2 10 ch stereo Analog Inputs A - MUX 10 :1 6CH DAC 2CH ADC 2 DACOUT 2L/ R 2 DACOUT 1L/ R 2 LINEOUT 1L/R 2 A- MUX 11:1 10 ch stereo Figure 2. Interface to External ASRC Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 3 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DVDD1 AVDD_OSC VR_ANA XTAL_OUT XTAL_IN AVSS_ESD AVDD_HP HPOUTR AVSS_HP HPOUTL AVDD_HP AVDD_DAC AVSS_DAC DACOUT2R DACOUT2L DACOUT1R DACOUT1L LINEIN1R LINEIN1L AVSS_LO TEST TEST TEST TEST AVDD_REF PZP PACKAGE (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 V1P5_REF BG_REF BIAS_REF AVSS_ADC/REF AVDD_ADC LINEIN10R LINEIN10L AVSS_LI LINEIN9R LINEIN9L AVDD_LI LINEIN8R LINEIN8L AVSS_LI LINEIN7R LINEIN7L AVDD_LI LINEIN6R LINEIN6L AVSS_LI LINEIN5R LINEIN5L AVDD_LI LINEIN4R LINEIN4L MCLKIN DVSS3 DVDD3 I2C_SDA2 I2C_SCL2 I2C_SDA1 I2C_SCL1 CS GPIO1 GPIO2 MUTE RESET DVSS4 DVDD4 DVSS5 VR_DIG2 AVSS_ESD LINEIN1L LINEIN1R AVDD_LI LINEIN2L LINEIN2R AVSS_LI LINEIN3L LINEIN3R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DVSS1 VREG_EN STEST TEST TEST GPIO4 GPIO3 MCLKOUT LRCLKOUT SCLKOUT SDOUT1 SDOUT2/SPDIFOUT DVDD2 VR_DIG1 DVSS2 SPDIF_IN TEST TEST TEST TEST SDIN3 SDIN2 SDIN1 LRCLKIN SCLKIN Table 1. ORDERING INFORMATION PACKAGE (1) TA (2) ORDERABLE PART NUMBER TAS3208IPZP –40°C to 85°C TQFP – PZP –20°C to 70°C (1) (2) 4 Tape and reel TAS3208IPZPR TAS3208PZP TAS3208PZPR TOP-SIDE MARKING TAS3208IPZP TAS3208PZP Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 2. TERMINAL FUNCTIONS TERMINAL NO. NAME I/O TERMINATION (1) DESCRIPTION 1 DVSS1 P 2 VREG_EN DI 3 STEST DI Pulldown 4, 5, 17, 18, 19, 20 TEST – Pulldown 6 GPIO4 DIO Pulldown General-purpose input/output 4 7 GPIO3 DIO Pulldown General-purpose input/output 3 8 MCLKOUT DO Master clock output 9 LRCLKOUT DO Left/right (frame) clock output 10 SCLKOUT DO Serial audio data clock output 11 SDOUT1 DO Serial digital audio data output 1 12 SDOUT2/ SPDIF_OUT DO Serial digital audio data out 2/SPDIF output 13 DVDD2 P 3.3-V digital power 14 VR_DIG1 P Pinout of internal regulator. A 4.7-µF low-ESR capacitor should be connected between this pin and digital ground. This terminal must not be used to power external devices. (1) Digital ground Voltage regulator enable Test pin to reconfigure pins 15 DVSS2 P Digital ground 16 SPDIF_IN DI SPDIF input 21 SDIN3 DI Serial digital audio data input 3 22 SDIN2 DI Serial digital audio data input 2 23 SDIN1 DI Serial digital audio data input 1 24 LRCLKIN DI Left/right (frame) clock input 25 SCLKIN DI Serial audio data clock input 26 MCLKIN DI Master clock input 27 DVSS3 P Digital ground 28 DVDD3 P 3.3-V digital power master 29 I2C_SDA2 DIO I2C serial data master 30 I2C_SCL2 DIO I2C serial clock slave 31 I2C_SDA1 DIO I2C serial data slave 32 I2C_SCL1 DIO I2C serial clock 33 CS DI 34 GPIO1 DIO Chip select General-purpose input/output 1 35 GPIO2 DIO General-purpose input/output 2 36 MUTE DI Pullup Mute device 37 RESET DI Pullup Reset 38 DVSS4 P Digital ground 39 DVDD4 P 3.3-V digital power 40 DVSS5 P 3.3-V digital power 41 VR_DIG2 P Pinout of internal regulator. A 4.7-µF low-ESR capacitor should be connected between this pin and digital ground. This terminal must not be used to power external devices. 42 AVSS_ESD P Analog ESD ground 43 LINEIN1L AI Left-channel analog input 1 All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns (166 kΩ) . The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups at logic 1 input; pulldowns at logic 0 input). Devices that drive inputs with pullups must be able to sink 20 µA while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be able to source 20 µA while maintaining a logic 1 drive level. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 5 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 2. TERMINAL FUNCTIONS (continued) TERMINAL 6 I/O TERMINATION (1) DESCRIPTION NO. NAME 44 LINEIN1R AI Right-channel analog input 1 45, 53, 59, 65 AVDD_LI P 3.3-V analog power 46 LINEIN2L AI Left-channel analog input 2 47 LINEIN2R AI Right-channel analog input 2 48, 56, 62, 68 AVSS_LI P Analog ground 49 LINEIN3L AI Left-channel analog input 3 50 LINEIN3R AI Right-channel analog input 3 51 LINEIN4L AI Left-channel analog input 4 52 LINEIN4R AI Right-channel analog input 4 54 LINEIN5L AI Left-channel analog input 5 55 LINEIN5R AI Right-channel analog input 5 57 LINEIN6L AI Left-channel analog input 6 58 LINEIN6R AI Right-channel analog input 6 60 LINEIN7L AI Left-channel analog input 7 61 LINEIN7R AI Right-channel analog input 7 63 LINEIN8L AI Left-channel analog input 8 64 LINEIN8R AI Right-channel analog input 8 66 LINEIN9L AI Left-channel analog input 9 67 LINEIN9R AI Right-channel analog input 9 69 LINEIN10L AI Left-channel analog input 10 70 LINEIN10R AI Right-channel analog input 10 71 AVDD_ADC P 3.3-V analog power 72 AVSS_ADC/REF P Analog ground 73 BIAS_REF AO Pin should be tied to analog ground with 22 kΩ ± 1%. 74 BG_REF AO Band-gap output. Must be tied to ground with 1-µF low-ESR capacitor. 75 V1P5_REF AO Common-mode output. Must be tied to ground with 1-µF low-ESR capacitor. 76 AVDD_REF P 77, 78, 79, 80 TEST – 3.3-V analog power 81 AVSS_LO P 82 LINEOUT1L AO Analog ground Left-channel analog output 1 83 LINEOUT1R AO Right-channel analog output 1 84 DACOUT1L AO Left-channel digital-to-analog converter output 1 85 DACOUT1R AO Right-channel digital-to-analog converter output 1 86 DACOUT2L AO Left-channel digital-to-analog converter output 2 87 DACOUT2R AO Right-channel digital-to-analog converter output 2 88 AVSS_DAC P Analog ground 89 AVDD_DAC P 3.3-V analog power 90 AVDD_HP P 3.3-V analog power 91 HPOUTL AO 92 AVSS_HP P 93 HPOUTR AO 94 AVDD_HP P 3.3-V analog power 95 AVSS_ESD P Analog ground 96 XTAL_IN DI External crystal input Left-channel headphone output Analog ground Right-channel headphone output Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 2. TERMINAL FUNCTIONS (continued) TERMINAL I/O TERMINATION (1) DESCRIPTION NO. NAME 97 XTAL_OUT DO 98 VR_ANA P Pinout of internal regulator. A 4.7-µF low-ESR capacitor should be connected between this pin and digital ground. This terminal must not be used to power external devices. 99 AVDD_OSC P 3.3-V analog power 100 DVDD1 P 3.3-V digital power External crystal output Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 7 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Clocks The TAS3208 can be configured as either the clock master or clock slave depending on the settings in the clock configuration register. By default, the TAS3208 is configured as the clock master. Figure 3 shows the block diagram of the TAS3208 clocks. SDA I2C Sampling Clock (N = 0) DIV by 2^N Digital Signal Processor (DSP) I2C Module DIV by (M+1) N[2:0] DSP_CLK (135MHz) DIV BY 4 DIV by 10 I2C Master SCL Clock (M = 8) M[2:0] 2816Fs DPLL (11x) SCL 8051uC & Control MICRO_CLK (33MHz) SPDIF _CONTROL_REG_IN[ ] CMS 512Fs OSC DIV BY 2 256Fs DIV BY 4 128Fs DIV BY 8 64Fs DIV BY 512 Fs Parallel Data from DSP SPDIF _L[23:0] Parallel Data from DSP SPDIF _R[23:0] MCLKIN DIV BY 2 0 SPDIF Transmitter SPDIF_CLK spdif_tx_out (Audio Output Select - Control Bits [1:0] from SPDIF Control Register : 0x16) 1 OUTMUX [1:0] CMS (Clock Master /Slave Selection ) MCLKIN 256Fs MCLKOUT 1 64Fs 00 1* CMS SCLKIN SPDIF_MUTE (Mute Control Register : 0x09) 01 0 SCLKOUT 0 0 1 SPDIF_OUT/ SDOUT2 SPDIF _IN 0 1 Data from DSP Ch 1[23:0] Data from DSP Ch 2[23:0] CMS LRCLKIN Fs Data from DSP Ch 3[23:0] Data from DSP Ch 4[23:0] 0 1 SAPOUT_MUTE [1:0] OW[1:0] (SAP Output Word Size ) OM[1:0] (SAP Output Mode ) IM[1:0] ON (Output Normalization Enable) SDOUT 1 SAP OUT (Transmitter ) LRCLKOUT (Recreation / Normalization ) sdout2 LRCLKOUT Data to DSP Ch 1[23:0] SDIN 1 Data to DSP Ch 2[23:0] SDIN 2 SDIN 3 IM[1:0] (SAP Input Mode ) IW[1:0] (SAP Input Word Size ) Data to DSP Ch 3[23:0] SAP IN (Receiver ) Data to DSP Ch 4[23:0] Data to DSP Ch 5[23:0] Data to DSP Ch 6[23:0] Figure 3. Clocking System Digital Audio Interface The TAS3208 has three digital inputs that accept discrete I2S, discrete left-justified, and discrete right-justified PCM data. The TAS3208 has two digital outputs that provide discrete I2S, discrete left-justified, and discrete right-justified PCM data.The second digital output can also be configured to provide SPDIF encoded PCM data. The TAS3208 has a SPDIF input that is capable of routing an SPDIF-encoded signal through the device. This input is not processed by the digital audio processor (DAP). The clocking system for the device is shown in Figure 4. 8 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com 2 I C Sub Address x 00 31 25 23 24 21 18 16 15 13 11 9 5 7 3 1 0 S Slave Addr Ack Sub Addr Ack Res Res CMS Ack Res Res Res ON Ack Res OW Res IW Ack Res OM Res IM Ack CMS 0 1 ON 0 1 IM[1] 0 0 CLOCK MASTER SELECT Clock slave mode Master mode IM[0] INPUT SAP MODE 0 Left-justified Right-justified 1 2 1 0 IS 1 1 Reserved OM[1] OM[0] OUTPUT SAP MODE 0 0 Left-justified Right-justified 1 0 SAP OUTPUT NORMALIZATION Normalization disable Normalization enable 2 1 0 IS 1 1 Reserved IW[0] INPUT SAP WORD SIZE 0 16-bit 20-bit 1 IW[1] 0 0 1 0 24-bit 1 1 Reserved OW[1] OW[0] OUTPUT SAP WORD SIZE 0 0 16-bit 20-bit 1 0 1 0 24-bit 1 1 Reserved 2 I C Sub Address x 01 31 15 23 7 6 S Slave Addr Ack Sub Addr Ack Res Ack Res Ack Res Ack Res M 2 0 N Ack Figure 4. Clocking System I2C Mapping Clock Master Operation When configured as the device clock master, an external crystal is used as a reference to an internal oscillator. In this mode of operation, all internal clocks are generated by the oscillator. • LRCLKOUT is fixed at 48 kHz (Fs). • SCLKOUT is fixed at 64 × Fs. • MCLKOUT is fixed 256 × Fs. Clock Slave Operation When configured as the device clock slave, the DAP, MCU, and I2C interface are derived from the external crystal. However, the digital audio clocks are supplied externally. Internal analog clocks for the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are derived from the MCLKIN input. As a result, analog performance depends on the quality of MCLKIN. Degradation in analog performance is to be expected, depending on the quality of MCLKIN. The TAS3208 device does not include any internal clock error or click/pop detection/management. The muting of the outputs at updating of sample-rate-dependent coefficients must be initiated by the host system controller. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 9 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com MCLKOUT, SCLKOUT, and LRCLKOUT are passed through from the clock inputs MCLKIN, SCLKIN, and LCLKIN. • MCLKIN 256 × Fs is supplied externally. • SCLKIN 64 × Fs is supplied externally. • LRCLKIN Fs is supplied externally. NOTE In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLKIN of 32, 44.1, or 48 kHz. The TAS3208 does not support the use of an external (i.e., 24-MHz) clock input into XTALI. Digital Audio Data Formats Serial data is input on pins SDIN3–SDIN1 on the TAS3208, allowing up to six channels of digital audio input. The TAS3208 supports 16-, 20-, or 24-bit data in left, right, or I2S serial data format. By default, all TAS3208 serial digital inputs are configured in the 24-bit I2S format. The serial data input format is configurable via the SAP/Clock Settings register. Serial data is output on pins SDOUT1 and SDOUT2, allowing up to four channels of digital audio output. By default, the SDOUT data format is 24-bit I2S format at the same data rate as the input. The SDOUT1 and SDOUT2 outputs use SCLKOUT and LRCLKOUT signals to provide synchronization. SDOUT2 is multiplexed with an SPDIF output. NOTE To avoid audio artifacts, I2C commands to reconfigure the serial audio port (SAP) should not be issued as stand-alone commands, rather they should be accompanied by mute and unmute commands. The TAS3208 uses the SCLK as a reference for both input and output samples. The negative edge of SCLK is used to output a new data bit, whereas the positive edge of SCLK is used to sample incoming serial data. Discrete I2S Timing I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is LOW for the left channel and HIGH for the right channel. A bit clock running at 64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written most significant bit (MSB) first and is valid on the rising edge of bit clock. The TAS3208 will mask unused trailing data bit positions. 2 2-Channel I S (Philips Format) Stereo Input 32 clks 32 clks LRCLK (note reversed phase) Left Channel Right Channel SCLK MSB LSB MSB LSB 24-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 5 4 3 2 1 0 3 2 1 0 20-Bit Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 5 4 3 2 1 0 16-Bit Mode 15 14 13 12 11 10 A. 9 8 7 6 9 8 7 6 All data are presented in 2s-complement form with MSB first. Figure 5. SAP I2S 64 × Fs Format 10 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Discrete Left-Justified (LJ) Timing Left-justified timing uses an LRCLK to define when the data being transmitted is for the left channel or right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3208 will mask unused trailing data bit positions. 2-Channel Left-Justified Stereo Input 32 clks LRCLK 32 clks Right Channel Left Channel SCLK MSB LSB MSB LSB 24-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 0 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 5 4 3 2 1 0 3 2 0 1 20-Bit Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 5 4 3 2 1 0 16-Bit Mode 15 14 13 12 11 10 A. 9 8 7 6 9 8 7 6 All data are presented in 2's complement form with MSB first. Figure 6. SAP Left-Justified 64 × Fs Format Discrete Right-Justified (RJ) Timing Right-justified timing uses an LRCLK to define when the data being transmitted is for the left channel or right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3208 will mask unused leading data bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input 32 clks LRCLK 32 clks Right Channel Left Channel SCLK MSB LSB MSB LSB 24-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20-Bit Mode 16-Bit Mode A. All data are presented in 2s-complement form with MSB first. Figure 7. SAP Right-Justified 64 × Fs Format Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 11 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com SAP Input and Output Normalization The TAS3208 supports SAP input and SAP output normalization. This supports simultaneous output to left-justified and I2S devices. NOTE The normalization function is only available in slave mode. I2S, Left, or Right Justified 2 I S, Left, or Right Justified External Data Source MCLKIN MCLKOUT SCLKIN SCLKOUT LRCLKIN SDIN TAS3208 LRCLKOUT DAC SDOUT Figure 8. SAP Output Normal Configuration (No Normalization) 12 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com 2 IS External Data Source Left Justified SDOUT Left Justified LRCLK DAC 1 (Left Justified) Left Justified SDIN TAS3208 2 DAC 2 2 (I S) I S LRCLK 2 I S LRCLK SCLK 2 I S SDIN MSB MSB Left Channel Right Channel Left-Justified LRCLK Left-Justified SDOUT MSB MSB Left Channel Right Channel Figure 9. SAP Output Configuration (I2S to Left Normalization ON) Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 13 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Left-Justified LRCLK SCLK Left-Justified SDIN MSB MSB Left Channel Right Channel 2 I S LRCLK 2 I S SDOUT MSB MSB Left Channel MSB Right Channel Left Channel Figure 10. SAP Output Configuration (I2S to Left Normalization OFF) 14 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Left Justified External Data Source I2S SDOUT I2S LRCLK DAC1 (I2S) I2S SDIN TAS3208 Left Justified LRCLK DAC2 (Left Jusitified) Left Justified LRCLK SCLK Left Justified SDIN MSB MSB Left Channel Right Channel I2S LRCLK I2S SDOUT MSB MSB Left Channel Right Channel MSB Left Channel Figure 11. SAP Output Configuration (Left to I2S Normalization ON) Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 15 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com I2 S LRCLK SCLK I2 S SDIN MSB MSB Left Channel Right Channel Left Justified LRCLK Left Justified SDOUT MSB MSB Left Channel Right Channel Figure 12. SAP Output Configuration (Left to I2S Normalization OFF) SPDIF Encoder The SPDIF encoder is a digital audio transmitter designed for use in consumer audio applications. Transmit data rates up to 48 kHz are supported. The SPDIF encoder complies with the IEC 60958 interface standard. The SPDIF encoder creates a multiplexed bit stream containing audio, status, and user data. The multiplexed data format is shown in Figure 14. The data is then biphase mark encoded and output. The hardware architecture of the SPDIF encoder is shown in Figure 13. SDOUT2 Serial Audio Port Transmitter SCLKIN LRCLKIN SDIN Channel Mute Control Serial Audio Port (Receiver) SPDIF Encoder SDOUT2/ SPDIF DAP Control Signals ANALOGIN Analog Interface SPDIF Control Register “0” SPDIF_IN Output Selector Figure 13. SPDIF Encoder Hardware Architecture 16 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Start of Channel Status Block Frame 191 Channel A X Frame 0 Channel B Z Channel A Y Frame 1 Channel B Channel A X Y Channel B One Sub-Frame Bits: 0 78 34 27 28 29 30 31 Aux Data LSB Preamble MSB V U C P Audio Data Validity Data User Data Channel Status Data Parity Bit Figure 14. SPDIF Frame Format SPDIF Encoder Operation The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performs biphase mark encoding of the multiplexed data stream. Audio data for both left and right channels from the DAP are latched at the rising edge of the internal LRCLK, which marks the beginning of next sample cycle. The SPDIF encoder then multiplexes these samples with internally-generated preambles, channel status, user data, validity flag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF control registers, while the user data is fixed to all zero. The biphase mark-encoded signal is then output starting at the next rising edge of the internal LRCLK. The generated SPDIF stream is fixed to consumer-mode linear audio PCM format. While the RESET input is low, the transmitter output (SPDIF_OUT) is forced to logic low level. Upon setting RESET high, the SPDIF encoder remains inactive until the module reset is removed by writing 0 to the RST bit of the control register. Then this module will wait for synchronization with the internal frame clock and start encoding audio data. It is recommended to set all other SPDIF control register bits before releasing the module reset. Transmitter Control Register Table 3 shows the M8051 SFR register map for the SPDIF module control. Table 3. M8051 SFR Register Map ADDR 7 xx00 RST 6 5 3 2 1 CP xx01 xx10 4 CATEGORY SR xx11 VL VR CLKAC 0 EMP L SRCNUM WORDLEN The relationship of the M8051 SFR register map with I2C registers is described in Table 4. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 17 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 4. Relationship of M8051 SFR Register Map With I2C Registers RST 0 1 Module reset Normal operation Reset SPDIF TX module (default) CP 0 1 Copy permit Copy prohibit (default) Copy permit EMP 0 1 Preemphasis No preemphasis (default) 50-/15-µs 2-channel preemphasis CATEGORY Category code 7-bit device category code (default “0101010”) (digital sound processor) L 0 1 Generation status Generation 1 or higher (default) Original SR 00 01 10 11 Sampling rate 44.1 kHz 48 kHz (default) Reserved 32 kHz VL 0 1 Validity for left channel Left-channel data is valid (default) Left-channel data is invalid VR 0 1 Validity for right channel Right-channel data is valid (default) Right-channel data is invalid SRCNUM "0000" "0001" "0010" "0011" ⋮ "1000" Source channel number Not specified 1 2 (default) 3 ⋮ 8 CLKAC "00" "01" "10" "11" Clock accuracy Level II, 1000 ppm Level III, variable pitch shifted Level I, 50 ppm (default) Reserved WORDLEN "0000: "0001" "0010" ⋮ "0100" ⋮ "1000" Others Sample bit size 24 bits (default) 23 bits 22 bits ⋮ 20 bits ⋮ 16 bits Reserved 18 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com I2C Register Map for SPDIF Figure 15 shows system-accessible I2C register mapping for controlling the SPDIF module. The mute control (MTE) uses the same control bits for controlling SDOUT2 mute at subaddress 0x09, and the module reset (RST) is mapped to subaddress 0x10 together with other power-down control bits. Other control bits are mapped to subaddress 0x16. 0 x 09 18 17 31 S Slave Addr Ack Sub Addr Ack 12 11 AMUXes 00000000000000 8 7 10 9 SDOUT1 SDOUT2 0 x 10 8 S Slave Addr Ack Sub Addr Ack 7 6 0 DIT Decode TX-SAP 0 MUTE RSTZ SPDIF-TX 0 . . . 0 DITRST PWRDN CTL 0 1 DACs 00 X Mute Ctl *1 Force Mute Off 10 Force Mute On Decode 31 2 1 Powerdown, disable Powerup, enable SDOUT2 SPDIF_IN “0” 0 x 16 31 30 29 28 27 24 23 22 21 S Slave Addr Ack Sub Addr Ack CP EMP CLKAC WORDLEN RST CP SR VL 20 19 16 15 9 8 7 2 1 0 VR SRCNUM CATEGORY L 000000 OUTMUX EMP CATEGORY L ESFR SR VL VR SRCNUM CLKAC WORDLEN Figure 15. I2C Register to EFSR and Hardware Connection Map Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 19 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Specification Coverage The TAS3208 is covered by the following specifications: • IEC 60956-1: Second Edition, 2004-03 • IEC 60956-3: Second Edition, 2003-01 • IEC 958-2: First Edition, 1994-07 Specification coverage details can be found in Table 5. Table 5. TAS3208 Specification Coverage (1) SPECIFICATION IEC 60958-1 IEC 958-2 SECTION SUPPORTED Yes Auto frame formatting Channel Status (5) Yes First two bits fixed to 00 (consumer, linear PCM) Mode 1 (software info delivery using b32–191 of channel stat) (4.2.2.1–4.2.2.3) No Bits 28–191 fixed to all zero Channel Status – General (5.1) Yes First channel status bit fixed to 0 Channel Status – Application (5.2.1) – Byte0 (control) IEC 60958-3 Yes, with restriction Channel Status – Application (5.2.2) – Byte2 (source and channel number) Yes Channel Status – Application (5.2.2) – Byte3 (sampling freq and clock accuracy) Yes, with restriction Yes, partially Yes, with restriction Category Code Groups (5.3.2) User Data (6) 20 Yes Channel Status – Application (5.2.2) – Byte1 (category) Channel Status – Application (5.2.2) – Byte4 (word length, original sampling rate, Byte0, b1, 6, 7 = “0”) (1) REMARKS Interface Format (4) b0–1: Fixed (00) b2: Register settable b3–5: Register settable b6–7: Fixed (00) Category code is register settable, with default value 0101010L (digital sound processor), but user data is fixed to all zero. b16–19: Register settable b20–23: H/W auto set (1 for left, 2 for right channel) b24–27: Register settable (32, 44.1, 48 kHz only) b28–29: Register settable b32–35 : H/W auto set according to register setting, 24-bit original output sample truncated to the specified word length b36–39 : Fixed to all zero (not indicated) Specifying categories other than 0101010L (digital sound processor), especially those requiring nonzero user data is not recommended. All zero Timing Accuracy (7.2.1) Yes Clock accuracy indication is register settable. Expected to set level I (50 ppm) for master mode (XTAL source) or level II (1000 ppm) for slave mode. Line Driver Characteristics (7.3.2) No Standard output buffer. Needs external SPDIF driver (e.g., optical driver). Other sections of the specification not mentioned here are either considered irrelevant or covered elsewhere. IEC 60958-4 is specific for professional applications and, thus, irrelevant. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Analog Audio Interface The TAS3208 is has ten analog stereo inputs that are multiplexed to one ADC. Additionally, the TAS3208 has one line output that can source any of the ten analog stereo inputs. The TAS3208 has three stereo DACs. The outputs of of DAC3 are designed to be used as a 24-mW headphone amplifier or line driver. The other two DAC outputs are configured as stereo line drivers. Both the ADC and DAC blocks can be placed in power down when not used. Figure 16 shows a block diagram of the analog interface. Stereo Analog-to-Digital Converter (ADC) The TAS3208 has an analog 10:1 input multiplexer and an 11:1 output multiplexer. These can accept analog stereo inputs up to 1 Vrms. The outputs of the multiplexers are the stereo ADC and the line output. The ADC supports a sampling rate of 48 kHz in clock master mode. In clock slave mode, 32-, 44.1-, and 48-kHz sampling frequencies are supported, based on the master clock frequency. Stereo Digital-to-Analog Converters (DACs) The TAS3208 has three stereo DACs. Each DAC can operate a maximum of 48 kHz. The DACs provide a 48-kHz sampling frequency in master mode. In slave mode, 32-, 44.1-, and 48-kHz sampling frequencies are supported, based on the master clock frequency. Two of the DACs are configured for providing line outputs. One of the stereo DACs has the capability to drive either a line out or to be used as a headphone (HP) amplifier. The stereo HP amplifier is designed to drive up to 24 mW per channel into a headphone speaker load of 16 Ω. The headphone output is a single-ended configuration using series 16-Ω resistors and ac-coupling capacitors. The TAS3208 includes a multiplexed stereo line driver output. The input can be selected to use the output of the stereo DAC or one of the ten sets of analog inputs. The line driver is capable of driving up to a 10-kΩ load. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 21 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Line Amp –1 MUX ADC MUX 10:1 LINE IN 10 ch (Stereo) –1 Amp ADC 1 VRMS (single-ended) D2S Line Amp MUX1 MUX 11:1 –1 Amp + DAC 1 –1 – VREF and IBIAS LINEOUT 1 L/R (Stereo) DACOUT 1 L/R (Stereo) VREF D2S Line Amp –1 DACOUT 2 L/R (Stereo) – DAC 2 + D2S HP Amp –1 HPOUT L/R (Stereo) – DAC 3 + Register Map for MUTE Control Pin Name LINEOUT1 13 0x09 MUTE Block BIT 12 MUX1 Pin Name DACOUT1 Pin Name DACOUT2 Pin Name HPOUT MUTE Block BIT 7 6 5 4 BIT 3 DAC 1 MUTE Block BIT DAC 2 MUTE Block 2 DAC 3 DESCRIPTION 0 0 HW Mute control * 1 Force MUTE OFF 1 0 Force MUTE ON Figure 16. Analog Input/Output 22 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Embedded M8051 WARP Microcontroller The embedded M8051 WARP microcontroller provides the overall control for the TAS3208 device. This control includes device initialization, memory loading, I2C transactions, control-pin operations, and participation in most processing tasks requiring multiframe processing cycles. The microcontroller has its own data RAM for storing intermediate values and queuing I2C commands, a fixed boot program ROM, and a programmable program RAM. The microprocessor’s boot program cannot be altered. The microcontroller has specialized hardware for a master and slave interface operation, volume updates, and a programmable interval timer interrupt. M8051 Addressing Modes The 256 bytes of internal data memory address space are accessible using indirect addressing instructions (including stack operations). However, only the lower 128 bytes are accessible using direct addressing. The upper 128 bytes of direct address data memory space are used to access external special function data registers (ESFRs). Register Banks There are four directly addressable register banks, only one of which may be selected at one time. The register banks occupy Internal data memory addresses from 00 hex to 1F hex. Bit Addressing The 16 bytes of internal data memory that occupy addresses from 20 hex to 2F hex are bit addressable. ESFRs that have addresses in the form 1XXXX000 binary are also bit addressable. Scratch Pad Internal data memory occupying direct addresses from 30 hex to 7F hex can be used as scratch-pad registers or for the stack. External Data Memory External data RAM occupies a 64K address space. This space contains ESFRs. ESFRs permit access and control of the hardware features and internal interfaces of the TAS3208 DSP. M8051 Boot-Up Sequence Figure 17 shows the boot-up sequence. M8051 MCU ROM code follows this sequence after device reset release. After the micro completes the boot-up application code (RAM code), the microcontroller switches the program counter from ROM to RAM code by pc_source(esfr - 0xFD). Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 23 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Any State Reset State RESET = False Start-up Oscillator Initialize DPLL RESET = True PLL Locked and Stable DAP -> Idle uP -> Initialization I2C BUS -> HIGH uP Flushs Internal RAM RAM Flushed RAM Flushed uP -> Cmd to Flush Delay Memory uP Flushs External RAM Delay Memory Flush command issued uP initialize its variables Variables initialized uP Sets default H/W configuration Default Values Loaded RAM Flushed uP Flushs DAP Instruction RAM uP Flushs uP Instruction RAM RAM Flushed uP Flushs DAP Coef/Data RAM RAM Flushed Enable I2C Master mode EEPROM Load Process Setup I2C Master I /F 3 Reads tried OR SCL, SDA = LOW for 1ms detected Disable I 2C Master mode GPIO1 = Low Check GPIO 1 Successful Load Zero length data header has been read GPIO1 = High Load default DAP Program and coefficient Loaded Setup I2C Slave I/F Enable DAP Processing start GPIO1 output Low Successful Load Zero length data header has been received Switch ROM to RAM IDLE uP Test command received I2C Slave download process Main IDLE loop Test Processing Routine Slave download command received Start App uP Code Figure 17. Boot-Up Sequence Detailed information about the boot-up sequence is given in Table 6. 24 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 6. Process Description PROCESS STATE ESFR DESCRIPTION DSP → idle uP → initialization I2C bus → high uP flush internal RAM Clear micro internal RAM (256 byte) uP flush external RAM Clear micro external RAM (2048 byte) uP command to flush delay memory clr_dly_ram (0xc0 bit(3)) 1 mute0_t 0 mute1_t 0 mute2_t 0 reset_dac_mod 0xff reset_adc_sinc 0x03 clock_control1 0x0a clock_delay_control2 0x05 clock_delay_sel 0x80 i2s_word_byte 0x22 i2c_mode_byte 0x22 sap_en 1 uP flush uP instruction RAM mem_sel 0x02 Clear uP instruction RAM (16384 byte) uP flush DSP instruction RAM mem_sel 0x01 Clear DSP instruction RAM (3328 W) uP flush DSP lower coefficient/data RAM mem_sel 0x00 Clear DSP lower coefficient RAM (1024 W) and data (48 bit) RAM (768 W) uP initialize variables uP set default H/W configuration Initialize variables Default mutez control IW/OW: 24 bit IM/OM: I2S Setup I2C master interface mode (enable interrupt 10) Enable I2C master interface EEPROM load Disable I2C master mode and enable slave interface i2c_ms_ctl 0 Switch ROM to RAM pc_source 1 Load default DSP Program and coefficient host_dsp 0 GPIO1 output low Switch control MUX to slave I2C port If (gpio_in_3_0 == 1) { Host_dsp = 1; /* keep DSP turned off */ } else { Host_dsp = 0; /* turn on DSP */ } Enable GPIO output mode, and output low Control Pins RESET RESET is an asynchronous control signal that restores all TAS3208 components to the default configuration. When a reset occurs, the digital audio processor (DAP) is put into an idle state and the M8051 MCU starts initialization. A reset can be initiated by inputting logic 0 on the reset pin . A reset will also be issued at power-up sequencing by the internal 1.8-V regulator power subsystem. NOTE There is a 1.3-µs deglitch filter on RESET. During a power up sequencing process, RESET should be held low until the DVDD and AVDD power inputs have reached a voltage of 3 V. As long as RESET is held a logic 0, the device is in the reset state. During this reset state, all I2C and serial data bus operations are ignored. The I2C interface SCL and SDA lines goes HIGH and remain in that state until device initialization has completed. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 25 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Power-Up Sequence The rising edge of the RESET pin begins the initialization of housekeeping functions by clearing memory and setting the default register values. After housekeeping initialization is complete, the TAS3208 enables the master I2C interface. The TAS3208 then uses the master I2C interface to determine if an external memory device is present. External Memory Device Present Using the master I2C interface, the TAS3208 will automatically test to see if an external memory device is at address 1010xxx. The value xxx can be chip selects, other information, or don’t care depending on the EEPROM selected. If an external memory device is present and it contains the correct header information along with one or more blocks of program/memory data, the TAS3208 will automatically download the M8051 MCU program RAM, coefficient, and/or data RAM from the external EEPROM. This download is considered complete when an ‘end of program’ header is read by the TAS3208. The memory block structure of the external memory device is available in Master I2C Load RAM Block Formats. At this point, the TAS3208 will disable the master I2C interface, enable the slave I2C interface, and start normal operation. After a successful download, the M8051 MCU program counter will be reset and the downloaded M8051 MCU and DSP application firmware will control execution. External Memory Device Not Present If no external EEPROM is present or if an error occurred during the external memory device read, the TAS3208 will disable the master I2C interface, enable the slave I2C interface. The default slave configuration will then be loaded from the ROM into the M8051 MCU and DSP. In this default configuration, the TAS3208 will stream audio from input to output if the GPIO1 pin is pulled LOW. NOTE The master and slave interfaces do not operate simultaneously, thus when one interface is enabled, the other is disabled. I2C Chip Select (CS) The CS pin on the TAS3208 allows up to two TAS3208 devices to be addressed by the I2C bus via an external host controller, without the need for external logic. Table 7 and Table 8 list the I2C address for each I2C interface. Table 7. I2C Slave Addressing SLAVE ADDRESS CS 0x68/69 0 0x6A/6B 1 Table 8. I2C Master Addressing SLAVE ADDRESS CS 0xA0/A1 0 0xA2/A3 1 General-Purpose Input/Output (GPIO) Pins The TAS3208 has two level-sensitive GPIO pins, GPIO1 and GPIO2, that are firmware programmable. Upon power up or following a RESET, GPIO1 becomes an input and has a special function as described in GPIO1 Pin Function. 26 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com GPIO1 Pin Function • After RESET or power-up initialization, if no EEPROM is present, a memory error occurs, or SDA and SCL are pulled LOW for 1 ms, then TAS3208 will disable the master I2C interface and enable the slave I2C interface initialization, to load the slave default configuration. – When GPIO1 has been pulled HIGH through a 10-kΩ to 20-kΩ resistor, the TAS3208 will then initialize in the default configuration with the serial data outputs not active. Once the TAS3208 has completed its default initialization procedure, with the Status register updated and the I2C slave interface enabled, GPIO1 will become an output and will be driven LOW. Following the HIGH to LOW transition of GPIO1, the system controller can access the TAS3208 through the I2C interface and read the Status register to determine the load status. If a memory read error occurs, the TAS3208 reports the error in the Status register. – When GPIO1 has been pulled LOW through a 10-kΩ to 20-kΩ resistor to permit a simple functional device test, GPIO1 can be pulled LOW using external logic and a 10-kΩ to 20-kΩ resistor. In this case, once the TAS3208 has completed its default test initialization procedure, with the Status register updated and the I2C slave interface enabled, the TAS3208 will stream audio from the input SDIN1 to outputs SDOUT1 and SDOUT2. At this point, GPIO1 becomes an output and will be driven LOW. If the external logic is no longer driving GPIO1 LOW after the load has completed (≉100 ms following a RESET if no EEPROM is present), the state of GPIO1 can be observed. At this point, the system controller can access the TAS3208 through the I2C interface and read the Status register to determine the load status. NOTE If the GPIO1 pin state is not observed, the only indication that the device has completed its initialization procedure is that the TAS3208 will stream audio and the I2C slave interface has been enabled. NOTE Some I2C masters will hang when they receive a NAC during an I2C transaction. • Once the TAS3208 has been programmed either through a successful boot load or via slave I2C download, the operation of GPIO1 can be programmed to be an input or an output. GPIO Ports In I2C slave mode, the GPIO ports can be used as true general-purpose ports. Each port can be individually programmed via the I2C bus to be either an input or output port. The default assignment for all GPIO ports in I2C slave mode is an input port. When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR of subaddress 0x0C to logic 1, the logic-level output is set by the logic level programmed into the appropriate bit in bit field GPIO IN OUT. The I2C bus then controls the logic output level for those GPIO ports assigned as output ports. When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field GPIODIR to logic 0, the logic input level into the GPIO port is written to the appropriate bit in bit field GPIO IN OUT. The I2C bus then can be used to read bit field GPIO IN OUT to determine the logic levels at the input GPIO ports. Whether a given bit in the bit field GPIO IN OUT is a bit to be read via the I2C bus or a bit to be written to via the I2C bus is strictly determined by the corresponding bit setting in bit field GPIODIR. In I2C slave mode, the GPIO input ports are read every GPIOMICROCOUNT micro clocks, as was the case in the I2C master mode. However, parameter GPIO_samp_int does not have a role in I2C slave mode. If a GPIO port is assigned as an output port, a logic 0 bit value is supplied by the TAS3208 for this GPIO port in response to a read transaction at subaddress 0x0C. If the GPIO ports are left in their power turnon default state, they are input ports with a weak pullup on the input to VDSS. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 27 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Watchdog Timer There is a hardware watchdog timer in the TAS3208 that can be programmed in the customer application code to monitor the microprocessor activity. If the watchdog timer expires, it will generate a reset to the 8051 microprocessor. GPIOMICROCOUNT, in subaddress 0x0C, is used in order to trigger GPIO and the monitoring to the DSP diagnostic count. Because of this, the value selected for GPIOMICROCOUNT must be chosen to provide a good tradeoff of between micro overheard and adequate execution frequency of these processes. The default value for this counter is 0x5820 which corresponds to a period of 1.25 ms. Figure 18 shows the GPIO register, the GPOI interface, and a typical user application code implementation of the watchdog timer reset. 2 I C Sub Address x 0C 31 30 27 S Slave Addr Ack Sub Addr Ack WDE Res 24 23 15 0 7 GPIO_samp_int Ack See Note A 8051 uControl MICRO_CLK 25 GPIOMICROCOUNT GPIOMICROCOUNT GPIO IN/OUT GPIO DIR Ack Ack Ack MS BYTE LS BYTE 0 0 1 1 Data_IN_OUT Down Counter LD “0” (default state) enables watchdog timer Reset Watchdog Timer MICRO_CLK 8051 uC Firmware Reset Decode 2^16 Decode 2^16 Data Path Switch ENB GPIO1 Q D Sampling Logic ENB GPIO1 Q D A. Determines how many consecutive logic 0 samples (where each sample is spaced by GPIOMICROCOUNT Micro_clks) are required to read a logic 0 on a GPIO input port Figure 18. GPIO Ports 28 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com I2C Control Interface General I2C Transactions The M8051 microprocessor receives and distributes I2C data to the I2C bus controllers, and participates in most I2C processing tasks requiring multiframe processing cycles. The master and slave interfaces do not operate simultaneously. The I2C communication protocol for the I2C slave mode is shown in Figure 19. Read or Write (by master) Stop (by master) Ack LSB MSB 1 Ack 0 MSB 1 R/W 1 CS1 0 CS0 S Data Byte (by transmitter) Ack Data Byte (by transmitter) Slave Address (By master) LSB Start (by master) S (See Note A) Acknowledge (by TAS3208) I2C_SDA MSB Acknowledge (by receiver) MSB–1 MSB–2 Acknowledge (by receiver) LSB I2C_SCL Start Condition I2C_SDA ↓ while I2C_SCL = 1 A. Stop Condition I2C_SDA ↑ while I2C_SCL = 1 Bits CS1 and CS0 in the TAS3208 slave address are compared to the logic levels on pins CS0 and CS1 for address verification. This provides the ability to address up to four TAS3208 chips on the same I2C bus. Figure 19. I2C Slave-Mode Communication Protocol The I2C bus employs two signals – SDA (data) and SCL (clock) – to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data be transferred in byte (8-bit) format with the MSB transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a Start condition on the bus and ends with the master device driving a Stop condition on the bus. The bus uses transitions on the data (SDA) terminal while the clock is HIGH to indicate Start and Stop conditions. A HIGH-to-LOW transition on SDA indicates a Start, and a LOW-to-HIGH transition indicates a Stop. Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The slave holds SDA LOW during the acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes that can be transmitted between Start and Stop conditions. When the last word transfers, the master generates a Stop condition to release the bus. A read transaction requires that the master device first issue a write transaction to give the TAS3208 the subaddress to be used in the read transaction that follows. This subaddress assignment write transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be written. For write transactions, the subaddress must always be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If a subaddress assignment's only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3208 as another subaddress replacing the one previously written. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 29 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Multiple Byte Write A multiple byte data write transfer is identical to a single byte data write transfer, except that multiple data bytes are transmitted by the master device to slave (see Figure 20). After receiving each data byte, the TAS3208 will respond with an acknowledge bit. Start Condition Acknowledge A6 A5 SS A1 A0 R/W Ack Acknowledge A7 A6 2 SS A1 A0 Ack SS D0 Ack First Data Byte Sub Address I C Device Address and Read/ Write Bit D7 Acknowledge Stop Condition Acknowledge Acknowledge D7 SS D0 D7 Ack SS D0 Ack Last Data Byte Other Data Bytes Figure 20. Multiple Byte Write Transfer Multiple Byte Read A multiple byte data read transfer is identical to a single byte data read transfer, except that multiple data bytes are transmitted by the TAS3208 to the master device (see Figure 21). Except for the last data byte, the master device will respond with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge A6 2 SS A0 R/W Ack I C Device Address and Read/Write Bit A7 Stop Condition Acknowledge SS A0 Sub Address Ack Acknowledge A6 2 SS A0 R/W Ack I C Device Address and Read/Write Bit D7 Acknowledge SS D0 First Data Byte Ack D7 Not Acknowledge Acknowledge SS D0 Ack Other Data Bytes D7 SS D0 Ack Last Data Byte Figure 21. Multiple Byte Read Transfer Random I2C Transactions Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For random I2C read commands, the TAS3208 responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in accordance with the data assignment for that address space. For example, if a write command is received for a biquad subaddress, the TAS3208 expects to see five 32-bit words. If fewer than five data words have been received when a Stop command (or another Start command) is received, the data received is discarded. Sequential I2C Transactions The TAS3208 supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS3208. For I2C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a Stop or Start is transmitted, determines how many subaddresses are written to. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data is discarded. Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master does not issue enough data received acknowledges to receive all the data for a given subaddress, the master device simply does not receive all the data. 30 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com If the master device issues more data received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both sequential and random, can impose wait states. For the standard I2C mode (SCL = 100 kHz), worse-case wait state times for an 8-MHz microprocessor clock is on the order of 2 µs. Nominal wait state times for the same 8-MHz microprocessor clock is on the order of 1 µs. For the fast I2C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worse-case wait state times can extend up to 10.5 µs in duration. Nominal wait state times for this same case lie in a range from 2 µs to 4.6 µs. Increasing the microprocessor clock frequency lowers the wait state times and for the standard I2C mode, a higher microprocessor clock can totally eliminate the presence of wait states. For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I2C mode, higher microprocessor clocks shortens the wait state times encountered, but does not totally eliminate their presence. I2C Master-Mode Operation I2C master-mode operation is enabled following a reset or power-on reset. The TAS3208 uses the master mode to download from EEPROM the memory contents for: • Microprogram memory • Micro extended memory • DSP program memory • DSP coefficient memory • DSP data memory The TAS3208, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3208 operates as an I2C master, it generates a repeated Start without an intervening Stop command while downloading program and memory DATA from an external EEPROM. When a repeated Start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to quickly transfer large blocks of data. Repeat Start Condition Start Condition Acknowledge A6 2 SS A0 R/W Ack I C Device Address and Read/Write Bit A7 Stop Condition Acknowledge SS A0 Ack Acknowledge A6 2 Sub Address SS A0 R/W Ack I C Device Address and Read/Write Bit D7 Acknowledge SS D0 First Data Byte Ack D7 Not Acknowledge Acknowledge SS D0 Ack Other Data Bytes D7 SS D0 Ack Last Data Byte Figure 22. Multiple-Byte Read Transfer The TAS3208 will query the bus for an I2C EEPROM at an address 1010xxx. The value xxx can be chip selects, other information, or don’t cares depending on the EEPROM selected. The first act of the TAS3208 as master will be to transmit a Start condition along with the device address of the I2C EEPROM, with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address byte and the TAS3208 sends a subaddress byte, which the EEPROM will acknowledge. Most EEPROMs have at least 2-byte addresses and will acknowledge as many as are appropriate. At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3208 acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. The memory load information starts with reading the header and data information that starts at subaddress 0 of the EEPROM. This information must be stored in a sequential memory addresses with no intervening gaps. The data block is contiguous blocks of data that immediately follow the headers' locations. The TAS3208 memory data can be stored and loaded in (almost) any order. Additionally this addressing scheme permits portions of the TAS3208 internal memories to be loaded. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 31 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com I2C EEPROM Memory Map Block Header 1 Data Block 1 Block Header 2 Data Block 2 … Block Header N Data Block N Figure 23. EEPROM Address Map The TAS3208 will sequentially read EEPROM memory and load its internal memory unless it does not find a valid memory header block, is not able to read the next memory location because the end of memory was reached, detects a checksum error, or reads a end-of-program header block. When it encounters a valid header or read error, the TAS3208 will attempt to read the header or memory location three times before it determines that it has an error. If the TAS3208 encounters a checksum error, it will attempt to reread the entire block of memory two more times before it determines that it has an error. NOTE Once the microprogram memory has been loaded, it can not be reloaded until the TAS3208 has been reset. If an error is encountered, the TAS3208 terminates its memory load operation, loads the default configuration for both the M8051 MCU and DSP from the embedded ROM, and disables further master I2C bus operations. If an end-of-program data block is read, the TAS3208 has completed the initial program load. The I2C master mode utilizes the starting and ending I2C checksums to verify a proper EEPROM download. The first 16-bit data word received from the EEPROM is the I2C checksum at subaddress 0x00. It is stored and compared against the 16-bit data word received for last subaddress, the ending I2C checksum, and the checksum that is computed during the download. These three values must be equal. If the read and computed values do not match, the TAS3208 sets the memory read error bits in the Status register and repeats the download from the EEPROM two more times. If the comparison check again fails the third time, the TAS3208 sets the microprogram to the default value. NOTE When acting as an I2C master, the data rate transfer is fixed at 375 kHz. 32 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com I2C Slave Mode Operation The I2C slave mode is the mode that is used to change configuration parameters during operation and perform program and coefficient downloads from a master device. The latter can be used to replace the I2C master mode EEPROM download. The TAS3208 uses the slave mode to load the memory contents for the: • Microprogram memory • Micro extended memory • DSP program memory • DSP coefficient memory • DSP data memory • Update coefficient and other control values • Read status flags The TAS3208 support both random and sequential I2C transactions. The TAS3208 I2C slave address is 011010X, where the first six bits are the TAS3208 device address and the final one bit is set by the TAS3208 internal microprocessor at power up. The internal microprocessor derives the last bit from an external pin (CS),which is pulled up or down to create two unique addresses for control of multiple TAS3208 part applications. The pulldown resistance of CS creates a default 00 address when no connection is made to the pin. The TAS3208 I2C block does respond to the broadcast address (00h). NOTE When acting as an I2C slave, data-rate transfer is determined by the master device on the bus. However, the setting of I2C parameter N at subaddress 0x01 does play a role in setting the maximum possible data transfer rate. In the I2C slave mode, bit rates other than (and including) the I2C-specific 100-Kbps and 400-Kbps bit rates can be obtained, but N must always be set so that the oversample clock into the I2C master and slave controllers is at least a factor of 20 higher in frequency than SCL. N = 0 is a special case. When N = 0, a mode is enabled that detects I2C frames and enables the TAS3208 I2C interface to reset and continue operation after receiving an invalid I2C frame. Table 9. I2C Slave Addresses SLAVE ADDRESS CS 0x68/69 0 0x6A/6B 1 Table 10. I2C Master Addresses SLAVE ADDRESS CS 0xA0/A1 0 0xA2/A3 1 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 33 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Digital Signal Processor (DSP) Arithmetic Unit Overview The arithmetic processor is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary features are: • Two pipe parallel processing architecture – 48-bit data path with 76-bit accumulator – Hardware single-cycle multiplier (28 × 48) – Three 48-bit general-purpose data registers – One 28-bit coefficient register – 48-bit adder – 28-bit adder – Shift right, shift left – Bimodal clip – Log2/Alog2 – Magnitude truncation • Read/read/write single-cycle memory access • Data input is 48-bit 2s complement multiplexed in from SAP immediately following FSYNC pulse. • Data output is four 32-bit 2s-complement buses. • Separate control for writing to delay memory • Separate coefficient memory (28 bit) and data memory (48 bit) • Linear Feedback Shift Register (LFSR) in the instruction register doubles as a random number generator in normal operating mode. • Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into the same memory space for convenient addressing by the micro. • Memory interface block contains four pointers – two for data memory and two for coefficient memory. Data Format Figure 24 shows the data word structure of the arithmetic unit. Eight bits of overhead or guard bits are provided at the upper end of the 48-bit word, and 16 bits of computational precision or noise bits are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with the MSB abutting the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed data samples. The arithmetic engine is a 48-bit (25.23 format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve 48-bit words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products are to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC operation to maintain precision in the intermediate computational stages. To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations, intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow will correct the overflow condition. The memory banks include a dual-port data RAM for storing intermediate results, a coefficient RAM, and a fixed-program ROM. Only the coefficient RAM, assessable via the I2C bus, is available to the user. 34 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com 47 S S S S S Overhead/Guard Bits 40 39 S 32 31 16-bit audio 18-bit audio 20-bit audio 24-bit audio 24 23 22 21 20 19 16 15 32-bit audio 8 7 Precision/Noise Bits 0 Figure 24. Arithmetic Unit Data Word Structure 8-Bit ALU Operation (without saturation) 10110111 (–73) + 11001101 (–51) –73 + 10000100 (–124) Rollover + 11010011 (–45) 01010111 (57) + 00111011 (59) 10010010 (–110) –51 –124 + –45 –169 + 59 –110 Figure 25. DSP ALU Operation With Intermediate Overflow Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 35 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com DAP Data Path Data Representation D23 D22 ------------ D1 D0 Input 24-Bit Data 8-Bit Headroom and 16-Bit Noise 0 ... 0 D23 D22 ------------ D1 D0 0 ... 0 47–40 39 ------------------16 15–0 Coefficient Representation 27–23 Scaling Headroom Multiplier Output 75–71 70–63 5 8 22 --------------- 0 Data (24-Bits) Fractional Noise 62–39 12 12 38–31 30–0 8 31 48-Bit Clipping POS48 = NEG48 = 0x7F_F 0x80_0 FFF_FFFF 000_0000 _FF _00 32-Bit Clipping POS40 = NEG40 = 0xXX_ 0xXX_ 7FFF_FFFF 8000_0000 _XX _XX 28-Bit Clipping POS20 = NEG20 = 0xXXXXX_ 0xXXXXX_ 7FFF_FFF 8000_000 Figure 26. DSP Data-Path Data Representation 36 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com 28 28 Micro Mem IF 24 24 DATA RAM 1024 X 24 28 48 28 DATA RAM 768 X 48 48 COEF RAM 1.2 K X 24 28 VOL (5 LSBs) VOL 48 48 DI (3 LSBs) 28 48 48 LFS 2 48 48 28 28 48 48 48 48 L B 48 28 48 48 MD MC 48 48 28 LOG, ALOG, NEG, ABS, or THRU Barrel Shift NEG, ABS, or THRU DLYO 76 48 ACC Multiply 76 48 BR LR MR Legend “ZERO” 76 48 48 Operand A 76 76 Register 24 Operand B 24-bit data 28 ADD 28-bit data 32 32-bit data 76 48 48-bit data CLIP 76 Delay RAM DLYI 48 76-bit data Output Register File (DO8–DO8) 32 To Output SAP Figure 27. DSP Data-Path Architecture Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 37 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 DO0 DO1 DO2 www.ti.com DO3 DO4 DO5 DO6 DO7 DO8 Inside core Outside core Micro Data Audio_out1 Audio_out2 Audio_out3 Audio_out4 Audio_out5 Audio_out6 Audio_out7 SDOUT1(L) SDOUT1(R) SDOUT2(L) SDOUT2(R) DAC (TDM) SPDIF(L) SPDIF(R) Audio_out8 Ext_mem (2nd Gen) Figure 28. DSP Output Register Configuration DSP MICRO Coef RAM (1 K x 28 ) 48 -bit Datapath 28 x 48-bit Multiplier 76-bit Accumulator Internal Data RAM (256 x 8 ) Data RAM (768 x 48 ) Memory Interface DSP Controller External Data RAM (2 K x 8 ) Program RAM (3 .25 K x 55 ) 8 -bit MCU (8051 ) Program RAM (16 K x 8 ) A. Delay Memory (17408 x 24 ) Delay Control Memory size K = 1024 Figure 29. DSP, MCU, and Memory Interfaces Delay Memory The delay memory interface (DMIF) is the interface block between the DSP core and the delay memory. The DMIF block’s primary purpose is to keep track of 24 sets of delay memory pointers that are initially set up by the microcontroller through an I2C command(s). Eight of the pointers are used to write/retrieve 48-bit data (full-precision intermediate) and the other 16 for 24-bit data (post quantized). Thus, to support 48-bit word reverb delay, two RAM locations must be used. 38 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com The key features of the delay memory are: • 17408 × 24 delay memory locations • 24 separately addressable pointers • Programmable Start/Stop address on each pointer • Pointers capable of accessing 24-bit or 48-bit words • Single-port access (one pointer access per access cycle) • Access cycle < four DSP clocks • Self clearing – INIT pin used to clear all memory to zero • Fully synchronous • DP1–DP15: 16 24-bit pointers • RP1–RP8: Eight 48-bit (full precision) pointers Since all of the pointers are contiguous, it is only necessary to write the address END point. For example, if DP1 is to be a three-sample delay, the register DP1 should be set to 0x003. If RP1 is to be a three-sample delay, the register RP1 should be set to the value of DP15 + 6. All of the DP16–DP1 and RP8–RP1 registers must be set to a minimum of a one sample delay (one or two words). DP1 Start address is defined as 000x0. DP2 Start address is equal to DP1 end address + 1. RP1 Start address is equal to DP16 end address + 1. RP8 Start address is equal to RP7 end address + 2. Since the Start/Stop address for each pointer is programmable anywhere in the delay RAM's address space, the delay for any one channel can be anywhere in the delay RAM. There is, however, no address space collision avoidance logic to separate the pointers. The user (or micro) must take care to avoid overlapping the address spacing of each pointer. Pointer register address endpoint registers DP16–DP1 and RP8–RP1 are typically written only during the initialization (fast load) mode of the device. Writing to these registers while the TAS3208 DSP core is accessing the pointers may cause the pointers to cross the address space of another pointer. To write to the delay RAM, the TAS3208 DSP core controller must present the data to be written on the PT_DATA bus (LSB always in bit zero of the bus), select the pointer to be accessed by driving the PT_SEL pins, and assert the PT_WZ pin for a minimum of four clocks. The pointer will not increment until a write has been performed and the PT_WZ pin has been deasserted. To perform a read, the PT_OUT bus may be read four clocks after PT_SEL is driven. DSP Instruction Word TAS3208 has a 55-bit instruction word. Each instruction has five independent operations, which can load two operands from data memory and coefficient memory, store the result into data or coefficient memory, and perform two parallel arithmetic operations. 55-BIT INSTRUCTION Data Memory Load Ext ALU First Stage ALU Second Stage 0 P1OP P2OP MOP1 AD1 MOP2 AD2 MOP3 AD3 54 53–49 48–42 41–37 36–27 26–24 23–14 13–10 9–0 Coefficient Memory Load Memory Store Figure 30. Instruction Word The TAS3208 instruction set is a superset of the TAS3208 instruction set, extending the DSP processing capabilities for improved efficiency of FIR operations, as well as extending the addressable memory space. The Ext instruction bit (bit 54) has been added to extend the internal memory address space by one bit, increasing the memory space from 1K to 2K words. The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3208 device, since the 54-bit instruction word required dummy storage of two bits in the EEPROM. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 39 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com TAS3208 instruction word DUM 2 54–55 54-BIT INSTRUCTION ALU First Stage ALU Second Stage P1OP P2OP Data Memory Load MOP1 Coefficient Memory Load AD1 MOP2 AD2 Memory Store MOP3 AD3 5 4 5 10 3 10 4 10 53–49 48–42 41–37 36–27 26–24 23–14 13–10 9–0 Contains two dummy bits in every instruction word of the EEPROM. All TAS3208 tool compilers always ZERO to these dummy bits in the compile EEPROM image. Figure 31. Instruction Word As shown in Figure 32, the extension bit designates an offset of 1K to all three addresses in the instruction word. However, it should be noted that both data and coefficient memory addresses above the 1K boundary are reserved for housekeeping processing tasks. Any attempt to write to these addresses may corrupt the audio output. New “Ext”-ended field 54-BIT INSTRUCTION Data Memory Load Ext ALU First Stage ALU Second Stage 0 P1OP P2OP MOP1 AD1 MOP2 AD2 MOP3 AD3 54 53–49 48–42 41–37 36–27 26–24 23–14 13–10 9–0 Coefficient Memory Load Memory Store Extension bit designates offset of 1K to these address references for LD/ST operations Figure 32. Instruction Word Extension Field DSP Instruction Set Please see the TASxxx Programmer’s Guide for detailed information regarding programming of this device. 40 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) MIN MAX DVDD Supply voltage range –0.5 3.8 V AVDD Supply voltage range –0.5 3.8 V 3.3-V TTL –0.5 VDDS + 0.5 3.3-V analog –0.5 AVDDS + 0.5 1.8-V LVCMOS –0.5 AVDD (2) + 0.5 3.3-V TTL –0.5 VDDS + 0.5 3.3-V analog –0.5 AVDDS + 0.5 –0.5 DVDD (3) + 0.5 –0.5 AVDD (4) + 0.5 VI Input voltage range VO Output voltage range 1.8-V LVCMOS UNIT V V IIK Input clamp current VI < 0 or VI > DVDD) ±20 mA IOK Output clamp current VO < 0 or VO > DVDD ±20 mA Tstg Storage temperature range 150 °C 260 °C –65 Lead temperature 1.6 mm (1/16 in) from case for 10 s (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AVDD is an internal 1.8-V supply derived from a regulator in the TAS3208 chip. Pin XTALI is the only TAS3208 input that is referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI. DVDD is an internal 1.8-V supply derived from regulators in the TAS3208 chip. DVDD is routed to DVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. Pin XTALO is the only TAS3208 output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. AVDD is also routed to AVDD_BYPASS_CAP to provide access to external filter capacitors, but should not be used to source power to external devices. (3) (4) PACKAGE DISSIPATION RATINGS (1) (2) TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING 2.78 W 28.7°C/W 1.22 W (1) (2) PACKAGE TQFP – PZP High-K Board, 105°C junction Refer to the application report PowerPAD ™ Thermally Enhanced Package (literature number SLMA002) RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 3.6 V 3 3.3 3.6 V DVDD Digital supply voltage AVDD Analog supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating ambient air temperature (ensuring parametric) –20 TJ Operating junction temperature –20 3.3-V analog 3.3-V TTL 1.8-V LVCMOS (XTL_IN) 2 1.26 1.95 3.3-V TTL 0.8 1.8-V LVCMOS (XTL_IN) 0.54 25 Product Folder Link(s): TAS3208 V V 70 °C 105 °C Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated UNIT 41 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com AUDIO SPECIFICATIONS – CHANNEL (INPUT TO OUTPUT) TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, clock source from XTALI, AES17 filter, second-order 30-kHz low-pass filter (unless otherwise noted) PARAMETER Overall dynamic range MIN TYP A-in → ADC → DSP → DAC → Lineout A: WTD CONDITIONS 87 92 A-in → MUX → Lineout A-WTD 95 98 MAX UNIT dB AUDIO SPECIFICATIONS – DIGITAL FILTERS TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, clock source from XTALI, AES17 filter, second-order 30-kHz low-pass filter (unless otherwise noted) PARAMETER MIN TYP MAX UNIT ADC Decimation Filter, Fs = 48 kHz Filter gain from 0 Fs to 0.39 Fs Filter gain at 0.4125 Fs Filter gain at 0.45 Fs Filter gain at 0.5 Fs Filter gain from 0.55 Fs to 64 Fs Filter group delay ±0.1 dB –0.25 dB –3 dB –17.5 dB –75 dB 17/Fs s DAC Interpolation Filter, Fs = 48 kHz Pass band ±0.06 0.45 × Fs Transition band 0.5501 × Fs Stop band –65 Stop-band attenuation Filter group delay 42 0.45 × Fs 20 Pass-band ripple 21/Fs Submit Documentation Feedback Hz dB 0.5501 × Fs Hz 7.455 × Fs kHz dB s Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com ELECTRICAL SPECIFICATIONS – ANALOG SECTIONS (1) TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, clock source from XTALI, AES17 filter, second-order 30-kHz low-pass filter (unless otherwise noted) PARAMETER Stereo MUX Input/ADC Channel TEST CONDITIONS MIN TYP MAX UNIT 1 1.15 Vrms 1.43 1.5 1.57 90 93 dBA –75 –80 dB dB 1-kHz sine-wave input Full-scale input voltage (0 dB) Input common-mode voltage Over recommended operating conditions DNR –60-dB full-scale input applied at line inputs, A-weighted THD + N 1-kHz, –4-dB full-scale input PSRR 1 kHz, 100 mVpp on AVDD Channel separation 1 kHz Input resistance 51 57 –80 –90 14.6 18.33 Input capacitance DAC Channel/DAC Output dB 22 0.81 10 pF 0.9 Vrms –10 Gain error Output common mode Over recommended operating conditions DNR –60-dB full-scale input applied at line inputs, A-weighted THD + N –1-dBFS input, 0-dB gain PSRR 1 kHz, 100 mVpp on AVDD, VGND powered down 10 1.57 1.5 95 97 dBA V –80 –90 dB 50 56 dB pF Load resistance 10 Channel separation kΩ –81 –84 dB 0.72 0.9 Vrms 80 90 dBA –50 –60 dB 48 54 dB 24 mW 1-kHz sine-wave input, Load = 16 Ω, External series resistance = 16 Ω, Coupling capacitance = 47 µF Full-scale output voltage (0 dB) DNR –60-dB full-scale input applied at Line inputs, A-weighted THD + N 0-dBFS input, 0-dB gain PSRR 1 kHz, 100 mVpp on AVDD , VGND powered down Maximum output power (2) Load capacitance 100 Load resistance pF Ω 16 –70 Channel separation (2) % 1.43 Load capacitance (1) kΩ 1-kHz sine-wave input, Load = 10 kΩ, 10 pF Full-scale output voltage (0 dB) DAC Channel/ Headphone Output V –80 dB When the TAS3208 is operated in slave mode, the internal analog clocks for ADC and DAC are derived from external MCLKIN input. In this case, the analog performance will depend on MCLKIN quality (i.e., jitter, phase noise, etc.). 16-Ω series resistor required in L and R headphone outputs for short-circuit protection. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 43 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com ELECTRICAL SPECIFICATIONS – ANALOG SECTIONS(1) (continued) TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs (audio) = 48 kHz, clock source from XTALI, AES17 filter, second-order 30-kHz low-pass filter (unless otherwise noted) PARAMETER DAC Channel/Headphone Output TEST CONDITIONS MIN TYP Full-scale output voltage (0 dB) DNR –60-dB full-scale input applied at line inputs, A-weighted THD + N 0-dBFS input, 0-dB gain PSRR 1 kHz, 100 mVpp on AVDD, VGND powered down Channel separation Analog Mux in Bypass Mode 1-kHz sine-wave input, Load = 10 kΩ, 10 pF Mux switching noise LINEIN inputs floating 0.81 0.9 Vrms 80 90 dBA –70 –82 dB 48 54 dB –70 –80 dB –20 Full-scale input voltage (0 dB) Input common-mode voltage 1.43 20 Load resistance 1.15 1.57 V 20 pF 10 Between each line input –80 Submit Documentation Feedback Vrms kΩ –80 0.9 mV 1 Between Lch and Rch Full-scale output voltage (0 dB) 44 UNIT 1.5 Load capacitance Channel separation MAX 1-kHz sine-wave input, Load = 10 kΩ, 10 pF 1 dB dB 1.1 Vrms Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS 3.3-V TTL IOH = –4 mA 1.8-V LVCMOS (XTL_OUT) IOH = –0.55 mA 3.3-V TTL IOL = 4 mA 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance output current 3.3-V TTL MIN MAX UNIT 2.4 V 1.44 0.5 V 0.396 ±20 1.8-V LVCMOS (XTL_IN) µA ±1 IIL Low-level input current (1) IIH High-level input current (2) IDVDD Digital supply current DSP clock = 135 MHz, LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.288 MHz 200 mA IAVDD Analog supply current DSP clock = 135 MHz, LRCLKIN/LRCLKOUT = 48 KHz, XTALI = 24.288 MHz 28 mA IDVDD Digital supply current RESET = LOW 0.1 mA IAVDD Analog supply current RESET = LOW 5 mA (1) (2) 3.3-V TTL 1.8-V LVCMOS (XTL_IN) 3.3-V TTL VI = VIL µA ±1 ±1 VI = VIH µA ±1 Value given is for those input pins that connect to an internal pullup resistor, as well as an input buffer. For inputs that have a pulldown resistor or no resistor, IIL = ±1 µA. Value given is for those input pins that connect to an internal pulldown resistor, as well as an input buffer. For inputs that have a pullup resistor or no resistor, IIH = ± 1 µA. TIMING REQUIREMENTS – MASTER CLOCK SIGNALS over recommended operating conditions (see Figure 33) MIN TYP MAX UNIT 24.576 (512 Fs) (1) fXTALI XTALI frequency (1/ tcyc1) tcyc1 XTALI cycle time (2) fMCLKIN MCLKIN frequency (1/ tcyc2) twMCLKIN MCLKIN pulse duration (3) fMCLKOUT MCLKOUT frequency(1/ tcyc3) trMCLKOUT MCLKOUT rise time CL = 30 pF 10 ns tfMCLKOUT MCLKOUT fall time CL = 30 pF 10 ns twMCLKOUT MCLKOUT pulse duration (4) 0.6 × tcyc3 ns tdMI–MO (1) (2) (3) (4) (5) MHz 1/(512 Fs) ns 256 Fs 0.4 × tcyc2 MHz 0.6 × tcyc2 ns 256 Fs 0.4 × tcyc3 MCLKOUT jitter XTALI master clock source Delay time, MCLKIN rising edge to MCLKOUT rising edge (5) MCLKOUT = MCLKIN MHz 80 ps 17 ns Frequency tolerance is ±100 ppm (or better) at 25°C. tcyc1 = 1/ fXTALI tcyc2 = 1/ fMCLKIN tcyc3 = 1/ fMCLKOUT When MCLKOUT is derived from MCLKIN, MCLKOUT jitter = MCLKIN jitter. MCLKOUT has the same duty cycle as MCLKIN when MCLKOUT = MCLKIN. TIMING REQUIREMENTS – RESET with respect to DVDD power good (see Figure 34) MIN tpgw(L) Minimum pulse duration, RESET low following DVDD = 3.3 V 100 MAX UNIT ms Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 45 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS – RESET control signal parameters over recommended operating conditions (unless otherwise noted) (see Figure 35) MIN trDMSTATE Time to outputs inactive twRESET Pulse duration, RESET active trEMSTATE Time to enable I2C TYP MAX UNIT 100 µs 0 0 (= termination header) YES Status Error? Mem_select Valid Status I = error NO pc_source = 1 PCON = 0x01 Check num_byte RAM Switch Num_byte OK? NG receive mem_load_ctrl (0x04) OK Halt DSP host_dsp = 1 Load Data receive mem_load_data (0x05) Load Received Data to Specified Memory Calculate Checksum NO End Checksum? YES Check Checksum YES Checksum Error? NO Clear Error Status Figure 39. I2C Slave Download Flow Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 55 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 16. M8051 Microcontroller Program RAM and External Data RAM Block Structure (1) REGISTER Control 0x04 Data 0x05 Data 0x05 Data 0x05 (1) 56 BYTE DATA BLOCK FORMAT 1 Checksum MSB 2 Checksum LSB 3 Memory to be loaded 0x00 or 0x01 4 0x00 5 Start memory address MSB 6 Start memory address LSB 7 Total number of byte transferred MSB 8 Total number of byte transferred LSB 1 Datum 1 D7–D0 2 Datum 2 D7–D0 3 Datum 3 D7–D0 4 Datum 4D7–D0 5 Datum 5 D7–D0 6 Datum 6 D7–D0 7 Datum 7 D7–D0 8 Datum 8 D7–D0 1 Datum 9 D7–D0 2 Datum 10 D7–D0 3 Datum 11D7–D0 4 Datum 12 D7–D0 5 Datum 13 D7–D0 6 Datum 14 D7–D0 7 Datum 15 D7–D0 8 Datum 16 D7–D0 1 Datum N-3 D7–D0 2 Datum N-2 D7–D0 3 Datum N-1 D7–D0 4 Datum N D7–D0 5 0x00 6 0x00 7 Checksum MSB 8 Checksum LSB CALC CHECKSUM TOTAL NO. BYTES NOTE If the last data register datum is less than 6 byte, zero data should be filled. Should be zero End checksum is always located here. Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 17. DSP Program RAM Block Structure (1) REGISTER Control 0x04 Data 0x05 Data 0x05 Data 0x05 (1) BYTE DATA BLOCK FORMAT 1 Checksum MSB 2 Checksum LSB 3 Memory to be loaded 0x02 4 0x00 5 Start memory address MSB 6 Start memory address LSB 7 Total number of byte transferred MSB 8 Total number of byte transferred LSB 1 0x00 2 D55–D48 3 D47–D40 4 D39–D32 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 0x00 2 D55–D48 3 D47–D40 4 D39–D32 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 0x00 2 0x00 3 0x00 4 0x00 5 0x00 6 0x00 7 Checksum MSB 8 Checksum LSB CALC CHECKSUM TOTAL NO. BYTES NOTE Program word 1 Program word 2 Should be zero End checksum is always located here. Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 57 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 18. DSP Coefficient RAM Block Structure (1) REGISTER Control 0x04 Data 0x05 Data 0x05 Data 0x05 (1) 58 BYTE DATA BLOCK FORMAT 1 Checksum MSB 2 Checksum LSB 3 Memory to be loaded 0x03 4 0x00 5 Start memory address MSB 6 Start memory address LSB 7 Total number of byte transferred MSB 8 Total number of byte transferred LSB 1 D31–D24 2 D23–D16 3 D15–D8 4 D7–D0 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 D31–D24 2 D23–D16 3 D15–D8 4 D7–D0 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 D31–D24 2 D23–D16 3 D15–D8 4 D7–D0 5 0x00 6 0x00 7 Checksum MSB 8 Checksum LSB CALC CHECKSUM TOTAL NO. BYTES NOTE Coefficient word 1 Coefficient word 2 Coefficient word 3 Coefficient word 4 Coefficient word N or zero Should be zero End checksum is always located here. Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 19. DSP Data Block Structure (1) REGISTER Control 0x04 Data 0x05 Data 0x05 Data 0x05 (1) BYTE DATA BLOCK FORMAT 1 Checksum MSB 2 Checksum LSB 3 Memory to be loaded 0x04 4 0x00 5 Start memory address MSB 6 Start memory address LSB 7 Total number of byte transferred MSB 8 Total number of byte transferred LSB 1 0x00 2 0x00 3 D47–D40 4 D39–D32 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 0x00 2 0x00 3 D47–D40 4 D39–D32 5 D31–D24 6 D23–D16 7 D15–D8 8 D7–D0 1 0x00 2 0x00 3 0x00 4 0x00 5 0x00 6 0x00 7 Checksum MSB 8 Checksum LSB CALC CHECKSUM TOTAL NO. BYTES NOTE Coefficient word 1 Coefficient word 2 Coefficient word 3 Coefficient word 4 Should be zero End checksum is always located here. Shades cells indicate the values included in the checksum/total number of bytes calculation. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 59 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 20. Termination Header Block Structure (1) REGISTER Control 0x04 (1) BYTE DATA BLOCK FORMAT CALC CHECKSUM TOTAL NO. BYTES NOTE 1 Checksum MSB 00 2 Checksum LSB 00 3 Memory to be loaded 00 4 0x00 00 5 Start memory address MSB 00 6 Start memory address LSB 00 7 Total number of byte transferred MSB 00 8 Total number of byte transferred LSB 00 Shades cells indicate the values included in the checksum/total number of bytes calculation. I2C Register Map The I2C register map for ROM advanced code is described in Table 21. Table 21. I2C Register Map (1) SUB ADDRESS REGISTER BYTES 0x00 SAP/Clock Setting 4 See SAP/Clock Setting Register u(31:24), u(23:16), u(15:8), u(7)M(6:3)N(2:0) 0x00, 0x00, 0x00, 0x00 2 60 DEFAULT VALUE 0x01 I C M and N 4 0x02 Status 8 See Status Register 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x04 I C RAM Load Control 8 See I2C RAM Load Control Register 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x05 I2C RAM Load Data 8 See I2C RAM Load Data Register 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x06 PEEK/POKE Control 4 See PEEK/POKE Control Register 0x00, 0x00, 0x00, 0x00 0x07 PEEK/POKE Data 8 See PEEK/POKE Data Register 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x08 Silicon Version 4 ver(31:24), ver(23:16), ver(15:8), ver(7:0) 0x00, 0x00, 0x00, 0x02 0x09 Mute Control 4 See Mute Control Register 0x00, 0x00, 0x00, 0x00 0x0a Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0b Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0c GPIO Control 4 See GPIO Control Register 0x00, 0x00, 0x00, 0x00 0x0d Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0e Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x0f Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x10 Powerdown Control 4 See Powerdown Control Register 0x00, 0x00, 0x00, 0x00 0x11 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x12 A-MUX Control 4 See A-MUX Control Register 0x00, 0x00, 0x00, 0x00 0x13 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x14 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x15 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x03 (1) CONTENTS 2 Shades cells indicate common to basic and advanced modes. Unshaded cells indicate advanced mode only. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 21. I2C Register Map(1) (continued) SUB ADDRESS REGISTER BYTES 0x16 SPDIF Control 0x17 Reserved 0x18 CONTENTS DEFAULT VALUE 4 See SPDIF Control Register 0x00, 0x00, 0x00, 0x00 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x19 Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1a Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1b Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x1c Reserved 8 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x01 0x47, 0xae, 0x00, 0x00 0x1d DC Dither 4 See DC Dither Register 0x00, 0x00, 0x00, 0x01 0x1e DSP Program Start Address 4 See DSP Program Start Address Register 0x00, 0x00, 0x00, 0x00 0x1f Reserved 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x20 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x21 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x22 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x23 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x24 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x25 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x26 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x27 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x28 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x29 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2a Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2b Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2c Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2d Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2e Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x2f Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x30 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x31 Unused 4 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x32 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x33 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x34 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x35 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x36 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x37 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x38 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x39 Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3a Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3b Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3c Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0x3d Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0xfe Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 0xff Unused 16 u(31:24), u(23:16), u(15:8), u(7:0) 0x00, 0x00, 0x00, 0x00 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 61 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com SAP/Clock Setting Register (0x00) The SAP/Clock Setting register is used to configure the device as a clock master/slave, as well as specify the desired format of the digital audio ports. This register is four bytes in length. Table 22. SAP/Clock Setting Register BIT BIT 31 30 29 28 27 26 25 0 0 0 0 0 0 0 23 22 21 20 19 18 17 24 DESCRIPTION CM/S Clock master/slave select Unused 16 Unused ON BIT 15 14 13 OW1 OW0 12 11 10 9 SAP output normalization 8 0 Unused Digital audio output word size 0 BIT 7 6 5 OM1 OM0 0 4 3 Unused IW1 IW0 2 1 Digital audio input word size 0 0 Unused Digital audio output format 0 0 Unused IM1 IM0 Digital audio input format Table 23. Clock Master/Slave Select (1) (1) CLOCK MASTER/SLAVE SELECT CMS Master 1 Slave 0 Default values are shown in italics. Table 24. Digital Audio Port Normalization (1) (1) DIGITAL AUDIO PORT NORMALIZATION ON Enable 1 Disable 0 Default values are shown in italics. Bits 9–8 (IW1 and IW0) define the data word size for the input SAP. Bits 13–12 (OW1 and OW0) define the data word size for the output SAP. Table 25. Audio Data Word Size (1) (1) 62 DIGITAL AUDIO I/O WORD SIZE IW1/OW1 IW0/OW0 16 bit 0 0 20 bit 0 1 24 bit 1 0 – 1 1 Default values are shown in italics. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 26. Audio Data Format (1) (1) DIGITAL AUDIO I/O FORMAT IM1/OM1 IM0/OM0 Left-justified 0 0 Right-justified 0 1 I2S 1 0 – 1 1 Default values are shown in italics. Status Register (0x02) The Status register provide memory load information. When a memory load error for a particular memory occurs, the memory load error bit for that memory is set to 1. When a memory load is successful for a particular memory, the memory load error bit for that memory is set to 0. The host must check this load status after memory load. The host can clear all load error status by writing 0 to bits D40–D32 of this register. Table 27. Status Register BIT BIT BIT BIT 63 62 61 60 59 58 57 56 DESCRIPTION 0 0 0 0 0 0 0 0 Reserved 55 54 53 52 51 50 49 48 0 0 0 0 0 0 0 47 46 45 44 43 42 41 40 0 0 0 0 0 0 0 0 39 38 37 36 35 34 33 32 x x x x x x x 1 M8051 program memory load error x x x x x x 1 x M8051 external memory load error x x x x x 1 x x DSP program memory load error x x x x 1 x x x DSP coefficient memory load error x x x 1 x x x x DSP data memory load error Reserved Unsused x 1 x x x x x x Invalid memory select 1 x x x x x x x End of load header error 1 1 1 1 1 1 1 1 No EEPROM 0 0 0 0 0 0 0 0 No error 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 BIT 23 22 21 20 19 18 17 0 0 0 0 0 0 0 BIT 15 14 13 12 11 10 9 BIT Reserved 16 Reserved 8 0 BIT 7 Reserved 6 5 4 3 2 1 0 0 Reserved ABSY Analog busy flag 0 Reserved 0 Reserved 0 Reserved 0 Reserved 2 BUSE I C bus error 0 Reserved Bits 40–32 define the memory load error status on EEPROM download and slave download. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 63 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 28. Analog Busy (1) (1) ANALOG BUSY FLAG ABSY Analog is busy 1 Analog not busy 0 Default values are shown in italics. Analog control sequence takes time (maximum approximately 500 ms for headphone power up). This busy flag indicates whether the analog control sequence is running or not. Table 29. I2C Bus Error (1) (1) I2C BUS ERROR BUSE Bus error 1 No bus error 0 Default values are shown in italics. 2 If an I C bus error occurs, this flag will be set. Only the host microcontroller can clear this flag by writing 0 to this bit. I2C bus error status is read from ESFR 0xC5, bit 6, and is cleared by ESFR 0xC7, bit 6. I2C RAM Load Control and Data Registers (0x04 and 0x05) The I2C memory load port permits the system controller to load the TAS3208 memories as an alternative to having the TAS3208 load its memory from an external EEPROM. The transfer is performed by writing to two I2C registers. The first register is a 8-byte register than holds the checksum, memory to be written, starting address, and number of data bytes to be transferred. The second register holds eight bytes of data. The memory load operation starts with the first register being set. Then the data is written into the second register using the format shown. After the last data byte is written into the second register, an additional two bytes are written, which constrain the 2-byte checksum. At that point, the transfer is complete and status of the operation is reported in the Status register. NOTE Once the microprogram memory has been loaded, further updates to this memory are inhibited until the device is reset. When the first I2C slave download register is written by the system controller, the TAS3208 updates the Status register by setting a error bit to indicate an error for the memory type that is being loaded. This error bit is reset when the operation complete and a valid checksum has been received. For example, when the microprogram memory is being loaded, the TAS3208 will set a microprogram memory error indication in the Status register at the start of the sequence. When the last byte of the microprogram memory and checksum is received, the TAS3208 will clear the microprogram memory error indication. This enables the TAS3208 to preserve any error status indications that occur as a result of incomplete transfers of data/ checksum error during a series of data and program memory load operations. The checksum is always contained in the last two bytes of the data block. The I2C slave download is terminated when a termination header with a zero-length byte count field is received. 64 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 30. I2C RAM Load Control Register (0x04) BYTE 1–2 DATA BLOCK FORMAT SIZE Checksum code NOTES 2 bytes Checksum of bytes 2 through N + 8, If this is a termination header, this value is 00 00. 3 Memory to be loaded 1 byte 0: Microprogram memory 1: Micro external data memory 2: DSP program memory 3: DSP coefficient memory 4: DSP data memory 5–15: Reserved 4 Unused 1 byte Reserved 6–7 Starting TAS3208 memory address 2 bytes If this is a termination header, this value is 00 00. 7–8 Number of data bytes to be transferred 2 bytes If this is a termination header, this value is 00 00. Table 31. I2C RAM Load Data Register (0x05) BYTE 8-BIT DATA 24-BIT DATA 28-BIT DATA 48-BIT DATA 55-BIT DATA 1 Datum 1 D7–D0 2 Datum 2 D7–D0 D23–D16 D23–D16 3 Datum 3 D7–D0 D15–D8 D15–D8 D47–D40 D47–D40 4 Datum 4 D7–D0 D7–D0 D7–D0 D39–D32 D39–D32 5 Datum 5 D7–D0 XXXX D27–D24 D31–D24 D31–D24 6 Datum 6 D7–D0 D23–D16 D23–D16 D23–D16 D23–D16 7 Datum 7 D7–D0 D15–D8 D15–D8 D15–D8 D15–D8 8 Datum 8 D7–D0 D7–D0 D7–D0 D7–D0 D7–D0 XXXX D27–D24 X D54–D48 PEEK/POKE Control and Data Registers (0x06 and 0x07) The PEEK/POKE Control (Table 32) and PEEK/POKE Data (Table 33) registers allow the user to access the internal resources of TAS3208. Figure 40 shows the I2C transaction for the PEEK/POKE registers. Table 32. PEEK/POKE Control Register (0x06) BIT BIT BIT BIT 31 30 29 28 27 26 25 24 DESCRIPTION 0 0 0 0 0 0 0 0 Unused 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 1 DSP coefficient memory load error 0 0 0 0 0 0 1 0 DSP data memory load error 0 0 0 0 0 0 1 1 DSP delay memory 0 0 0 0 0 1 0 0 M8051 internal data memory 0 0 0 0 0 1 0 1 M8051 external data memory 0 0 0 0 0 1 1 0 Extended special function registers 0 0 0 0 0 1 1 1 M8051 program memory DSP program memory 0 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Memory address MSB Memory address LSB Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 65 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 33. PEEK/POKE Data Register (0x07) BIT BIT BIT BIT BIT BIT BIT 63 62 61 60 59 58 57 56 DESCRIPTION D63 D62 D61 D60 D59 D58 D57 D56 Data to be read or written 55 54 53 52 51 50 49 48 D55 D54 D53 D52 D51 D50 D49 D48 47 46 45 44 43 42 41 40 D47 D46 D45 D44 D43 D42 D41 D40 39 38 37 36 35 34 33 32 D39 D38 D37 D36 D35 D34 D33 D32 31 30 29 28 27 26 25 24 D31 D30 D29 D28 D27 D26 D25 D24 23 22 21 20 19 18 17 16 D23 D22 D21 D20 D19 D18 D17 D16 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 BIT Data to be read or written Data to be read or written Data to be read or written Data to be read or written Data to be read or written Data to be read or written Data to be read or written Memory Select and Address S Slave address +W ACK Sub address (0x06) ACK 00000000 ACK memory section ACK address (MS Byte) ACK address (LS Byte) ACK P ACK Peek (Read) S Slave address +W ACK S Slave address +W ACK Sub address (0x07) ACK P D63–D56 ACK D55–D48 ACK D47–D40 ACK D39–D32 D31–D24 ACK D23–D16 ACK D15–D8 ACK D7–D0 D63–D56 ACK D55–D48 ACK D47–D40 ACK D39–D32 D31–D24 ACK D23–D16 ACK D15–D8 ACK D7–D0 NAK P Poke (Write) S Slave address +W ACK Sub address (0x07) ACK ACK NAK P Figure 40. I2C Transaction for PEEK/POKE 66 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Mute Control Register (0x09) Table 34. Mute Control Register BIT BIT BIT 31 30 29 28 27 26 25 24 DESCRIPTION 0 0 0 0 0 0 0 0 Unused 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 AMX1 AMX0 Unused Unused Analog MUX out (LINEOUT1) SD2 SD2 SDOUT2/SPDIFOUT SD1 SD1 BIT 7 6 DAC1 DAC1 5 4 3 DAC2 DAC2 2 1 SDOUT1 0 DAC1 DAC2 DAC3 DAC3 DAC3 DIT DIT DIT Table 35. Mute (1) (1) MUTE MUTE[1] MUTE[0] Hardware controlled 0 0 Force mute off 0 1 Force mute on 1 0 Default values are shown in italics. GPIO Control Register (0x0c) Table 36. GPIO Control Register BIT 31 30 29 28 27 26 25 24 DESCRIPTION WDE Watchdog timer 0 0 0 Unused IO2 GPIO2 input/output value IO1 GPIO1 input/output value DIR2 GPIO2 direction DIR1 BIT BIT BIT 23 22 21 20 19 18 17 16 x x x x x x x x 15 14 13 12 11 10 9 8 x x x x x x x x 7 6 5 4 3 2 1 0 y y y y y y y y GPIO1 direction GPIOMICROCOUNT MSB GPIOMICROCOUNT LSB GPIO_Sampling_Interval GPIOMICROCOUNT sets the number of micro clock cycles for Timer 0 interrupt. In Timer 0 interrupt service routine, the watchdog timer is reset if it is enabled. The default value for this counter is 0x5820, which corresponds to a period 1.25 ms. Table 37. Watchdog Timer Enable (1) WATCHDOG TIMER WDE Enable 0 (1) Default values are shown in italics. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 67 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 37. Watchdog Timer Enable(1) (continued) WATCHDOG TIMER WDE Disable 1 Table 38. GPIO Direction (1) (1) GPIOx DIRECTION DIRx Output 0 Input 1 Default values are shown in italics. Powerdown Control Register (0x10) Table 39. Powerdown Control Register BIT BIT BIT BIT 31 30 29 28 27 26 25 24 DESCRIPTION 0 0 0 0 0 0 0 0 Unused 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Unused Unused DIT DIT reset DAC 3 DAC3 DAC 2 DAC2 DAC 1 DAC1 ADC AMUX + AAF + ADC 0 Unused 0 Unused AMX1 AMUX1 + LineAmp1 Table 40. Powerdown (1) (1) 68 POWERDOWN PD Powerdown and disable 0 Powerup and enable 1 Default values are shown in italics. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com A-MUX Control Register(0x12) Table 41. A-MUX Control Register BIT BIT BIT BIT 31 30 29 28 27 26 25 24 DESCRIPTION x x x x 1 1 1 1 Reserved x x x x 1 1 1 0 Reserved x x x x 1 1 0 1 Reserved x x x x 1 1 0 0 Reserved x x x x 1 0 1 1 DAC x x x x 1 0 1 0 Analog MUX line 10 select x x x x 1 0 0 1 Analog MUX line 9 select x x x x 1 0 0 0 Analog MUX line 8 select x x x x 0 1 1 1 Analog MUX line 7 select x x x x 0 1 1 0 Analog MUX line 6 select x x x x 0 1 0 1 Analog MUX line 5 select x x x x 0 1 0 0 Analog MUX line 4 select x x x x 0 0 1 1 Analog MUX line 3 select x x x x 0 0 1 0 Analog MUX line 2 select x x x x 0 0 0 1 Analog MUX line 1 select 0 0 0 0 0 0 0 0 MUTE 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 x x x x 1 1 1 1 Reserved x x x x 1 1 1 0 Reserved x x x x 1 1 0 1 Reserved x x x x 1 1 0 0 Reserved x x x x 1 0 1 1 DAC x x x x 1 0 1 0 Analog MUX line 10 select x x x x 1 0 0 1 Analog MUX line 9 select x x x x 1 0 0 0 Analog MUX line 8 select x x x x 0 1 1 1 Analog MUX line 7 select x x x x 0 1 1 0 Analog MUX line 6 select x x x x 0 1 0 1 Analog MUX line 5 select x x x x 0 1 0 0 Analog MUX line 4 select x x x x 0 0 1 1 Analog MUX line 3 select x x x x 0 0 1 0 Analog MUX line 2 select x x x x 0 0 0 1 Analog MUX line 1 select 0 0 0 0 0 0 0 0 MUTE Unused Unused Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 69 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com SPDIF Control Register (0x16) Table 42. SPDIF Control Register BIT 31 30 29 28 27 26 25 24 DESCRIPTION CP Copyright flag EMP BIT 23 22 SR SR b24 b25 Pre-emphasis flag CLKAC CLKA C b28 b29 WL3 WL2 WL1 WL0 21 20 19 18 17 16 0 0 0 0 0 0 Clock accuracy Sample word length Sampling rate VL Left-channel validity flag VR BIT Right-channel validity flag SRC# SRC# SRC# SRC# b19 b18 b17 b16 8 15 14 13 12 11 10 9 Cat Cat Cat Cat Cat Cat Cat b8 b9 b10 b11 b12 b13 b14 7 6 5 4 3 2 1 0 0 0 0 0 0 0 MUX1 MUX0 Source channel number Category code 0 L BIT Generation status Unused SPDIF MUX Table 43. Copyright Flag (1) (1) COPYRIGHT FLAG CP Copy prohibited 0 Copy permitted 1 Default values are shown in italics. Table 44. Pre-Emphasis Flag (1) (1) PRE-EMPHASIS FLAG EMP No pre-emphasis 0 50/15 µs pre-emphasis 1 Default values are shown in italics. Table 45. Sample Word Length SAMPLE WORD LENGTH WLx 24-bit sample word length 0 Table 46. Sampling Rate 70 SAMPLING RATE b24 b25 48 kHz 0 1 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Table 47. Validity Flag (1) (1) VALIDITY FLAG Vx Valid 0 Not valid 1 Default values are shown in italics. Table 48. Channel Source Number CHANNEL SOURCE NUMBER b19 b18 b17 b16 Channel 2 0 0 1 0 Table 49. Category Code CATEGORY CODE b8 b9 b10 b11 b12 b13 b14 Digital sound processor 0 1 0 1 0 1 0 Table 50. Generation Status GENERATION STATUS Vx Gen 1 or higher 0 Original 1 Table 51. SDOUT/SPDIF MUX (1) (1) SDOUT/SPDIF MUX MUX1 MUX2 SDOUT2 0 0 SPDIF Tx 0 1 SPDIF In 1 – Default values are shown in italics. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 71 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com DC Dither Register (0x1d) Table 52. DC Dither Register BIT BIT BIT BIT 31 30 29 28 27 26 25 24 DESCRIPTION 0 0 0 0 0 0 0 0 Unused 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Unused Unused Unused ON DC dither enable Table 53. DC Dither Enable (1) DC DITHER ENABLE ON Disable 0 Enable 1 (1) Default values are shown in italics. DSP Program Start Address Register (0x1e) The DSP instruction execution loops each Fs cycle. At the beginning of the Fs cycle, the DSP instruction pointer is set to the starting address specified in the 12 LSBs. The maximum address is the end address of DSP instruction address 3327. Table 54. DSP Program Start Address Register BIT 31 0 0 0 0 0 0 BIT 23 22 21 20 19 18 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 x x x x 7 6 5 4 3 2 1 0 x x x x x x x x BIT BIT 72 30 29 28 27 26 25 24 DESCRIPTION 0 0 Unused 17 16 Submit Documentation Feedback Unused Starting address MSB Starting address LSB Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION Headphone L Line Out 1 R 2 1 47uF 2 10K 1 2 22uF 10K 2 1 2 1 22uF 2 10K 1 2 22uF 10K 2 1 2 1 22uF 2 10K 1 2 22uF 10K AVDD_LI Line Out 1 L AVDD_LI AVDD_LI AVDD_REF RESERVED LINEIN6L RESERVED AVSS_LI SDIN3 LINEIN5R SDIN2 LINEIN5L SDIN1 AVDD_LI LRCLKIN LINEIN4R 2 1uF 1 2 1uF 73 1 2 24k AVDD_DAC 1 1 0.1 uF 2 0.1 uF 0.1 uF 2 1 1 0.1 uF 0.1 uF 72 AVDD 1 1 2 1 2 67 1 33K 33K 2 1 4.7uF 4.7uF 2 66 1 2 1 2 64 1 33K 33K 2 1 4.7uF 4.7uF 2 63 1 2 1 2 61 1 33K 33K 2 1 4.7uF 4.7uF 2 60 1 2 1 2 58 1 33K 33K 2 1 4.7uF 4.7uF 2 57 1 2 1 2 55 1 33K 33K 2 1 4.7uF 4.7uF 2 54 1 2 1 2 52 1 33K 33K 2 1 4.7uF 4.7uF 2 51 1 2 1 2 65 62 59 56 53 33K Line In 10 R AVDD_HP 4.7uF 2 Line In 10 L 0.1 uF Line In 9 R Line In 9 L AVDD_LI Line In 8 R AVDD Line In 8 L AVDD_HP 1 68 AVDD_ADC Line In 7 R Line In 7 L 4.7uF 2 69 4.7uF 2 2 1 1 33K 2 70 1 71 LINEIN3R LINEIN3L 1 74 0.1 uF 0.1 uF AVDD_LI Line In 6 R Line In 6 L Line In 5 R Line In 5 L AVDD_LI Line In 4 R Line In 4 L 4.7uF 50 49 AVSS_LI LINEIN2R 48 LINEIN2L 47 46 AVDD_LI LINEIN1L LINEIN1R 45 44 43 42 27 26 AVSS_ESD LINEIN4L VR_DIG2 SCLKIN 75 10uF 2 2 AVDD_REF TEST TEST TEST TEST AVSS_LO LINEOUT1L LINEOUT1R DACOUT1L DACOUT1R DACOUT2L DACOUT2R AVSS_DAC AVDD_HP AVDD_DAC HPOUTL HPOUTR AVSS_HP AVDD_HP XTAL_IN AVSS_ESD XTAL_OUT DVDD1 AVDD_OSC LINEIN6R DVSS5 25 AVDD_LI RESERVED 41 24 LINEIN7L RESERVED MCLKIN SCLK_IN 23 SPDIF_IN 40 L/RCLK_IN 22 LINEIN7R DVDD4 SDIN1 AVSS_LI DVSS2 DVSS4 SDIN2 21 VR_DIG1 39 20 SDIN3 TAS3208PZP 38 19 LINEIN8L /RESET 2 4.7uF DVDD2 /MUTE 18 LINEIN8R U1 37 17 AVDD_LI SDOUT2/SPDIF_OUT GPIO2 1 SPDIF SDOUT1 36 16 LINEIN9L 35 15 LINEIN9R SCLKOUT GPIO1 14 AVSS_LI LRCLKOUT CS DVDD2 MCLKOUT 34 13 LINEIN10L I2C_SCL1 12 RESERVED 33 11 SDOUT1 SDOUT2/SPDIFOUT LINEIN10R 32 10 SCLK_OUT AVDD_ADC RESERVED I2C_SDA1 9 L/RCLK_OUT RESERVED I2C_SCL2 MCLK_OUT AVSS_ADC/REF 31 8 RESERVED I2C_SDA2 7 BIAS_REF 30 6 BG_REF RESERVED 29 5 V1P5_REF /VREG_EN DVDD3 4 DVSS1 DVSS3 3 28 2 Power_PAD 1 VR_ANA 1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 2 101 AVDD_REF 4.7uF AVDD_ADC AVDD 1 1 DVDD1 Line Out 1 R 1 2 AVDD_HP Line Out 1 L 1 AVDD_HP AVDD_HP Line Out 1 R 1 1 AVDD_DAC 1 Line Out 1 L 147uF 1.00M 2 1 2 1 22uF 2 2 2 1 10pF 24.576MHz 10pF 2 2 2 10K 2 1 2 1 1 1 2 10K 2 1 Headphone R MCLK_IN 1 DVDD3 DVDD4 MASTER_SCL 2 MASTER_SDA 4.7uF 1 33K 2 1 4.7uF 2 1 33K 2 1 4.7uF 2 1 33K 2 1 4.7uF 2 1 33K 2 1 4.7uF 2 1 33K 2 1 4.7uF 2 1 33K 2 1 4.7uF 2 AVDD_LI SLAVE_SDA SLAVE_SCL Chip_Select GPIO1 GPIO2 nMUTE Line In 3 R Line In 3 L Line In 2 R Line In 2 L Line In 1 R Line In 1 L nRESET DVDD 4.7uF 0.1 uF 1 1 DVDD2 4.7uF 2 0.1 uF 1 1 1 4.7uF DVDD1 2 0.1 uF 2 1 DVDD4 2 1 4.7uF 2 2 1 DVDD3 DVDD 2 DVDD 2 DVDD 0.1 uF Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 73 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) TAS3208IPZP ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TAS3208IPZP TAS3208PZP ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -20 to 70 TAS3208PZP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of